Philips SAA7157T, SAA7157 Datasheet
INTEGRATED CIRCUITS
DATA SH EET
SAA7157
Clock signal generator circuit for
digital TV systems (SCGC)
Product specification
File under Integrated Circuits, IC02
May 1992
Philips Semiconductors Product specification
Clock signal generator circuit for digital
SAA7157
TV systems (SCGC)
FEATURES
• Clock generation suitable for digital TV systems (line-locked)
• PLL frequency multiplier to generate 4 times of input frequency
• Dividers to generate clocks LL1.5A, LL1.5B, LL3A and LL3B (4th and 2nd multiples of input frequency)
• PLL mode or VCO mode selectable
• Reset control and power fail detection
• Suitable for applications with feature box and picture memory
GENERAL DESCRIPTION
The SAA7157 generates all clock signals required for a digital TV system suitable for the SAA715x family and the
SAA7199B (DENC). The circuit operates in either the phase-locked loop mode (PLL) or voltage controlled oscillator
mode (VCO).
QUICK REFERENCE DATA
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
V
V
I
DDA
I
DDD
V
f
i
V
V
T
DDA
DDD
LFCO
I
O
amb
analog supply voltage (pin 5) 4.5 5.0 5.5 V
digital supply voltage (pins 8, 17) 4.5 5.0 5.5 V
analog supply current 3 - 9 mA
digital supply current 10 - 60 mA
LFCO input voltage
(peak-to-peak value) 1 - V
DDA
V
input frequency range 6.0 - 7.25 MHz
input voltage LOW
input voltage HIGH
output voltage LOW
output voltage HIGH
0
2.0-0
2.6--
0.8
V
0.6
V
DDD
DDD
V
V
V
V
operating ambient temperature range 0 - 70 °C
ORDERING INFORMATION
EXTENDED
TYPE NUMBER
PINS PIN POSITION MATERIAL CODE
SAA7157 20 DIL plastic SOT146
SAA7157T 20 mini-pack (SO20) plastic SOT163A
Note
1. SOT146-1; 1996 December 17.
2. SOT163-1; 1996 December 17.
May 1992 2
PACKAGE
(1)
(2)
Philips Semiconductors Product specification
Clock signal generator circuit for digital TV
systems (SCGC)
handbook, full pagewidth
MS
LFCO
LFCO2
CE
1
LOOP
FILTER
MS = LOW
PHASE
DETECTOR
11
19
2
PRE-FILTER
AND
PULSE
SHAPER
V
DDAVDDD1VDDD2
5 8 17
VCO
SAA7157
FREQUENCY
DIVIDER
1 : 2
POWER-ON
RESET
LFCOSEL
316 4 6, 9, 13, 18
PORD
FREQUENCY
DIVIDER
1 : 2
DELAY
V
SSA
V
SSD
10
14
20
15
12
MEH452
SAA7157
7
LL1.5A
(LL27A)
LL1.5B
(LL27B)
LL3A
LL3B
CREF
RESN
Fig.1 Block diagram.
FUNCTIONAL DESCRIPTION
The SAA7157 generates all clock signals required for a
digital TV system suitable for the SAA715x family
consisting of an 8-bit analog-to-digital converter (ADC8),
digital video multistandard decoder (DMSD2) and video
enhancement and D/A processor circuit (VEDA). Optional
extras (feature box, video memory etc.) can be driven via
external buffers, advantageous for a digital TV system
based on display standard conversion concepts.
The 6.75 MHz input signal LFCO (triangular waveform)
coming from the DMSD or LFCO2 is multiplied to 27 MHz
by the PLL (including phase detector, loop filter, VCO and
frequency divider) and output on LL1.5A (pin 7) and
LL1.5B (pin 10). The 13.5 MHz frequencies are generated
by dividers using ratio of 1:2 and are output on LL3A (pin
14) and LL3B (pin 20).
The rectangular output signals have 50% duty factor.
Outputs with equal frequency may be connected together
externally. The clock outputs go HIGH during power-on
reset (and chip enable) to ensure that no output clock
signals are available before the PLL has locked-on.
Mode select MS
The LFCO input signal is directly connected to the VCO at
MS = HIGH. The circuit operates as an oscillator and
frequency divider. This function is not tested.
Source select LFCOSEL
Line frequency control signal (LFCO) is selected by
LFCOSEL input.
LFCOSEL = LOW:
signal from LFCO (pin 11) is selected.
LFCOSEL = HIGH:
signal from LFCO2 (pin 19) is selected.
This function is not tested.
Chip enable CE
The buffer outputs are enabled and RESN is set to HIGH
by
CE = HIGH (Fig.4).
CE = LOW sets the clock outputs HIGH and RESN output
LOW.
May 1992 3
Philips Semiconductors Product specification
Clock signal generator circuit for digital TV
SAA7157
systems (SCGC)
CREF output
TV2 digital clock reference output signal. Clock qualifier signal to TV system with 2 times of LFCO or LFCO2 frequency.
Power-on reset
Power-on reset is activated at power-on, when the supply voltage decreases below 3.5 V (Fig.4) or when chip enable is
done. The indicator output RESN is LOW for a time determined by capacitor on pin 3. The RESN signal can be applied
to reset other circuits of this digital TV system.
The LFCO or LFCO2 input signals have to be applied before RESN becomes HIGH.
PINNING
SYMBOL PIN DESCRIPTION
MS 1 mode select input (LOW = PLL mode)
CE 2 chip enable /reset (HIGH = outputs enabled)
PORD 3 power-on reset delay, dependent on external capacitor
V
SSA
V
DDA
V
SSD1
LL1.5A 7 line-locked clock output signal 1.5A (4 times f
V
DDD1
V
SSD2
LL1.5B 10 line-locked clock output signal 1.5B (4 times f
LFCO 11 line-locked frequency control input signal 1
RESN 12 reset output (active-LOW, Fig.4)
V
SSD3
LL3A 14 line-locked clock output signal 3A (2 times f
CREF 15 clock reference output, qualifier signal (2 times f
LFCOSEL 16 LFCO source select (LOW = LFCO selected)
V
DDD2
V
SSD4
LFCO2 19 line-locked frequency control input signal 2
LL3B 20 line-locked clock output signal 3B (2 times f
4 analog ground (0 V)
5 analog supply voltage (+5 V)
6 digital ground 1 (0 V)
8 digital supply voltage 1 (+5 V)
9 digital ground 2 (0 V)
13 digital ground 3 (0 V)
17 digital supply voltage 2 (+5 V)
18 digital ground 4 (0 V)
LFCO
(1)
LFCO
LFCO
LFCO
(1)
)
)
)
LFCO
)
)
Note
1. MS and LFCO2 functions are not tested. LFCO2 is a multiple of horizontal frequency.
May 1992 4
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