Philips SAA7152 Datasheet
INTEGRATED CIRCUITS
DATA SH EET
SAA7152
Digital Video Comb Filter (DCF)
Product specification
File under Integrated Circuits, IC02
August 1996
Philips Semiconductors Product specification
Digital Video Comb Filter (DCF) SAA7152
FEATURES
• Comb filter circuit for luminance and chrominance
separation
• Applicable for standards
– PAL B/G, M and N
– PAL 4.43 (525 lines, 60 Hz)
– NTSC M and N
– NTSC 4.43 (50 and 60 Hz)
• Luminance and chrominance bypasses with short delay
in case of no filtering
• Line-locked system clock; CCIR-compatible
• I2C-bus controlled
GENERAL DESCRIPTION
The CMOS digital comb filter circuit is located between
video analog-to-digital converters and the video
multistandard decoder SAA7151B (not applicable for
SAA7191B). The two-dimensional filtering is only
appropriate for standard signals from a source with
constant phase relationship between subcarrier signal and
horizontal frequency. The comb-filter has to be switched
off for VTR-signals and for separate VBS and C signals. In
VCR and S-Video operation the luminance low-pass and
the chrominance bandpass parts can still be used for noise
reduction purposes. The processing delay is:
21 × LL27 clocks in active mode, or
3 × LL27 in short delay bypass mode (BYPS = 1)
QUICK REFERENCE DATA
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
V
DD
I
P
V
i
V
o
supply voltage (pins 11, 34, 44) 4.5 5.0 5.5 V
total supply current − 85 180 mA
input levels TTL-compatible
output levels TTL-compatible
LL27 typical system clock frequency − 27 − MHz
T
amb
operating ambient temperature range 0 − 70 °C
ORDERING INFORMATION
EXTENDED
TYPE NUMBER
PINS PIN POSITION MATERIAL CODE
PACKAGE
SAA7152 44 PLCC plastic SOT187
Note
1. SOT187-2; 1997 January 06.
August 1996 2
(1)
Philips Semiconductors Product specification
Digital Video Comb Filter (DCF) SAA7152
BLOCK DIAGRAM
handbook, full pagewidth
CVBS(7 -0)
CIN(7 -0)
LL27
2
I C-bus
SDA
SCL
20 to 13
10 to 3
2
23
24
SAA7152
INPUT
INTERFACE
CSEL
CLOCK
BUFFER
control bits
2
I C-BUS
CONTROL
luminance bypass
clk
+5 V
V
DDD1
NLIN,
LLEN
LINE
DELAY 1
BANDPASS
FILTER 2
LOW-PASS
FILTER
chrominance bypass
11, 34, 44
CFRQ
TAPS,
CFRQ
to V
DDD3
CFRQ
BANDPASS
FILTER 1
LINE
DELAY 2
COMB FILTER
LOGIC
(MED)
ADDER
AND
LIMITER
NLIN,
LLEN
MULTIPLEXER
CCMB,
TAPS
YCMB
BYPS
OUTPUT
INTERFACE
REGISTER
25 to 32
35 to 42
YOUT(7-0)
COUT(7-0)
RESN
1
21
SP AP
22
12, 33, 43
V to V
SSD1
SSD3
MEH423-1
Fig.1 Block diagram.
August 1996 3
Philips Semiconductors Product specification
Digital Video Comb Filter (DCF) SAA7152
PINNING
SYMBOL PIN DESCRIPTION
RESN 1 reset input; active low
LL27 2 line-locked system clock input (27 MHz)
CIN0 3
CIN1 4
CIN2 5
CIN3 6
CIN4 7
CIN5 8
CIN6 9
CIN7 10
V
V
DD1
SS1
11 +5 V supply input
12 ground 1 (0 V)
CVBS0 13
CVBS1 14
CVBS2 15
CVBS3 16
CVBS4 17
CVBS5 18
CVBS6 19
CVBS7 20
SP 21 connected to ground (shift pin for testing)
AP 22 connected to ground (action pin for testing)
SDA 23 I
SCL 24 I
YOUT7 25
YOUT6 26
YOUT5 27
YOUT4 28
YOUT3 29
YOUT2 30
YOUT1 31
YOUT0 32
V
V
SS2
DD2
33 ground 2 (0 V)
34 +5 V supply input 2
chrominance input data bits CIN0 to CIN7
CVBS input data bits 0 to 7
2
C-bus data line
2
C-bus clock line
luminance (Y) output data bits 7 to 0
August 1996 4
Philips Semiconductors Product specification
Digital Video Comb Filter (DCF) SAA7152
SYMBOL PIN DESCRIPTION
COUT7 35
COUT6 36
COUT5 37
COUT4 38
COUT3 39
COUT2 40
COUT1 41
COUT0 42
V
V
SS3
DD3
43 ground 3 (0 V)
44 +5 V supply input 3
chrominance (C) output data bits 7 to 0
handbook, full pagewidth
COUT2
COUT1
COUT0
V
SS3
V
DD3
RESN
LL27
CIN0
CIN1
CIN2
CIN3
SS2
DD2
V
12
V
33 29303132
13 17161514
YOUT0
YOUT1
COUT3
39 3435363738
40
41
42
43
44
1
2
3
4
5
6
711109
COUT4
8
COUT5
COUT7
COUT6
SAA7152
YOUT2
YOUT3
28
27
26
25
24
23
22
21
20
19
18
YOUT4
YOUT5
YOUT6
YOUT7
SCL
SDA
AP
SP
CVBS7
CVBS6
CVBS5
CIN4
CIN5
CIN6
CIN7
V
DD1
V
SS1
Fig.2 Pin configuration.
August 1996 5
CVBS0
CVBS1
CVBS2
CVBS3
CVBS4
MEH422
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