13.4Repairing soldered joints
14DEFINITIONS
15LIFE SUPPORT APPLICATIONS
16PURCHASE OF PHILIPS I2C COMPONENTS
1998 Apr 092
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
1FEATURES
1.1Video processing
• Full size, full speed video delivery to and from the frame
buffer or virtual system memory enables various
processing possibilities for any external PCI device
• Full bandwidth PCI-bus master write and read (up to
132 Mbytes/s)
• Virtual memory support (4 Mbytes per DMA channel)
• Processing of maximum 4095 active samples per line
and maximum 4095 lines per frame
• Vanity picture (mirror) for video phone and video
conferencing applications
• Video flip (upside down picture)
• Colour space conversion with gamma correction for
different kinds of displays
• Chroma Key generation and utilization
• Pixel dithering for low resolution video output formats
• Brightness, contrast and saturation control
• Video and Vertical Blanking Interval (VBI) synchronized
programming of internal registers with Register
Programming Sequencer (RPS), ability to control two
asynchronous data streams simultaneously
• Rectangular clipping of frame buffer areas minimizes
PCI-bus load
• Random shape mask clipping protects selectable areas
of frame buffer
• 3 × 128 Dword video FIFO with overflow detection and
‘graceful’ recovery.
1.2Audio processing
• Time Slot List (TSL) processing for flexible control of
audio frames up to 256 bits on 2 asynchronous
bidirectional digital audio interfaces simultaneously
(4 DMA channels)
• Video synchronous audio capture, e.g. for sound cards
• Various synchronization modes to support I
different audio and DSP data formats
• Audio input level monitoring enables peak control via
software
• Programmable bit clock generation for master and slave
applications.
2
S and other
SAA7146A
1.3Scaling
• Scaling of video pictures down to randomly sized
windows (vertical down to 1 : 1024; horizontal down to
1 : 256)
• High Performance Scaler (HPS) offers two-dimensional,
phase correct data processing for improved signal
quality of scaled video data, especially for compression
applications
• Horizontal and vertical FIR filters with up to 65 taps
• Horizontal upscaling (zoom) supports e.g. CCIR to
square pixel conversion
• Additional Binary Ratio Scaler (BRS) supports CIF and
QCIF formats, especially for video phone and video
conferencing.
1.4Interfacing
• Dual D1 (8-bit, CCIR 656) video I/O interface
• DMSD2 compatible (16-bit YUV) video input interface
• Supports various packed (pixel dithering) and planar
video output formats
• Data Expansion Bus Interface (DEBI) for interfacing with
e.g. MPEG or JPEG decoders with Intel (ISA like) and
Motorola (68000 like) protocol style, capability for
immediate and block mode (DMA) transfers with up to
23 Mbytes/s peak data rate
• 5 digital audio I/O ports
• 4 independent user configurable General Purpose I/O
Ports (GPI/O) for interrupt and status processing
• PCI interface (release 2.1)
2
• I
C-bus interface (bus master).
1998 Apr 093
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
SAA7146A
Scaler and PCI circuit (SPCI)
1.5General
• Subsystem (board) vendor ID support for board
identification via software driver
• Internal arbitration control
• Diagnostic support and event analysis
• Programmable Vertical Blanking Interval (VBI) data
region for e.g. to support INTERCAST, teletext, closed
caption and similar applications
• 3.3 V supply enables reduced power consumption, 5 V
tolerant I/Os for 5 V PCI signalling environment.
3QUICK REFERENCE DATA
SYMBOLPARAMETERMIN.TYP.MAX.UNIT
V
DDD
I
DDD(tot)
V
i;Vo
f
LLC
f
PCI
f
I2S
T
amb
digital supply voltage3.03.33.6V
total digital supply current−400−mA
data input/output levelsTTL compatible
LLC input clock frequency−−32MHz
PCI input clock frequency−−33MHz
I2S input clock frequency−−12.5MHz
operating ambient temperature0−70°C
2GENERAL DESCRIPTION
The SAA7146A, Multimedia PCI-bridge, is a highly
integrated circuit for DeskTop Video (DTV) applications.
The device provides a number of interface ports that
enable a wide variety of video and audio ICs to be
connected to the PCI-bus thus supporting a number of
video applications in a PC. One example of the application
capabilities is shown in Fig.49.
Figure 1 shows the various interface ports and the main
internal function blocks.
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1998 Apr 095
k, full pagewidth
Dual D1 or 16-bit YUV
5BLOCK DIAGRAM
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
Philips SemiconductorsProduct specification
2
C-bus
I
Intel/
Motorola
2
S1-bus
I
2
S2-bus
I
GPIO PORTI/O
I2C-BUS MASTER
DEBI PORT
AUDIO INPUT/OUTPUT
AUDIO INPUT/OUTPUT
AUDIO FIFO
PCI INTERFACE
control
data
SAA7146A
DEBI FIFO
TSL
PCI BUS
RPS
TASK 1
TASK 2
EVENT
MANAGER
REAL TIME VIDEO INTERFACE
8-BIT D1 INPUT/OUTPUT8-BIT D1 INPUT/OUTPUT
16-BIT YUV IN
YUV
HIGH PERFORMANCE SCALER
H-FILTER/SCALER
V-FILTER/SCALER
VIDEO-FLIP/MIRROR
COLOUR SPACE CV. GAMMA CORRECTION
PIXEL-FORMATTER/DITHER
YUV/RGB
VIDEO
FIFO1
DMA AND INTERNAL ARBITRATION CONTROLLERMMU
CLIPPING
UNIT
VIDEO
FIFO2
YUV
BINARY
RATIO
SCALER
YUV
VIDEO
FIFO3
MHB044
SAA7146A
Fig.1 Block diagram.
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
SAA7146A
Scaler and PCI circuit (SPCI)
6PINNING
Pin description for QFP160
SYMBOLPINSTATUSDESCRIPTION
D1_A01I/Obidirectional digital CCIR 656 D1 port A bit 0
D1_A12I/Obidirectional digital CCIR 656 D1 port A bit 1
D1_A23I/Obidirectional digital CCIR 656 D1 port A bit 2
D1_A34I/Obidirectional digital CCIR 656 D1 port A bit 3
V
DDD1
V
SSD1
D1_A47I/Obidirectional digital CCIR 656 D1 port A bit 4
D1_A58I/Obidirectional digital CCIR 656 D1 port A bit 5
D1_A69I/Obidirectional digital CCIR 656 D1 port A bit 6
D1_A710I/Obidirectional digital CCIR 656 D1 port A bit 7
VS_A11I/Obidirectional vertical sync signal port A
HS_A12I/Obidirectional horizontal sync signal port A
LLC_A13I/Obidirectional line-locked system clock port A
PXQ_A14I/Obidirectional pixel qualifier signal to mark valid pixels port A; note 1
V
DDD2
V
SSD2
TRST17Itest reset input (JTAG pin must be set LOW for normal operation)
TMS18Itest mode select input (JTAG pin must be floating or set to HIGH during normal
TCLK19Itest clock input (JTAG pin should be set LOW during normal operation)
TDO20Otest data output (JTAG pin not active during normal operation)
TDI21Itest data input (JTAG pin must be floating or set to HIGH during normal operation)
V
DDD3
V
SSD3
INTA#24OPCI interrupt line output (active LOW)
RST25IPCI global reset input (active LOW)
CLK26IPCI clock input
GNT#27Ibus grant input signal, PCI arbitration signal (active LOW)
REQ#28Obus request output signal, PCI arbitration signal (active LOW)
V
DDD4
V
SSD4
AD PCI3131I/Obidirectional PCI multiplexed address/data bit 31
AD PCI3032I/Obidirectional PCI multiplexed address/data bit 30
AD PCI2933I/Obidirectional PCI multiplexed address/data bit 29
AD PCI2834I/Obidirectional PCI multiplexed address/data bit 28
V
DDD5
V
SSD5
AD PCI2737I/Obidirectional PCI multiplexed address/data bit 27
5Pdigital supply voltage 1 (3.3 V)
6Pdigital ground 1
15Pdigital supply voltage 2 (3.3 V)
16Pdigital ground 2
operation)
22Pdigital supply voltage 3 (3.3 V)
23Pdigital ground 3
29Pdigital supply voltage 4 (3.3 V)
30Pdigital ground 4
35Pdigital supply voltage 5 (3.3 V)
36Pdigital ground 5
1998 Apr 096
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
SAA7146A
Scaler and PCI circuit (SPCI)
SYMBOLPINSTATUSDESCRIPTION
AD PCI2638I/Obidirectional PCI multiplexed address/data bit 26
AD PCI2539I/Obidirectional PCI multiplexed address/data bit 25
AD PCI2440I/Obidirectional PCI multiplexed address/data bit 24
C/BE# [3]41I/Obidirectional PCI multiplexed bus command and byte enable 3 (active LOW)
IDSEL42IPCI initialization device select signal input
AD PCI2343I/Obidirectional PCI multiplexed address/data bit 23
AD PCI2244I/Obidirectional PCI multiplexed address/data bit 22
AD PCI2145I/Obidirectional PCI multiplexed address/data bit 21
AD PCI2046I/Obidirectional PCI multiplexed address/data bit 20
V
DDD6
V
SSD6
AD PCI1949I/Obidirectional PCI multiplexed address/data bit 19
AD PCI1850I/Obidirectional PCI multiplexed address/data bit 18
AD PCI1751I/Obidirectional PCI multiplexed address/data bit 17
AD PCI1652I/Obidirectional PCI multiplexed address/data bit 16
V
DDD7
V
SSD7
C/BE# [2]55I/Obidirectional PCI multiplexed bus command and byte enable 2 (active LOW)
FRAME#56I/Obidirectional PCI cycle frame signal (active LOW)
IRDY#57I/Obidirectional PCI initiator ready signal (active LOW)
TRDY#58I/Obidirectional PCI target ready signal (active LOW)
DEVSEL#59I/Obidirectional PCI device select signal (active LOW)
STOP#60I/Obidirectional PCI stop signal (active LOW)
PERR#61OPCI parity error signal output (active LOW)
PAR62I/Obidirectional PCI parity signal
C/BE# [1]63I/Obidirectional PCI-bus command and byte enable 1 (active LOW)
V
DDD8
V
SSD8
AD PCI1566I/Obidirectional PCI multiplexed address/data bit 15
AD PCI1467I/Obidirectional PCI multiplexed address/data bit 14
AD PCI1368I/Obidirectional PCI multiplexed address/data bit 13
AD PCI1269I/Obidirectional PCI multiplexed address/data bit 12
V
DDD9
V
SSD9
AD PCI1172I/Obidirectional PCI multiplexed address/data bit 11
AD PCI1073I/Obidirectional PCI multiplexed address/data bit 10
AD PCI974I/Obidirectional PCI multiplexed address/data bit 9
AD PCI875I/Obidirectional PCI multiplexed address/data bit 8
V
DDD10
V
SSD10
C/BE# [0]78I/Obidirectional PCI multiplexed bus command and byte enable 0 (active LOW)
47Pdigital supply voltage 6 (3.3 V)
48Pdigital ground 6
53Pdigital supply voltage 7 (3.3 V)
54Pdigital ground 7
64Pdigital supply voltage 8 (3.3 V)
65Pdigital ground 8
70Pdigital supply voltage 9 (3.3 V)
71Pdigital ground 9
76Pdigital supply voltage 10 (3.3 V)
77Pdigital ground 10
1998 Apr 097
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
SAA7146A
Scaler and PCI circuit (SPCI)
SYMBOLPINSTATUSDESCRIPTION
AD PCI779I/Obidirectional PCI multiplexed address/data bit 7
AD PCI680I/Obidirectional PCI multiplexed address/data bit 6
V
SSD11
AD PCI582I/Obidirectional PCI multiplexed address/data bit 5
AD PCI483I/Obidirectional PCI multiplexed address/data bit 4
AD PCI384I/Obidirectional PCI multiplexed address/data bit 3
AD PCI285I/Obidirectional PCI multiplexed address/data bit 2
V
DDD11
V
SSD12
AD PCI188I/Obidirectional PCI multiplexed address/data bit 1
AD PCI089I/Obidirectional PCI multiplexed address/data bit 0
V
DDD12
V
SSD13
AD1592I/Obidirectional DEBI multiplexed address data line bit 15
AD1493I/Obidirectional DEBI multiplexed address data line bit 14
AD1394I/Obidirectional DEBI multiplexed address data line bit 13
AD1295I/Obidirectional DEBI multiplexed address data line bit 12
V
DDD13
V
SSD14
AD1198I/Obidirectional DEBI multiplexed address data line bit 11
AD1099I/Obidirectional DEBI multiplexed address data line bit 10
AD9100I/Obidirectional DEBI multiplexed address data line bit 9
AD8101I/Obidirectional DEBI multiplexed address data line bit 8
V
DDD14
V
SSD15
RWN_SBHE104ODEBI data transfer control signal output (read write not/system byte high enable)
AS_ALE105ODEBI address strobe and address latch enable output
LDS_RDN106Olower data strobe/read not output
UDS_WRN107Oupper data strobe/write not output
DTACK_RDY108IDEBI data transfer acknowledge or ready input
V
DDD15
V
SSD16
AD0111I/Obidirectional DEBI multiplexed address data line bit 0
AD1112I/Obidirectional DEBI multiplexed address data line bit 1
AD2113I/Obidirectional DEBI multiplexed address data line bit 2
AD3114I/Obidirectional DEBI multiplexed address data line bit 3
V
DDD16
V
SSD17
AD4117I/Obidirectional DEBI multiplexed address data line bit 4
AD5118I/Obidirectional DEBI multiplexed address data line bit 5
81Pdigital ground 11
86Pdigital supply voltage 11 (3.3 V)
87Pdigital ground 12
90Pdigital supply voltage 12 (3.3 V)
91Pdigital ground 13
96Pdigital supply voltage 13 (3.3 V)
97Pdigital ground 14
102Pdigital supply voltage 14 (3.3 V)
103Pdigital ground 15
109Pdigital supply voltage 15 (3.3 V)
110Pdigital ground 16
115Pdigital supply voltage 16 (3.3 V)
116Pdigital ground 17
1998 Apr 098
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SYMBOLPINSTATUSDESCRIPTION
AD6119I/Obidirectional DEBI multiplexed address data line bit 6
AD7120I/Obidirectional DEBI multiplexed address data line bit 7
WS0121I/Obidirectional word select signal for audio interface A1
SD0122I/Obidirectional serial data for audio interface A1
BCLK1123I/Obidirectional bit clock for audio interface A1
WS1124Oword select output signal for audio interface A1/A2
SD1125I/Obidirectional serial data for audio interface A1/A2
WS2126Oword select output signal for audio interface A1/A2
SD2127I/Obidirectional serial data for audio interface A1/A2
V
DDD17
V
SSD18
WS3130Oword select output signal for audio interface A1/A2
SD3131I/Obidirectional serial data for audio interface A1/A2
BCLK2132I/Obidirectional bit clock for audio interface A2
WS4133I/Obidirectional word select signal for audio interface A2
SD4134I/Obidirectional serial data for audio interface A2
ACLK135Iaudio reference clock input signal
SCL136I/Obidirectional I
SDA137I/Obidirectional I
V
DDD18
V
DDI2C
V
SSD19
GPIO3141I/Ogeneral purpose I/O signal 3
GPIO2142I/Ogeneral purpose I/O signal 2
GPIO1143I/Ogeneral purpose I/O signal 1
GPIO0144I/Ogeneral purpose I/O signal 0
D1_B0145I/Obidirectional digital CCIR 656 D1 port B bit 0
D1_B1146I/Obidirectional digital CCIR 656 D1 port B bit 1
D1_B2147I/Obidirectional digital CCIR 656 D1 port B bit 2
D1_B3148I/Obidirectional digital CCIR 656 D1 port B bit 3
V
DDD19
V
SSD20
D1_B4151I/Obidirectional digital CCIR 656 D1 port B bit 4
D1_B5152I/Obidirectional digital CCIR 656 D1 port B bit 5
D1_B6153I/Obidirectional digital CCIR 656 D1 port B bit 6
D1_B7154I/Obidirectional digital CCIR 656 D1 port B bit 7
V
DDD20
V
SSD21
LLC_B157I/Obidirectional line-locked system clock port B
VS_B158I/Obidirectional vertical sync signal port B
128Pdigital supply voltage 17 (3.3 V)
129Pdigital ground 18
2
C-bus clock line
2
C-bus data line
138Pdigital supply voltage 18 (3.3 V)
139II2C-bus voltage sense input; see note 3 of “Characteristics”
140Pdigital ground 19
149Pdigital supply voltage 19 (3.3 V)
150Pdigital ground 20
155Pdigital supply voltage 20 (3.3 V)
156Pdigital ground 21
SAA7146A
1998 Apr 099
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
SAA7146A
Scaler and PCI circuit (SPCI)
SYMBOLPINSTATUSDESCRIPTION
HS_B159I/Obidirectional horizontal sync signal port B
PXQ_B160I/Obidirectional pixel qualifier signal to mark valid pixels port B; note 2
Notes
1. For continuous CCIR 656 format at the D1_A port this pin must be set HIGH.
2. For continuous CCIR 656 format at the D1_B port this pin must be set HIGH.
handbook, halfpage
160
1
121
120
SAA7146AH
40
41
80
81
MHB045
Fig.2 Pin configuration SAA7146AH (QFP160).
1998 Apr 0910
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
SAA7146A
Scaler and PCI circuit (SPCI)
Pin description for SQFP208
SYMBOLPINSTATUSDESCRIPTION
V
SSD0
D1_A02I/Obidirectional digital CCIR 656 D1 port A bit 0
D1_A13I/Obidirectional digital CCIR 656 D1 port A bit 1
D1_A24I/Obidirectional digital CCIR 656 D1 port A bit 2
D1_A35I/Obidirectional digital CCIR 656 D1 port A bit 3
V
DDD1
n.c.7−reserved pin; not connected internally
V
SSD1
D1_A49I/Obidirectional digital CCIR 656 D1 port A bit 4
D1_A510I/Obidirectional digital CCIR 656 D1 port A bit 5
D1_A611I/Obidirectional digital CCIR 656 D1 port A bit 6
D1_A712I/Obidirectional digital CCIR 656 D1 port A bit 7
V
DDD2
n.c.14−reserved pin; not connected internally
V
SSD2
VS_A16I/Obidirectional vertical sync signal port A
HS_A17I/Obidirectional horizontal sync signal port A
LLC_A18I/Obidirectional line-locked system clock port A
PXQ_A19I/Obidirectional pixel qualifier signal to mark valid pixels port A; note 1
n.c.20−reserved pin; do not connect
V
DDD3
n.c.22−reserved pin; not connected internally
V
SSD3
TRST24Itest reset input (JTAG pin must be set LOW for normal operation)
TMS25Itest mode select input (JTAG pin must be floating or set to HIGH during normal
TCLK26Itest clock input (JTAG pin should be set LOW during normal operation)
TDO27Otest data output (JTAG pin not active during normal operation)
TDI28Itest data input (JTAG pin must be floating or set to HIGH during normal operation)
V
DDD4
n.c.30−reserved pin; not connected internally
V
SSD4
INTA#32OPCI interrupt line output (active LOW)
RST#33IPCI global reset input (active LOW)
CLK34IPCI clock input
GNT#35Ibus grant input signal input, PCI arbitration signal (active LOW)
REQ#36Obus request output signal output, PCI arbitration signal (active LOW)
V
DDD5
n.c.38−reserved pin; not connected internally
1Pdigital ground 0
6Pdigital supply voltage 1 (3.3 V)
8Pdigital ground 1
13Pdigital supply voltage 2 (3.3 V)
15Pdigital ground 2
21Pdigital supply voltage 3 (3.3 V)
23Pdigital ground 3
operation)
29Pdigital supply voltage 4 (3.3 V)
31Pdigital ground 4
37Pdigital supply voltage 5 (3.3 V)
1998 Apr 0911
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
SAA7146A
Scaler and PCI circuit (SPCI)
SYMBOLPINSTATUSDESCRIPTION
V
SSD5
AD PCI3140I/Obidirectional PCI multiplexed address/data bit 31
AD PCI3041I/Obidirectional PCI multiplexed address/data bit 30
AD PCI2942I/Obidirectional PCI multiplexed address/data bit 29
AD PCI2843I/Obidirectional PCI multiplexed address/data bit 28
V
DDD6
n.c.45−reserved pin; not connected internally
V
SSD6
AD PCI2747I/Obidirectional PCI multiplexed address/data bit 27
AD PCI2648I/Obidirectional PCI multiplexed address/data bit 26
AD PCI2549I/Obidirectional PCI multiplexed address/data bit 25
AD PCI2450I/Obidirectional PCI multiplexed address/data bit 24
V
DDD7
n.c.52−reserved pin; do not connect
n.c.53−reserved pin; not connected internally
V
SSD7
C/BE# [3]55I/Obidirectional PCI multiplexed bus command and byte enable 3 (active LOW)
IDSEL56IPCI initialization device select input signal
AD PCI2357I/Obidirectional PCI multiplexed address/data bit 23
AD PCI2258I/Obidirectional PCI multiplexed address/data bit 22
AD PCI2159I/Obidirectional PCI multiplexed address/data bit 21
AD PCI2060I/Obidirectional PCI multiplexed address/data bit 20
n.c.61−reserved pin; do not connect
n.c.62−reserved pin; not connected internally
V
SSD8
AD PCI1964I/Obidirectional PCI multiplexed address/data bit 19
AD PCI1865I/Obidirectional PCI multiplexed address/data bit 18
AD PCI1766I/Obidirectional PCI multiplexed address/data bit 17
AD PCI1667I/Obidirectional PCI multiplexed address/data bit 16
V
DDD8
n.c.69−reserved pin; do not connect
V
SSD9
C/BE# [2]71I/Obidirectional PCI multiplexed bus command and byte enable 2 (active LOW)
FRAME#72I/Obidirectional PCI cycle frame signal (active LOW)
IRDY#73I/Obidirectional PCI initiator ready signal (active LOW)
TRDY#74I/Obidirectional PCI target ready signal (active LOW)
V
DDD9
n.c.76−reserved pin; do not connect
V
SSD10
DEVSEL#78I/Obidirectional PCI device select signal (active LOW)
39Pdigital ground 5
44Pdigital supply voltage 6 (3.3 V)
46Pdigital ground 6
51Pdigital supply voltage 7 (3.3 V)
54Pdigital ground 7
63Pdigital ground 8
68Pdigital supply voltage 8 (3.3 V)
70Pdigital ground 9
75Pdigital supply voltage 9 (3.3 V)
77Pdigital ground 10
1998 Apr 0912
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
SAA7146A
Scaler and PCI circuit (SPCI)
SYMBOLPINSTATUSDESCRIPTION
STOP#79I/Obidirectional PCI stop signal (active LOW)
PERR#80OPCI parity error output signal (active LOW)
n.c.81−reserved pin; do not connect
PAR82I/Obidirectional PCI parity signal
C/BE# [1]83I/Obidirectional PCI-bus command and byte enable 1 (active LOW)
V
DDD10
n.c.85−reserved pin; not connected internally
V
SSD11
AD PCI1587I/Obidirectional PCI multiplexed address/data bit 15
AD PCI1488I/Obidirectional PCI multiplexed address/data bit 14
AD PCI1389I/Obidirectional PCI multiplexed address/data bit 13
AD PCI1290I/Obidirectional PCI multiplexed address/data bit 12
V
DDD11
n.c.92−reserved pin; not connected internally
V
SSD12
AD PCI1194I/Obidirectional PCI multiplexed address/data bit 11
AD PCI1095I/Obidirectional PCI multiplexed address/data bit 10
AD PCI996I/Obidirectional PCI multiplexed address/data bit 9
AD PCI897I/Obidirectional PCI multiplexed address/data bit 8
n.c.98−reserved pin; do not connect
n.c.99−reserved pin; not connected internally
V
SSD13
C/BE# [0]101I/Obidirectional PCI multiplexed bus command and byte enable (active LOW)
AD PCI7102I/Obidirectional PCI multiplexed address/data bit 7
AD PCI6103I/Obidirectional PCI multiplexed address/data bit 6
V
DDD12
n.c.105−reserved pin; do not connect
n.c.106−reserved pin; not connected internally
V
SSD14
AD PCI5108I/Obidirectional PCI multiplexed address/data bit 5
AD PCI4109I/Obidirectional PCI multiplexed address/data bit 4
AD PCI3110I/Obidirectional PCI multiplexed address/data bit 3
AD PCI2111I/Obidirectional PCI multiplexed address/data bit 2
V
DDD13
n.c.113−reserved pin; not connected internally
V
SSD15
AD PCI1115I/Obidirectional PCI multiplexed address/data bit 1
AD PCI0116I/Obidirectional PCI multiplexed address/data bit 0
V
DDD14
n.c.118−reserved pin; not connected internally
V
SSD16
84Pdigital supply voltage 10 (3.3 V)
86Pdigital ground 11
91Pdigital supply voltage 11 (3.3 V)
93Pdigital ground 12
100Pdigital ground 13
104Pdigital supply voltage 12 (3.3 V)
107Pdigital ground 14
112Pdigital supply voltage 13 (3.3 V)
114Pdigital ground 15
117Pdigital supply voltage 14 (3.3 V)
119Pdigital ground 16
1998 Apr 0913
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
SAA7146A
Scaler and PCI circuit (SPCI)
SYMBOLPINSTATUSDESCRIPTION
AD15120I/Obidirectional DEBI multiplexed address data line bit 15
AD14121I/Obidirectional DEBI multiplexed address data line bit 14
AD13122I/Obidirectional DEBI multiplexed address data line bit 13
AD12123I/Obidirectional DEBI multiplexed address data line bit 12
V
DDD15
n.c.125−reserved pin; not connected internally
V
SSD17
AD11127I/Obidirectional DEBI multiplexed address data line bit 11
AD10128I/Obidirectional DEBI multiplexed address data line bit 10
AD9129I/Obidirectional DEBI multiplexed address data line bit 9
AD8130I/Obidirectional DEBI multiplexed address data line bit 8
V
DDD16
n.c.132−reserved pin; not connected internally
V
SSD18
RWN_SBHE134ODEBI data transfer control output signal (read write not/system byte high enable)
AS_ALE135ODEBI address strobe and address latch enable output
LDS_RDN136Olower data strobe/read not output
UDS_WRN137Oupper data strobe/write not output
DTACK_RDY138IDEBI data transfer acknowledge or ready input
V
DDD17
n.c.140−reserved pin; not connected internally
V
SSD19
AD0142I/Obidirectional DEBI multiplexed address data line bit 0
AD1143I/Obidirectional DEBI multiplexed address data line bit 1
AD2144I/Obidirectional DEBI multiplexed address data line bit 2
AD3145I/Obidirectional DEBI multiplexed address data line bit 3
V
DDD18
n.c.147−reserved pin; not connected internally
V
SSD20
AD4149I/Obidirectional DEBI multiplexed address data line bit 4
AD5150I/Obidirectional DEBI multiplexed address data line bit 5
AD6151I/Obidirectional DEBI multiplexed address data line bit 6
AD7152I/Obidirectional DEBI multiplexed address data line bit 7
n.c.153−reserved pin; do not connect
n.c.154−reserved pin; do not connect
V
DDD19
n.c.156−reserved pin; not connected internally
n.c.157−reserved pin; do not connect
V
SSD21
WS0159I/Obidirectional word select signal for audio interface A1
SD0160I/Obidirectional serial data for audio interface A1
124Pdigital supply voltage 15 (3.3 V)
126Pdigital ground 17
131Pdigital supply voltage 16 (3.3 V)
133Pdigital ground 18
139Pdigital supply voltage 17 (3.3 V)
141Pdigital ground 19
146Pdigital supply voltage 18 (3.3 V)
148Pdigital ground 20
155Pdigital supply voltage 19 (3.3 V)
158Pdigital ground 21
1998 Apr 0914
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SYMBOLPINSTATUSDESCRIPTION
BCLK1161I/Obidirectional bit clock for audio interface A1
WS1162Oword select output signal for audio interface A1/A2
SD1163I/Obidirectional serial data for audio interface A1/A2
WS2164Oword select output signal for audio interface A1/A2
SD2165I/Obidirectional serial data for audio interface A1/A2
V
DDD20
n.c.167−reserved pin; not connected internally
V
SSD22
WS3169Oword select output signal for audio interface A1/A2
SD3170I/Obidirectional serial data for audio interface A1/A2
BCLK2171I/Obidirectional bit clock for audio interface A2
WS4172I/Obidirectional word select signal for audio interface A2
SD4173I/Obidirectional serial data for audio interface A2
ACLK174Iaudio reference clock input signal
SCL175I/Obidirectional I
SDA176I/Obidirectional I
V
DDD21
V
DDI2C
V
SSD23
GPIO3180I/Ogeneral purpose I/O signal 3
GPIO2181I/Ogeneral purpose I/O signal 2
GPIO1182I/Ogeneral purpose I/O signal 1
GPIO0183I/Ogeneral purpose I/O signal 0
V
DDD22
n.c.185−reserved pin; not connected internally
V
SSD24
D1_B0187I/Obidirectional digital CCIR 656 D1 port B bit 0
D1_B1188I/Obidirectional digital CCIR 656 D1 port B bit 1
D1_B2189I/Obidirectional digital CCIR 656 D1 port B bit 2
D1_B3190I/Obidirectional digital CCIR 656 D1 port B bit 3
V
DDD23
n.c.192−reserved pin; not connected internally
V
SSD25
D1_B4194I/Obidirectional digital CCIR 656 D1 port B bit 4
D1_B5195I/Obidirectional digital CCIR 656 D1 port B bit 5
D1_B6196I/Obidirectional digital CCIR 656 D1 port B bit 6
D1_B7197I/Obidirectional digital CCIR 656 D1 port B bit 7
V
DDD24
n.c.199−reserved pin; not connected internally
V
SSD26
LLC_B201I/Obidirectional line-locked system clock port B
166Pdigital supply voltage 20 (3.3 V)
168Pdigital ground 22
2
C-bus clock line
2
C-bus data line
177Pdigital supply voltage 21 (3.3 V)
178II2C-bus voltage sense input; see note 3 of “Characteristics”
179Pdigital ground 23
184Pdigital supply voltage 22 (3.3 V)
186Pdigital ground 24
191Pdigital supply voltage 23 (3.3 V)
193Pdigital ground 25
198Pdigital supply voltage 24 (3.3 V)
200Pdigital ground 26
SAA7146A
1998 Apr 0915
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
SAA7146A
Scaler and PCI circuit (SPCI)
SYMBOLPINSTATUSDESCRIPTION
VS_B202I/Obidirectional vertical sync signal port B
HS_B203I/Obidirectional horizontal sync signal port B
PXQ_B204I/Obidirectional pixel qualifier signal to mark valid pixels port B; note 2
n.c.205−reserved pin; do not connect
V
DDD25
n.c.207−reserved pin; not connected internally
n.c.208−reserved pin; do not connect
Notes
1. For continuous CCIR 656 format at the D1_A port this pin must be set HIGH.
2. For continuous CCIR 656 format at the D1_B port this pin must be set HIGH.
206Pdigital supply voltage 25 (3.3 V)
handbook, halfpage
52
208
1
SAA7146AHZ
53
157
104
156
105
MHB046
Fig.3 Pin configuration SAA7146AHZ (SQFP208).
1998 Apr 0916
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
7FUNCTIONAL DESCRIPTION
This chapter provides information about the features
realized with this device. First, a general, thus short,
description of the functionality is given. The following
sections deal with the single features in a detailed manner.
7.1General
The Dual D1 (DD1) interface can be connected to digital
video decoder ICs such as the SAA7110 and SAA7111A,
digital video encoder such as the SAA7185B, video
compression CODECs or to a D1 compatible connector,
e.g. for interconnection to an external digital camera.
The interface supports bidirectional full duplex two channel
full D1 (CCIR 656), optionally with separate sync lines
H/V, pixel qualifier signal and double pixel clock I/O, up to
32 MHz. It also supports a 16-bit parallel ‘YUV bus’ for
interfacing to the SAA7110.
One of the two internal video processors of the SAA7146A
is the two-dimensional High Performance Scaler (HPS).
Phase accurate re-sampling by interpolation supports
independent horizontal up and downscaling. In the
horizontal direction the scaling process is performed in two
functional blocks: integer decimation by window averaging
(up to 65 tap), and phase linear interpolation (10 tap filter
for luminance, 6 tap filter for chrominance). The vertical
processing for downscaling either uses averaging over a
window (up to 65 tap) or linear interpolation (2 tap).
The scaling function can be used for random sized display
windowing, for horizontal upscaling (zoom) or for
conversion between various sample schemes such as
CCIR or SQP. Incorporated with the HPS function is
brightness, contrast and saturation control. Colour key
generation is also established. The output of the HPS can
be formatted in various RGB and YUV formats.
Additionally, this output can be dithered for low bit rate
formats. Packed formats as well as planar formats (YUV)
are supported.
A second video channel (YUV4:2:2 format) bypasses
the HPS and connects the real time video interface with
the PCI interface. This video bypass channel, using the
second video processor Binary Ratio Scaler (BRS), is
bidirectional and has means to convert from full size video
(50 or 60 Hz) to Common Interchange Format (CIF),
Quarter Common Interchange Format (QCIF) or Quarter
Quarter Common Interchange Format (QQCIF) and vice
versa (binary ratio 1, 2, 4, 8,
programmable VBI data and test signal regions can be
bypassed without processing during each field.
1
⁄2,1⁄4and1⁄8only). Multiple
SAA7146A
The bidirectional digital audio serial interface is based on
2
the I
S-bus standard, but supports flexible programming
for various data and timing formats.
Two independent interface circuits control audio data
streaming of up to 2 × 128-bit frame width (bidirectional or
simultaneous input/output). Five or more I2S devices such
as the SAA7360 and SAA7366 (ADC) and SAA7350 and
SAA7351 (DAC) can be connected gluelessly.
The peripheral data port [Data Expansion Bus Interface
(DEBI)] enables 8 or 16-bit parallel access for system
set-up and programming of peripheral multimedia devices
(behind SAA7146A), but is also highly capable to interface
compressed MPEG/JPEG data of peripheral ICs with the
PCI system. DEBI supports both Intel compatible (ISA-bus
like) and Motorola (68000 style) compatible handshaking
protocols with up to 23 Mbytes/s peak data rate. Besides
the parallel port, there is also an I2C-bus port to control
peripheral ICs such as single-chip decoders SAA7110 and
SAA7111A or as encoders such as SAA7185B and
SAA7187 or as audio ICs.
The PCI interface has master read and master write
capability. The video signal flows to and from the PCI and
is controlled by three video DMA channels with a total
FIFO capacity of 384 Dwords. The video DMA channel
definition supports the typical video data structure
(hierarchy) of pixels, lines, fields and frames. The audio
signal flow is controlled by four audio DMA channels, each
with 24 Dwords FIFO capacity. The DEBI port is
connected to the PCI by single instruction direct access
(immediate mode) and via a data DMA channel for
streaming data (block mode) with 32 Dwords FIFO
capacity. To improve PCI-bus efficiency, an arbiter
schedules the access to PCI-bus for all local DMA
channels.
The PCI interface of the SAA7146A supports virtual
memory addressing for operating systems running virtual
demand paging. The integrated Memory Management
Unit (MMU) translates linear addressing to physical
addresses using a page table inside the system memory
provided by the software driver. The MMU supports up to
4 Mbytes of virtual address space per DMA channel.
The SAA7146A can change its programming sets using a
Register Programming Sequencer (RPS) that works by
itself on a user defined program controlled by internally
supported real time events. The SAA7146A has two RPS
machines to optimize flow control of e.g. an MPEG
compressed data stream and real time video scaling
control. The RPS programming is defined by an instruction
list in the system main memory that consists of multiple
RPS commands.
1998 Apr 0917
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
7.2PCI interface
This section describes the interface of the SAA7146A to
the PCI-bus. This includes the PCI modules, the DMA
controls of the video, audio and data channels, the
Memory Management Unit (MMU) and the Internal
Arbitration Control (INTAC). The handling of the FIFOs
and the corresponding errors are also described and a list
of all DMA control registers is given.
7.2.1PCI
The SAA7146A provides a PCI-bus interface having both
slave and master capability. The master and the slave
module fulfil the PCI local bus specification revision 2.1.
They decode the C/BE# lines to provide a byte-wise
access and support 32-bit transfers up to a maximum clock
rate of 33 MHz. To increase bus performance, they are
able to handle fast back-to-back transfers.
During normal operation the SAA7146A checks for parity
errors and reports them via the PERR# pin. If an address
parity error is detected the SAA7146A will not respond.
MODULES AND CONFIGURATION SPACE
SAA7146A
Using the SAA7146A as a slave, access is obtained only
to the programmable registers and to its configuration
space. Video, audio and other data of the SAA7146A
reads/writes autonomously via the master interface (see
Fig.4). The use of the PCI master module, i.e. which DMA
channel gets access to the PCI-bus, is controlled by the
INTAC (see Section 7.2.5).
The registers described in Table 1 are closely related to
the PCI specification. It should be noted that Header type,
Cache Line Size, BIST, Card bus CIS Pointer and
Expansion ROM Base Address Registers are not
implemented. All registers, which are not implemented are
treated as read only with a value of zero. Some values are
loaded after PCI reset via I
device address 1010000 (binary). This loading will take
approximately 1 ms at 33 MHz PCI clock. If any device
tries to read or write data from or to the SAA7146A during
the loading phase after reset, the SAA7146A will
disconnect with retry.
2
C-bus from EEPROM with
1998 Apr 0918
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1998 Apr 0919
ndbook, full pagewidth
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
PCI-bus
physical address
MEMORY MANAGEMENT
data
REGISTER
SHADOW RAM
data
byte enable
bus command
PCI
MODULE
MASTER
PCI
MODULE
SLAVE
AND
UNIT
(MMU)
CE
EOT
new Tr
address
logic
address
channel select
INTERNAL ARBITRA TION
CONTROL
(INTAC)
bus requests
REGISTER PROGRAMMING
SEQUENCER
(RPS)
FIFO
CONTROL
(FICO)
FIFO1
FIFO2
FIFO3
AUDIO FIFO1 OUT
AUDIO FIFO1 IN
AUDIO FIFO2 OUT
AUDIO FIFO2 IN
REGISTER
SETS
2
I
C-BUS REGISTER
FIFO
INPUT
CONTROL
(FINC)
video/audio
data streams
DEBI data/request
ERROR MANAGER
(EMA)
Fig.4 Block diagram of the PCI interface.
interrupts
MHB047
SAA7146A
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
SAA7146A
Scaler and PCI circuit (SPCI)
Table 1 Configuration space registers
ADDRESS
(HEX)
00Device ID31 to 16RO 7146HSAA7146A
04Status Register31−detected parity error
08Class Code31 to 8RO 048000H other multimedia device
0CLatency15 to 8RWthis register specifies, in units of PCI-bus clocks, the
10Base Address
2CSubsystem ID31 to 16ROthis value will be loaded after a PCI reset from external
3CMax_Lat31 to 24ROthis value will be loaded after a PCI reset from external
value of the latency timer for this PCI-bus master
31 to 9RWthis value must be added to the register offset to claim
8to0RO
15 to 0ROthis value will be loaded after a PCI reset from external
access to the programming registers; the lower 8 bits
are forced to zero
hardware using the I
hardware using the I
hardware using the I
hardware using the I
device uses. This device uses interrupt pin INTA#.
When these bits are read they return 01H.
interrupt controller the device’s interrupt pin is
connected to
2
C-bus; the default value is 0000H
2
C-bus; the default value is 0000H
2
C-bus; the default value is 26H
2
C-bus; the default value is 0FH
1998 Apr 0920
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
7.2.2VIDEO DMA CONTROL
The SAA7146A’s DMA control is able to support up to
three independent video targets or sources respectively.
For this purpose it provides three video DMA channels.
Each channel consists of a FIFO, a FIFO Input Control
(FINC) placed on the video side of the FIFO, and a FIFO
Control (FICO) placed on the PCI side of the FIFO.
Channel 1 only supports the unidirectional data stream
into the PCI memory. It is not able to read data from
system memory. However, this access is possible using
Channels 2 or 3. Table 2 surveys the possibilities and
purposes of each video DMA channel.
Each FIFO, i.e. each DMA channel, has its own
programming set including base address (doubled for odd
and even fields), pitch, protection address, page table
base address, several handling mode control bits and a
transfer enable bit (TR_E). In addition, each channel has a
threshold and a burst length definition for internal
arbitration (see Table 6, Section 7.2.5).
SAA7146A
To handle the reading modes FIFO 2 and FIFO 3 offer
some additional registers: Number of Bytes per line
(NumBytes), Number of Lines per field (NumLines) and
the vertical scaling ratio (only FIFO 3, see Table 69).
The programming sets could be reloaded after the
previous job is done [Video Transfer Done (VTD)] to
support several DMA targets per FIFO. The programming
set currently used is loaded by the Register Programming
Sequencer (RPS). If the RPS is not used, the registers
could be rewritten each time, using the SAA7146A as a
slave. But then the programmer must take care of the
synchronization of these write accesses.
All registers needed for DMA control are described in
Table 3, except the transfer enable bits, which are
described in Table 10. The registers are accessed through
PCI base address with appropriate offset (see Table 1).
Table 2 Size, direction and purpose of the video FIFOs and the associated DMA controls
FIFOSIZEDIRECTIONPURPOSE
FIFO 1128 Dwordswrite to PCIFIFO 1 buffers data from the HPS output and writes into PCI memory.
In planar mode FIFO 1 gets the Y data.
FIFO 2128 DwordsRWPlanar mode: FIFO 2 buffers U data provided by the HPS; the
associated DMA control 2 sends it into the PCI memory.
Clip mode: DMA control 2 reads clipping information (clip bit mask or
rectangular overlay data) from the PCI system memory and buffers it
in FIFO 2.
FIFO 3128 DwordsRWPlanar mode: FIFO 3 buffers V data provided by the HPS and writes
it into the PCI memory.
Chroma keying mode: FIFO 3 buffers chroma keying information
and writes it into PCI memory.
BRS mode: FIFO 3 buffers data provided by the BRS. DMA control 3
sends it into the PCI memory.
Read mode: DMA control 3 reads video data from the PCI system
memory (the same data up to four times to offer a simple upscaling
algorithm) and buffers it in FIFO 3.
1998 Apr 0921
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
SAA7146A
Scaler and PCI circuit (SPCI)
Table 3 Video DMA control registers
OFFSET
(HEX)
00BaseOdd131 to 0RWPCI base address for odd fields of the upper (or lower if pitch is
04BaseEven131 to 0RWPCI base address for even fields of the upper (or lower if pitch is
08ProtAddr131 to 2RWprotection address
0CPitch131 to 0RWdistance between the start addresses of two consecutive lines of a single
10Page131 to 12RWbase address of the page table (see Section 7.2.4)
14NumLines1 27 to 16RWNumber of lines per field; it defines the number of qualified lines to be
18BaseOdd231 to 0RWPCI base address for odd fields of the upper (or lower if top-down flip is
1CBaseEven231 to 0RWPCI base address for even fields of the upper (or lower if top-down flip is
20ProtAddr231 to 2RWprotection address
24Pitch231 to 0RWdistance between the start addresses of two consecutive lines of a field
28Page231 to 12RWbase address of the page table (see Section 7.2.4)
NAMEBITTYPEDESCRIPTION
negative) left pixel of the transferred field
negative) left pixel of the transferred field
−1 and 0−reserved
field
ME111RWmapping enable; this bit enables the MMU
−10 to 8−reserved
Limit17 to 4RWinterrupt limit; defines the size of the memory range, that raise an
interrupt, if its boundaries are passed
PV13RWprotection violation handling
−2−reserved
Swap11 and 0RWendian swapping of all Dwords passing the FIFO 1:
00 = no swap
01 = two bytes swap (3210 to 2301)
10 = four bytes swap (3210 to 0123)
11 = reserved
processed by the HPS per field. This will cut off all the following input lines
at the HPS input.
NumBytes111 to 0RWNumber of pixels per line; it defines the number of qualified pixels to be
processed by the HPS per line. This will cut off all the following pixels at
the HPS input.
selected) left pixel of the transferred field
selected) left pixel of the transferred field
−1 and 0−reserved
ME211RWmapping enable; this bit enables the MMU
−10 to 8−reserved
Limit27 to 4RWinterrupt limit; defines the size of the memory range, that raise an
interrupt, if its boundaries are passed
PV23RWprotection violation handling
1998 Apr 0922
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
SAA7146A
Scaler and PCI circuit (SPCI)
OFFSET
(HEX)
28RW22RWSpecifies the data stream direction of FIFO 2. A logic 0 enables a write
2CNumLines2 27 to 16RWNumber of lines per field: in read mode NumLines defines the number of
30BaseOdd331 to 0RWPCI base address for odd fields of the upper (or lower if top-down flip is
34BaseEven331 to 0RWPCI base address for even fields of the upper (or lower if top-down flip is
38ProtAddr331 to 2RWprotection address
3CPitch331 to 0RWdistance between the start addresses of two consecutive lines of a field
40Page331 to 12RWbase address of the page table (see Section 7.2.4)
44NumLines3 27 to 16RWNumber of lines per field: in read mode NumLines defines the number of
NAMEBITTYPEDESCRIPTION
operation to the PCI memory. A logic 1 enables a read operation from the
PCI memory.
Swap21 and 0RWendian swapping of all Dwords passing the FIFO 2:
00 = no swap
01 = two byte swap (3210 to 2301)
10 = four byte swap (3210 to 0123)
11 = reserved
lines to be read from system memory. A logic 0 specifies one line. In write
mode this register is not used.
NumBytes211 to 0RWNumber of bytes per line: in read mode this defines the number of bytes
per line to be read from system memory. A logic 0 specifies one byte. In
write mode this register is not used.
selected) left pixel of the transferred field
selected) left pixel of the transferred field
−1 and 0−reserved
ME311RWmapping enable; this bit enables the MMU
−10 to 8−reserved
Limit37 to 4RWinterrupt limit; defines the size of the memory range, that raise an
interrupt, if its boundaries are passed
PV33RWprotection violation handling
RW32RWSpecifies the data stream direction of FIFO 3. A logic 0 enables a write
operation to the PCI memory. A logic 1 enables a read operation from the
PCI memory.
Swap31 and 0RWendian swapping of all Dwords passing the FIFO 3:
00 = no swap
01 = two byte swap (3210 to 2301)
10 = four byte swap (3210 to 0123)
11 = reserved
lines to be read from system memory. A logic 0 specifies one line. In write
mode it defines the number of qualified lines to be processed by the BRS
per field. This will cut off all the following input-lines at the BRS input.
NumBytes311 to 0RWNumber of bytes per line: in read mode this defines the number of bytes
per line to be read from system memory. A logic0 specifies 1 byte. In write
mode it defines the number of qualified bytes to be processed by the BRS
per line. This will cut off all the following bytes at the BRS input.
1998 Apr 0923
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
The video channels provide 32 bits of data signals and
4 bits of Byte Enable (BE) signals, End-Of-Line (EOL),
End-Of-Window (EOW), Begin-Of-Field (BOF),
Line-Locked Clock (LLC), Odd/Even signal (OE) and a
Valid Data (VD) signal. To start a video data transfer, e.g.
via video DMA Channel 3, this channel must first be
included in the internal arbitration scheme. This is
achieved by setting the corresponding TR_E bit
(see Table 10). If a TR_E bit is not set, the corresponding
FIFO is reset.
In read mode, which is offered by Channels 2 and 3, the
FICO requests a PCI transfer with the next BOF. Data is
provided by the PCI master module. The FICO calculates
the PCI address autonomously, starting with the base
address of the corresponding field. Only the received data
will be filled into the FIFO. FIFO 3 offers the possibility to
read video information from PCI memory, e.g. from the
frame buffer. This could be achieved by using the
NumBytes and the NumLines register, which defines the
size of the source picture, so that the DMA control is able
to synchronize itself to the source frame. FIFO 2 does the
same if reading clip information from memory.
To support the Binary Ratio Scaler (BRS) included in the
SAA7146A, which only provides the possibility of
horizontal upscaling, the DMA control 3 can be applied to
perform line repetition by reading lines up to four times
from PCI memory. This feature is controlled by the vertical
scaling ratio in outbound mode (see Table 66). This ratio
specifies the number of times each line should be read:
00 = only once, 01 = twice, and so on.
In the event of FIFO underflow, i.e. if the BRS or the
clipping unit respectively tries to read data from the FIFO,
even if the DMA control was not able to fill any data until
that moment, the reading unit tries to synchronize itself to
the outgoing data stream as soon as possible. In this way
the reading of invalid data is minimized. If the clipping unit
receives no data, it will disable the associated pixels.
The behaviour of the BRS depends on the selected read
mode which is described in Section 7.10.
In the event of FIFO overflow, i.e. if the scaler tries to
transfer data although the FIFO is full, the FIFO input
control locks the FIFO for the incoming data. During FIFO
overflow the PCI address of the incoming data will be
increased, over writing itself each time, if the scaler
transfers data, which has been clipped, the same
mechanism is used to improve PCI performance.
The SAA7146A is able to handle a negative pitch.
With that, top-down-flip of the transmitted fields or frames
is possible. A negative pitch (MSB = 1) leads to a different
definition of the protection and the base address, as
SAA7146A
shown in Fig.5. If using negative pitch the first line starts at
base address + pitch.
In ‘none-RPS’ mode the SAA7146A supports the
displaying of interlaced video data by using the two
different base addresses (BaseOdd and BaseEven) and
vertical start phases (YPE6 to YPE0 and YPO6 to YPO0)
for odd and even fields.
Using the protection address, system memory could be
kept of from prohibited write accesses. If the PCI pointer of
the current transfer reaches or exceeds the protection
address, the SAA7146A stops this transfer and an
interrupt is initiated. No interrupt is set if a protection
violation occurs due to the programming that was done
before the channel has been switched on. To prevent one
field from being transferred into memory, set its base
address (BaseOdd or BaseEven) to the same value as the
protection address.
If the Protection Violation (PV) handling bit and the limit
register are reset, the following data will be ignored until
detection of the End-Of-Window (EOW) signal. In read
mode the DMA control also waits for this signal, to start the
next data transfer. If the PV bit is set, the input of the FIFO
will be locked and the FIFO will be emptied. If the FIFO is
empty the TR_E bit is reset. This feature could be used for
a single capture mode, if the protection address is the
same address as the last pixel in this field. With that, the
SAA7146A will write one field into system memory and
then stop.
If the limit register of any DMA channel (video, VBI data or
audio) has a value other than ‘0000’ the continuous write
mode is chosen. If the actual PCI address hits the
protection address and the PV bit is zero, the FINC stops
the current transfer, sets an interrupt and resets the actual
address to the base address. Regarding this, the
protection address could be used to define a memory
space to which data is sent. The SAA7146A offers the
possibility to monitor the filling level of this memory space.
The limit register defines an address limit, which generates
an interrupt if passed by the actual PCI address pointer.
‘0001’ means an interrupt will be generated if the lower
6 bits (64 bytes) of the PCI address are zero. ‘0010’
defines a limit of 128 bytes, ‘0011’ one of 256 bytes, and
so on up to 1 Mbyte defined by ‘1111’. This interrupt range
can be calculated as follows:
Range = 2
The protection handling modes such as those selected by
the PV bit and the contents of the limit register are shown
in Table 4.
(5 +Limit)
bytes.
1998 Apr 0924
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
SAA7146A
Scaler and PCI circuit (SPCI)
Table 4 Protection violation handling modes
LIMITPVDESCRIPTION
00000Lock input of FIFO and empty FIFO (only in write mode). Unlock FIFO and start next transfer
using the base address at the detection of BOF.
00000Restart immediately at base address.
(1)
XXXX
Note
1. X = don’t care.
handbook, full pagewidth
1Lock input of FIFO, empty FIFO (only in write mode) and then reset TR_E bit. The next transfer
starts with BOF using the corresponding base address, if the TR_E bit is set again. This setting
is useful for single-shot, that means transferring only one frame of a video stream. Therefore
the protection address has to be the same as the address of the last pixel of the field.
positive pitch
positive pitch
positive pitch
Last line
BaseAddr
BaseAddr
ProtAddr
1st line
negative pitch
Last line
2nd line
3rd line
(a) positive line pitch
negative pitch
2nd line
(b) positive line pitch
negative pitch
1st line
Fig.5 Handling of base and protection address using positive and negative line pitch.
ProtAddr
MGG260
1998 Apr 0925
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
SAA7146A
Scaler and PCI circuit (SPCI)
7.2.3AUDIO DMA CONTROL
The SAA7146A provides up to four audio DMA channels,
each using a FIFO of 24 Dwords. Two channels are read
only (A1_in and A2_in) and two channels are write only
(A1_out and A2_out). Because audio represents a
continuous data stream, which is neither line nor field
dependent, the audio DMA control offers only one base
address (BaseAxx) and no pitch register. For FIFO
overflow and underflow the handling of these channels is
done in the same way as the video DMA channels
(see Section 7.2.2).
Table 5 Audio DMA control register
OFFSET
(HEX)
94BaseA1_in31 to 0RWbase address for audio input Channel 1; this value specifies a
98ProtA1_in31 to 2RWprotection address for audio input Channel 1; this address
9CPageA1_in31 to 12RWbase address of the page table, see Section 7.2.4.
A0BaseA1_out31 to 0RWBase address for audio output Channel 1; this value specifies a
A4ProtA1_out31 to 2RWprotection address for audio output Channel 1; this address
A8PageA1_out31 to 12RWbase address of the page table, see Section 7.2.4.
NAMEBITTYPEDESCRIPTION
byte address
could be used to specify a upper limit for audio access in memory
space
−1to0−reserved
MEA1_in11RWmapping enable; this bit enables the MMU
−10 to 8−reserved
LimitA1_in7 to 4RWinterrupt limit; defines the size of the memory range, that
generates interrupt, if its boundaries are passed
PVA1_in3RWprotection violation handling
−2to0−reserved
byte address. The lower two bits are forced to zero.
could be used to specify a upper limit for audio access in memory
space
−1 and 0−reserved
MEA1_out11RWmapping enable; this bit enables the MMU
−10 to 8−reserved
LimitA1_out7 to 4RWinterrupt limit; defines the size of the memory range, that
generates an interrupt, if its boundaries are passed
PVA1_out3RWprotection violation handling
−2to0−reserved
The protection violation handling differs only if the limit
register and the PV bit are programmed to zero. The audio
DMA channel does not wait for the EOF signal, like the
video ones. It does not generate interrupts. The interrupt
range specified by the limit register is defined in the same
way as described in Section 7.2.2. The audio DMA
channels try immediately to transfer data after setting the
transfer enable bits. All registers for audio DMA control,
which are the base address, the protection address and
the control bits are listed in the following Table 5, except
the input control bits (Burst, Threshold), which are listed in
Table 6.
1998 Apr 0926
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
SAA7146A
Scaler and PCI circuit (SPCI)
OFFSET
(HEX)
ACBaseA2_in31 to 0RWBase address for audio input Channel 2; this value specifies a
B0ProtA2_in31 to 2RWprotection address for audio input Channel 2; this address
B4PageA2_in31 to 12RWbase address of the page table, see Section 7.2.4
B8BaseA2_out31 to 0RWBase address for audio output Channel 2; this value specifies a
BCProtA2_out31 to 2RWprotection address for audio output Channel 2; this address
C0PageA2_out31 to 12RWbase address of the page table, see Section 7.2.4
NAMEBITTYPEDESCRIPTION
byte address. The lower two bits are forced to zero.
could be used to specify a upper limit for audio access in memory
space
−1 and 0−reserve
MEA2_in11RWmapping enable; this bit enables the MMU
−10 to 8−reserved
LimitA2_in7 to 4RWinterrupt limit; defines the size of the memory range, that raise an
interrupt, if its boundaries are passed
PVA2_in3RWprotection violation handling
−2to0−reserve
byte address. The lower two bits are forced to zero.
could be used to specify a upper limit for audio access in memory
space
−1 and 0−reserved
MEA2_out11RWmapping enable; this bit enables the MMU
−10 to 8−reserved
LimitA2_out7 to 4RWinterrupt limit; defines the size of the memory range, that raise an
interrupt, if its boundaries are passed
PVA2_out3RWprotection violation handling
−2to0−reserved
1998 Apr 0927
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
7.2.4MEMORY MANAGEMENT UNIT (MMU)
7.2.4.1Introduction
To perform DMA transfers, physically continuous memory
space is needed. However, operating systems such as
Microsoft Windows are working with virtual demand
paging, using a MMU to translate linear to physical
addresses. Memory allocation is performed in the linear
address space, resulting in fragmented memory in the
physical address space. There is no way to allocate large
buffers of physical, continuous memory, except reserving
it during system start-up. Thus decreasing the system
performance dramatically. To overcome this problem the
SAA7146A contains a Memory Management Unit (MMU)
as well. This MMU is able to handle memory fragmented
to 4 kbyte pages, similar to the scheme used by the Intel
8086 processor family. The MMU can be bypassed to
simplify transfers to non-paged memory such as the
graphics adapter’s frame buffer.
7.2.4.2Memory allocation
The SAA7146A’s MMU requires a special scheme for
memory allocation. The following steps have to be
performed:
• Allocation of n pages, each page being 4 kbytes of size,
aligned to a 4 kbyte boundary
• Allocation of one extra page, to be used as page table
• Initialization of the page table.
Allocation of pages is done in physical address space.
Operating systems implementing virtual memory provide
services to allocate and free these pages.
SAA7146A
The page table is stored in a separate page. This limits the
linear address page to a size of 4 Mbytes and results in a
4 kbyte overhead. The page table is organized as an array
of n Dwords, with each entry giving the physical address of
one of the n pages of allocated memory. As pages are
aligned to 4 kbytes, the lower 12 bits of each entry are
fixed to zero.
7.2.4.3Implementation
The SAA7146A has up to 8 DMA channels (3 video,
4 audio and 1 DEBI channel) for which the memory
mapping is done. Each of them provides the linear address
to (from) which it wants to send (read) data during the next
transfer. Their register sets contain a page table base
address (Pagexx) and a mapping enable bit (MExx).
If MExx is set, mapping is enabled.
The MMU checks for each channel whether its address
has been already translated. If translated, its request can
pass to the Internal Arbitration Control (INTAC) managing
the access to the PCI-bus. If not, the MMU starts a bus
transfer to the page table. The page table entry address
could be calculated from the channels PCI address and
the page table base address, as shown in Fig.6. The upper
20 bits of the PCI address are replaced by the upper
20 bits of the according page address to generate the
mapped PCI address.
If the PCI address crosses a 4 kbyte boundary during a
transfer, the MMU stops this transfer and suppresses its
request to the INTAC until it has renewed the page
address, which means replacing the upper 20 bits of the
current address. To reduce latency the SAA7146A will do
a pre-fetch, i.e. it will always try to load the next page
address in advance.
1998 Apr 0928
Philips SemiconductorsProduct specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
7.2.5INTERNAL ARBITRATION CONTROL
The SAA7146A has up to three video DMA channels, four
audio DMA channels and three other DMA channels (RPS,
MMU and DEBI) each trying to get access to the PCI-bus.
To handle this, an Internal Arbitration Control (INTAC) is
needed. INTAC controls on the one hand the PCI-bus
requests and on the other hand the order in which each
DMA channel gets access to the bus.
The basic implementation of the internal arbitration control
is a round-robin mechanism on the top, consisting of the
RPS, the MMU and one of the eight data channels. Data
channel arbitration is performed using a ‘first come first
serve’ queue architecture, which may consist of up to eight
entries.
Each data channel reaching a certain filling level of its
FIFO defined by the threshold, is allowed to make an entry
into the arbitration queue. The threshold defines the
number of Dwords needed to start a sensible PCI transfer
and must be small enough to avoid a loss of data due to an
overflow regarding the PCI latency time. After each job
(Video Transfer Done, VTD) the video channels have to be
emptied and are allowed to fill an entry into the queue,
even if they have not yet reached their threshold.
Concurrently to the entry the channel sets a bit which
prohibits further entries to this channel. In the worst case,
each data channel can have only one entry in the queue.
If each channel wants to access the bus, which means the
queue is full, an order like the one shown below will be
given.
• MMU
• RPS.
SAA7146A
First entry of the data channel queue:
• MMU
• RPS.
Second entry of the data channel queue:
• MMU
• and so on.
If INTAC detects at least one DMA channel in the queue or
an MMU or an RPS request, it signals the need for the bus
by setting the REQ# signal on the PCI-bus. If the GNT#
signal goes LOW, the SAA7146A is the owner of the bus
and makes the PCI master module working with the first
channel selected. The master module tries to transfer the
number of Dwords defined in the Burst Register. For RPS
the burst length is hardwired to four and for the MMU it is
hardwired to two Dwords. After that the master module
stops this transfer and starts a transfer using the next
channel (due to the round-robin).
If a DMA channel gets its transfer stopped due to a retry,
the arbitration control sets the corresponding retry flag.
INTAC tries to end a retried transfer, even if this transfer
gets stopped via the Transfer Enable bit (TR_E). For this
reason the Transfer Enable bits are internally shadowed
by INTAC. A transfer can only be stopped if it has no retry
pending.
The Arbitration Control Registers (Burst and Threshold of
DEBI, Video 1 to 3, Audio 1 to 4) are listed in Table 6.
1998 Apr 0930
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