Philips SAA4979H Technical data

INTEGRATED CIRCUITS

DATA SH EET

SAA4979H

Sample rate converter with
embedded high quality dynamic
noise reduction and expansion port

Product specification 2002 May 28

Philips Semiconductors Product specification

Sample rate converter with embedded high quality
dynamic noise reduction and expansion port

CONTENTS

1 FEATURES
2 GENERAL DESCRIPTION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION

7.1 Digital processing at 1fH level

7.1.1 ITU 656 decoder

7.1.2 Double window and picture-in-picture
processing

7.1.3 Black bar detector

7.1.4 Dynamic noise reduction

7.1.5 Noise estimator

7.2 Embedded DRAM

7.2.1 3.5-Mbit field memory

7.3 Digital processing at 2fH level

7.3.1 Sample rate conversion

7.3.2 Expansion port

7.3.3 Panoramic zoom

7.3.4 Digital colour transient improvement

7.3.5 Y horizontal smart peaking

7.3.6 Non-linear phase filter

7.3.7 Post processing

7.4 Triple 10-bit digital-to-analog conversion

7.5 Microcontroller

7.5.1 Host interface

7.5.2 I2C-bus interface

7.5.3 SNERT-bus

7.5.4 I/O ports

7.5.5 Watchdog timer

7.5.6 Reset

7.6 System controller

7.6.1 Read enable output

7.6.2 Read enable input

7.6.3 Input enable

7.6.4 Horizontal deflection

7.6.5 Vertical deflection

7.6.6 Auxiliary display signal

7.6.7 Read enable 2

7.6.8 Output input enable 2

7.6.9 Reset read 2

7.6.10 Reset write 2

7.7 Line-locked clock generation

7.8 Boundary scan test

8 CONTROL REGISTER DESCRIPTION

8.1 Host interface detail

8.2 Special Function Registers (SFRs)
9 LIMITING VALUES
10 THERMAL CHARACTERISTICS
11 CHARACTERISTICS
12 TRANSFER FUNCTIONS
13 APPLICATION INFORMATION
14 PACKAGE OUTLINE
15 SOLDERING

15.1 Introduction to soldering surface mount
packages

15.2 Reflow soldering

15.3 Wave soldering

15.4 Manual soldering

15.5 Suitability of surface mount IC packages for
wave and reflow soldering methods

16 DATA SHEET STATUS
17 DEFINITIONS
18 DISCLAIMERS
19 PURCHASE OF PHILIPS I2C COMPONENTS

SAA4979H

2002 May 28 2

Philips Semiconductors Product specification

Sample rate converter with embedded high quality
dynamic noise reduction and expansion port

1 FEATURES

• Digital YUV input according to ITU 656 standard

• 4:2:2 field rate upconversion (50 to 100 Hz or

60 to 120 Hz)

• 3.5-Mbit embedded DRAM

• Sample rate conversion for linear zoom and

compression

• Panorama mode

• Dynamic noise reduction

• Noise estimator

• Black bar detection

• Luminance horizontal smart peaking

• Digital Colour Transient Improvement (DCTI)

• Triple 10-bit Digital-to-Analog Converter (DAC)

• Line-locked PLL

• Expansion port for SAA4992H and SAA4991WP

• Double window and Picture-In-Picture (PIP) processing

• Embedded 80C51 microcontroller

• 32-Kbyte internal ROM (mask programmable)

• 512-byte internal RAM

• I2C-bus controlled

• Synchronous No parity Eight bit Reception and

Transmission (SNERT) interface

• Boundary Scan Test (BST).

2 GENERAL DESCRIPTION

The SAA4979H provides an economic stand-alone
solution for 4:2:2 field rate upconversion (50 to 100 Hz
or 60 to 120 Hz) including the required field memory
combined withpicture improvement features and dynamic
field based noise reduction. The IC contains two digital
input channels to allow field or frame based
picture-in-picture processing. It also offers a feature
expansion port for vector based motion estimation and
compensation ICs such as SAA4991WP or SAA4992H.

SAA4979H

3 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V
V
V
V
I

DDD

I

DDA

P
T

DDD
DDA
DDO
DDP

tot
amb

; V

digital supply voltage 3.0 3.3 3.6 V
analog supply voltage 3.15 3.30 3.45 V
I/O supply voltage 3.0 3.3 3.6 V

DDI

protection supply voltage 3.0 5.0 5.5 V
digital supply current − 120 160 mA
analog supply current − 40 50 mA
total power dissipation −−0.9 W
ambient temperature −20 − +70 °C

4 ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

SAA4979H QFP128 plastic quad flat package; 128 leads (lead length 1.6 mm);

PACKAGE

SOT320-2

body 28 × 28 × 3.4 mm; high stand-off height

2002 May 28 3

Philips Semiconductors Product specification

Sample rate converter with embedded high quality
dynamic noise reduction and expansion port

5 BLOCK DIAGRAM

handbook, full pagewidth

]

Y[7:0

8

FAST

SWITCH

H, V

BLACK BAR
DETECTOR

16

REDUCTION

DYNAMIC

NOISE

SOURCE

SELECT

16

LLC1
LLC2

DI17 to DI10
DI27 to DI20

EXT_CLK

OSCI

OSCO
CLK32

HD, VD, ADS

REO, IE, OIE2

RE2, RSTR2
REI, RSTW2

RST

P1.2 to P1.5

SNRST

SNDA,SNCL

SDA, SCL

SOURCE

SELECT

8
8

H

PLL

SYSTEM CONTROLLER

ROM

MICROCONTROLLER

I/O

PORT

SNERT-

BUS

CLK27

MAIN CHANNEL

ITU 656

DECODER 1

SUB CHANNEL

ITU 656

DECODER 2

HREF

CLK32

RAM

2

C-BUS

I

NOISE

ESTIMATOR

2

H, V

16

16

2

SAA4979H

FIELD

MEMORY

3.5 MBIT

16

SAMPLE RATE

CONVERSION

27 to 32 MHz

DOWNSAMPLING

BYPASS

PANORAMIC

ZOOM

UPSAMPLING

SAA4979H

BYPASS

YO7 to YO0
UVO7 to UVO0

YI7 to YI0
UVI7 to UVI0

LUMINANCE CIRCUIT

NON-LINEAR

10

YOUT

UOUT

VOUT

TRIPLE

10-BIT

DAC

POST

PROCESSING

BLANKING

FRAMING

SIDE PANEL

PHASE
FILTER

CHROMINANCE CIRCUIT

10

10

DCTI

Fig.1 Block diagram.

2002 May 28 4

HORIZONTAL

SMART

Y PEAKING

UPSAMPLING

4 : 2 : 2

to

4 : 4 : 4

UV

Y

BCE

BOUNDARY

SCAN

TEST

MHC186

TDI
TCK
TMS
TRST
TDO

Philips Semiconductors Product specification

Sample rate converter with embedded high quality
dynamic noise reduction and expansion port

6 PINNING

SYMBOL PIN TYPE DESCRIPTION

V

DDO1

RSTR2 2 digital output (test input) reset read, source 2
RE2 3 digital output (test input) read enable, source 2
OIE2 4 digital output (test input) output/input enable, source 2
V

SSO1

RSTW2 6 digital input reset write, source 2
DI10 7 digital input ITU 656 input bit 0 (LSB), source 1
DI11 8 digital input ITU 656 input bit 1, source 1
DI12 9 digital input ITU 656 input bit 2, source 1
DI13 10 digital input ITU 656 input bit 3, source 1
DI14 11 digital input ITU 656 input bit 4, source 1
DI15 12 digital input ITU 656 input bit 5, source 1
DI16 13 digital input ITU 656 input bit 6, source 1
DI17 14 digital input ITU 656 input bit 7 (MSB), source 1
V

SSD1

LLC1 16 digital input 27 MHz clock signal, source 1
V

DDD1

V

DDP

DI20 19 digital input ITU 656 input bit 0 (LSB), source 2
DI21 20 digital input ITU 656 input bit 1, source 2
DI22 21 digital input ITU 656 input bit 2, source 2
DI23 22 digital input ITU 656 input bit 3, source 2
DI24 23 digital input ITU 656 input bit 4, source 2
DI25 24 digital input ITU 656 input bit 5, source 2
DI26 25 digital input ITU 656 input bit 6, source 2
DI27 26 digital input ITU 656 input bit 7 (MSB), source 2
V

SSD2

LLC2 28 digital input 27 MHz clock signal, source 2
V

DDD2

TCK 30 digital input test clock
TDI 31 digital input test data input
TMS 32 digital input test mode select
TRST 33 digital input test reset (active LOW)
n.c. 34 to 41 − not connected
TDO 42 digital output test data output
V

DDA1

YOUT 44 analog output Yanalog output
V

SSA1

UOUT 46 analog output −(B − Y) analog output
V

DDA2

1 supply I/O supply voltage 1 (3.3 V)

5 ground I/O ground 1

15 ground digital ground 1

17 supply digital supply voltage 1 (3.3 V)
18 supply protection supply voltage (5 V)

27 ground digital ground 2

29 supply digital supply voltage 2 (3.3 V)

43 supply analog supply voltage 1 (3.3 V)

45 ground analog ground 1

47 supply analog supply voltage 2 (3.3 V)

SAA4979H

2002 May 28 5

Philips Semiconductors Product specification

Sample rate converter with embedded high quality

SAA4979H

dynamic noise reduction and expansion port

SYMBOL PIN TYPE DESCRIPTION

VOUT 48 analog output −(R − Y) analog output
V

SSA2

AGND 50 ground analog ground (without substrate contacts)
BGEXT 51 analog I/O band gap external I/O
V

DDA3

V

SSO2

HD 54 digital output horizontal synchronisation output, display part
VD 55 digital output vertical synchronisation output, display part
V

SSA3

V

DDI

OSCI 58 analog input oscillator input
OSCO 59 analog output oscillator output
CLKEXT 60 digital input external clock input
V

DDD3

CLK32 62 digital output 32 MHz clock output
V

SSD3

V

DDO2

UVI0 65 digital input UV digital input bit 0 (LSB)
UVI1 66 digital input UV digital input bit 1
UVI2 67 digital input UV digital input bit 2
UVI3 68 digital input UV digital input bit 3
UVI4 69 digital input UV digital input bit 4
UVI5 70 digital input UV digital input bit 5
UVI6 71 digital input UV digital input bit 6
UVI7 72 digital input UV digital input bit 7 (MSB)
YI0 73 digital input Y digital input bit 0 (LSB)
YI1 74 digital input Y digital input bit 1
YI2 75 digital input Y digital input bit 2
YI3 76 digital input Y digital input bit 3
YI4 77 digital input Y digital input bit 4
YI5 78 digital input Y digital input bit 5
YI6 79 digital input Y digital input bit 6
YI7 80 digital input Y digital input bit 7 (MSB)
REI 81 digital input read enable input
V

SSO3

IE 83 digital output input enable
REO 84 digital output read enable output
YO7 85 digital output Y digital output bit 7 (MSB)
YO6 86 digital output Y digital output bit 6
YO5 87 digital output Y digital output bit 5
YO4 88 digital output Y digital output bit 4

49 ground analog ground 2

52 supply analog supply voltage 3 (3.3 V)
53 ground I/O ground 2

56 ground analog ground 3
57 supply I/O internal supply voltage (3.3 V)

61 supply digital supply voltage 3 (3.3 V)

63 ground digital ground 3
64 supply I/O supply voltage 2 (3.3 V)

82 ground I/O ground 3

2002 May 28 6

Philips Semiconductors Product specification

Sample rate converter with embedded high quality
dynamic noise reduction and expansion port

SYMBOL PIN TYPE DESCRIPTION

V

DDO3

YO3 90 digital output Y digital output bit 3
YO2 91 digital output Y digital output bit 2
YO1 92 digital output Y digital output bit 1
YO0 93 digital output Y digital output bit 0 (LSB)
V

SSO4

UVO7 95 digital output UV digital output bit 7 (MSB)
UVO6 96 digital output UV digital output bit 6
UVO5 97 digital output UV digital output bit 5
UVO4 98 digital output UV digital output bit 4
V

DDO4

UVO3 100 digital output UV digital output bit 3
UVO2 101 digital output UV digital output bit 2
UVO1 102 digital output UV digital output bit 1
UVO0 103 digital output UV digital output bit 0 (LSB)
V

SSD4

V

DDD4

ADS 106 digital output auxiliary display signal
SNCL 107 digital output SNERT clock
SNDA 108 digital I/O SNERT serial data
V

SSO5

SNRST 110 digital I/O SNERT restart (port 1.0)
SDA 111 digital I/O I
SCL 112 digital I/O I
P1.5 113 digital I/O port 1 data input/output signal 5
P1.4 114 digital I/O port 1 data input/output signal 4
P1.3 115 digital I/O port 1 data input/output signal 3
P1.2 116 digital I/O port 1 data input/output signal 2
V

DDO5

RST 118 digital input microcontroller reset input
n.c. 119 to 127 − not connected
BCE 128 digital input boundary scan compliant enable

89 supply I/O supply voltage 3 (3.3 V)

94 ground I/O ground 4

99 supply I/O supply voltage 4 (3.3 V)

104 ground digital ground 4
105 supply digital supply voltage 4 (3.3 V)

109 ground microcontroller I/O ground

2

C-bus serial data (port 1.7)

2

C-bus clock (port 1.6)

117 supply microcontroller I/O supply voltage (3.3 V)

SAA4979H

2002 May 28 7

Philips Semiconductors Product specification

Sample rate converter with embedded high quality
dynamic noise reduction and expansion port

handbook, full pagewidth

V

DDO1

RSTR2

RE2

OIE2

V

SSO1

RSTW2

DI10
DI11
DI12
DI13
DI14
DI15
DI16
DI17

V

SSD1

LLC1

V

DDD1
V

DDP
DI20
DI21
DI22
DI23
DI24
DI25
DI26
DI27

V

SSD2

LLC2

V

DDD2

TCK

TDI

TMS

BCE

n.c.

n.c.

n.c.

n.c.

n.c.

n.c.

n.c.

n.c.

128

127

126

125

124

123

122

121

120

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

n.c.
119

RST
118

DDO5

V

117

P1.2

P1.3

P1.4

P1.5

116

115

114

113

SAA4979H

SCL
112

SDA
111

SSO5

SNRST

V

110

109

SNDA

108

SNCL

107

ADS

106

DDD4VSSD4

V

105

104

UVO0

103

UVO1

102

UVO2

101

UVO3

V

100

DDO4

UVO4

999897

SAA4979H

UVO5

96

UVO6

95

UVO7
V

94

SSO4

93

YO0

92

YO1

91

YO2

90

YO3
V

89

DDO3

88

YO4

87

YO5

86

YO6

85

YO7

84

REO

83

IE
V

82

SSO3

81

REI

80

YI7

79

YI6

78

YI5

77

YI4

76

YI3

75

YI2

74

YI1

73

YI0

72

UVI7

71

UVI6

70

UVI5

69

UVI4

68

UVI3

67

UVI2

66

UVI1

65

UVI0

33343536373839404142434445464748495051525354555657585960616263

n.c.

n.c.

n.c.

n.c.

n.c.

n.c.

n.c.

n.c.

TRST

TDO

DDA1

V

YOUT

V

SSA1

UOUT

DDA2

V

Fig.2 Pin configuration.

2002 May 28 8

VOUT

V

SSA2

AGND

DDA3VSSO2

V

BGEXT

HD

VD

SSA3

V

V

DDI

OSCI

OSCO

CLKEXT

DDD3

V

SSD3

CLK32

V

64

DDO2

V

MHC200

Philips Semiconductors Product specification

Sample rate converter with embedded high quality
dynamic noise reduction and expansion port

7 FUNCTIONAL DESCRIPTION

7.1 Digital processing at 1fH level

7.1.1 ITU 656
The SAA4979H provides 2 digital video input channels,

which comply to the ITU 656 standard.
720 active video pixels per line are processed at a

line-locked clock of 27 MHz, which has to be provided by
the signal source. Luminance and chrominance
information have to be multiplexed in the following order:
CB1,Y1,CR1,Y2, ... Timing reference codes must be
inserted at the beginning and end of each video line
(see Table 1):

• A ‘Start of Active Video’ (SAV) code before the first
active video sample (see Table 2)

• A ‘End of Active Video’ (EAV) code after the last active
video sample (see Table 2).

Table 1 ITU data format

DECODER

Theincomingactive video data must belimitedto1 to 254,
since the data words 00H and FFH are used for
identification of the timing reference headers.

The digital signal input levels should comply to the
CCIR-601 standard (see Fig.3). The data stream is
decoded into the internal 4 :2:2 YUV format at a

13.5 MHz clock rate. If required the sign of the UV signals
canbe inverted for bothchannels (control inputs: uv_sign1
and uv_sign2).

The signal source of the main channel can be selected
from both inputs by the internal microcontroller (control
input: Select_data_input1).

SAA4979H

BLANKING

PERIOD

... 80 10 FF 00 00 SAV C

Table 2 SAV/EAV format

BIT 7

1 field bit

1st field: F = 0;
2nd field: F = 1

TIMING

REFERENCE

CODE (HEX)

BIT 6

(F)

TIMING

720 PIXELS YUV 4 :2:2 DATA

0Y0CR0Y1CB2 Y2 ... CR718 Y719 FF 00 00 EAV 80 10 ...

B

BIT 5

(V)

vertical blanking bit
VBI: V = 1;
active video: V = 0

H = 0 in SAV format;
H = 1 in EAV format

BIT 4

(H)

REFERENCE

CODE (HEX)

BIT 3

(P3)

reserved; evaluation not
recommended (protection bits
according to ITU 656)

BIT 2

(P2)

BLANKING

PERIOD

BIT 1

(P1)

BIT 0

(P0)

2002 May 28 9

Philips Semiconductors Product specification

Sample rate converter with embedded high quality
dynamic noise reduction and expansion port

+

handbook, full pagewidth

255

+

235

+

128

+

white

LUMINANCE 100%

16

0

black

a. Y output range. b. U output range (CB). c. V output range (CR).

+

255

+

240

+

212

+

128

+

44

+

16

0

blue 100%
blue 75%

colourless

U-COMPONENT

yellow 75%
yellow 100%

+

255

+

240

+

212

+

128

+

44

+

16

0

SAA4979H

red 100%
red 75%

colourless

V-COMPONENT

cyan 75%

cyan 100%

MHC201

It should be noted that the input levels are limited to 1 to 254 in accordance with ITU 601/656 standard.

Fig.3 Digital video input levels.

7.1.2 DOUBLE WINDOW AND PICTURE-IN-PICTURE

PROCESSING

Data from the sub channel can be inserted into the data
stream of the main channel by means of afast switch.The
two channels can be used together with one or two
external field memoriesto implement, for example, double
window or PIP processing. Both field based and frame
based PIP processing is supported. The synchronization
of the sub channel to the main channel is achieved by
providingsynchronized read signals(RE2and RSTR2) for
the external field memories, whereas the write signals
needto be providedtogether with the incomingdata by the
external signal source.

A multi-PIP mode is also supported by freezingthe data in
the internal field memory within certain areas via the
programmable internal control signal IE

.

int

7.1.3 BLACK BAR DETECTOR
Black bar detection searches for the last black line in the

upper part of the screen and for the first black line in the
lower part of the screen. The detection is done within a
programmable window (control inputs: bbd_hstart,
bbd_hstop, bbd_vstart and bbd_vstop). To avoid
disturbances of LOGOs in the video, the window can be
shifted to the horizontal centre of the lines. A video line is
considered to be black if the luminance values of that line
within the detection window are not greater than a certain
slice level (control input: bbd_slice_level) for more than a
specific number of pixels (control input: bbd_event_value).

The numbers of the first and the last active video line can
be read out by the microcontroller (control outputs:
bbd_1st_videoline and bbd_last_videoline).

2002 May 28 10

Philips Semiconductors Product specification

Sample rate converter with embedded high quality
dynamic noise reduction and expansion port

7.1.4 DYNAMIC NOISE REDUCTION

The main function of the noise reduction is shownin Fig.4.
It is divided into two signal paths for chrominance and
luminance. In principal two operating modes can be used,
the fixed and the adaptive mode. In both modes the
applied frequency range, in which the noise reduction
takes place, can be reduced or not reduced (control input:
unfiltered).

The noise reduction operates field recursive with an
averaging ratio (K factor) between fresh (new) and over
previousfieldsaveraged(old)luminanceandchrominance
values. Noise reduction can be activated by forcing the
NREN control bit to HIGH. If NREN is LOW the noise
reduction block is bridged via a data multiplexer.

Inthe fixed mode,thenoise reduction producesaconstant
weighted input averaging. Because of smearing effects
this mode should not be used for normal operation except
for K = 1. The fixed mode can be activated separately for
chrominance (control input: chromafix) and luminance
(control input: lumafix).

It should be noted that recursion is done over fields, and
that pixel positions between the new and old fields always
have a vertical offset of one line. So averaging is not only
done in the dimension of time but also in the vertical
direction.Therefore averaging verticallyon, for example, a
vertical black to white edge would produce a grey result.

The averaging in chrominance can optionally be slaved to
the luminance averaging (control input: Klumatochroma),
in that case chrominance differences are not taken into
account for the K factor setting of the chrominance signal
path.

The noise reduction scheme also decreases the
cross-colour patterns effectively if the adaptive noise
reductionfor the averagingin chrominance isslaved to the
luminance averaging (control input: Klumatochroma). The
cross-colour pattern does not produce an increase of the
measured luminance difference, therefore this pattern will
be averaged over many fields.

SAA4979H

In the adaptive mode, the averaging ratio is based on the
absolute differences of the inputs of luminance and
chrominancerespectively. If the absolutedifferenceis low,
only a small part of the fresh data will be added. In cases
of high difference, much of the fresh data will be taken.
This occurs either in situations of movement or where a
significant vertical contrast is seen. The relationship
between the amount of movement andthe K factor values
is defined in a look-up table where the steps can be
programmed (control input: Kstep).

2002 May 28 11

Philips Semiconductors Product specification

Sample rate converter with embedded high quality
dynamic noise reduction and expansion port

handbook, full pagewidth

control input:
unfiltered

data input

UV7 to UV0

8

new U/V

delta U/V

LOW-PASS

FILTER 1

LF delta U/V

Dfielddelay

UV7 to UV0

8

old U/V

control input:
unfiltered

data input

Y7 to Y0

8

new Y

delta Y

LOW-PASS

FILTER 1

SAA4979H

Dfielddelay

Y7 to Y0

8

old Y

LF delta Y

control input:
Cadapt_gain

ABS/LIMITER

UV

AVERAGE

LOW-PASS

FILTER 2

LUT

Kchroma

Kchromafix

Kluma

control input:
noiseshape

control input:
chromafix and
Klumatochroma

NOISE SHAPE

Dtomemory
UV7 to UV0

HF delta U/V

processed UV

8

control input:
Yadapt_gain

ABS/LIMITER

LOW-PASS

FILTER 2

LUT

Klumafix

Kluma

control input:
noiseshape

MHC202

HF delta Y

control input:
lumafix

processed Y

NOISE SHAPE

8

Dtomemory

Y7 to Y0

Fig.4 Schematic diagram of noise reduction.

2002 May 28 12

Philips Semiconductors Product specification

Sample rate converter with embedded high quality
dynamic noise reduction and expansion port

7.1.4.1 Band-splitting

The frequencies of the difference signals of luminance
(delta Y) and chrominance (delta U/V) can be split
optionally into an upper band (HF) and a lower band (LF)
with a low-pass filter in both signal paths. The lower
frequency band signals (LF delta Y and LF delta U/V) are
used as input for the noise reduction function.

The lower frequency band of the difference signals can
also be used for the motion detection. If, for example, only
the lower frequency band contains information, the
specific picture content does not move or is moving slowly.

Optionallyit is possibleto bridge theband-splitting (control
input: unfiltered = 1).

7.1.4.2 Motion detection

The same signals (the noise reduction is applied to) are
also used to detect the amount of motion in the difference
signals. Therefore, the absolute values of the difference
signals are generated and limited to a maximum value.
Theabsolute values of thedifferencesignal of U and V are
then averaged. The signals are low-pass filtered for
smoothingthesesignals.Thefiltered signals are amplified,
depending on the setting of the control inputs:
Yadapt_gain and Cadapt_gain respectively.

The amplified signals, which correlate to the amount of
movement in the chrominance or luminance signal path,
are transferred into 1 out of 9 possible K factor values via
look-up tables. The look-up tables consist of 9 intervals,
each related to one K factor. The boundaries between the
9 intervals are defined by 8 programmable steps (control
inputs:Kstep0 to Kstep7). The step values arevalidfor the
look-uptablesforboth the chrominance and theluminance
path. For example, signal values between Kstep2 and
Kstep3 result in a K factor of K =3/8.

7.1.4.3 K factor

The amount of noise reduction (field averaging) is
described my means of the K factor. When K = 1 no
averaging is applied and the new field information is used.
When K = 0 no averaging is applied and thus only the old
field information is used like in a still picture mode. All
values inbetween mean that a weighted averaging is
applied. It is possible to use fixed K factor values if the
control inputs lumafix or chromafix are set to logic 1. The
possible fixed K factor values of the control inputs
Klumafix and Kchromafix are given in Table 6.

7.1.4.4 Noise shape

Possible shadow picture information in the chrominance
and luminance path, resulting from a low K factor value,
will be eliminated if the noise shaping is activated. The
noise shaping function can be switched off via the
microcontroller (control input: noiseshape).

7.1.5 NOISE ESTIMATOR
The noise level of the luminance signal can be measured

within a programmable window (control inputs: ne_hstart,
ne_hstop, ne_vstart and ne_vstop). The correlation in flat
areas is used to estimate the noise in the video signal.
A large number of estimates of the noise is calculated for
every video field. Such an estimate is obtained by
summing absolute differences between current pixel
values and delayed pixel values within blocks of 4 pixels.
Within the lower part of the total range of possible
estimates15 intervals are defined. Eachintervalis defined
by a lower boundary and an upper boundary. The lower
boundary is equal to the number of the interval, whereas
the upper boundary has a fixed relationship to the lower
boundary (control input: gain_upbnd).

The lower boundary is increased or decreased by 1 in
each field until an interval is found which contains at least
a predefined number of estimates, and is at thesame time
lowestin the range. Thevalueofthe lower boundary ofthis
interval determines the current noise figure output. The
predefined number of estimates can be set via the
microcontroller (control input: wanted_value), and good
results were obtained with a value which is approximately

0.27% of the total number of blocks.
For video fields with a lot of noise the number of small

differences is very low, that means the number of noise
estimates in the lower intervals is close to 0. Contrary to
this, for clean sequences this number is very high. This
means that for clean sequences the noise estimate figure
will be close to 0, and for sequences with a lot of noise the
noise estimate figure (control output: nest) will reach 15.

To improve the performance of the noise estimator,
severalfunctionsareimplementedwhich can be controlled
by the microcontroller. To increase the sensitivity of the
noise measurement a prefilter with different gain settings
is available (control input: Ypscale). Since the video
content, e.g. sequences with a lot of high frequencies,can
influence the noise estimate figure, a detail-counter is
built-in.

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Philips Semiconductors Product specification

Sample rate converter with embedded high quality
dynamic noise reduction and expansion port

The detail-counter calculates the number of absolute
differences between current and previous pixels within a
programmable interval defined by the control inputs
lb_detail and upb_detail. The result of the 16-bit
detail-counter (control outputs: detail_cnt_h and
detail_cnt_l) can be used to increase or decrease the
result of the noise estimation figure (control input:
compensate).

In order to reduce the effect of clipping, only the blocks
where the sum of the luminance value is within a
predefined range are taken into account. The control
signal clip_offs can be used to increase or decrease this
range. A grey-counter gives information whether enough
pixels with values in the grey range are present in a video
field (control output: grey_cnt). When this number is lower
than a predefined threshold, e.g. for complete fields
towards black or white, all blocks are taken into account.

7.2 Embedded DRAM

7.2.1 3.5-MBIT FIELD MEMORY

Thebasic functionality ofthefield memory, whichisshown
in Fig.5, is similar to the SAA4956TJ. The memory size is
extended to 3538944 bits. The data path is 16-bit wide
(8-bitchrominanceand 8-bit luminance). The fieldmemory
is capable of storing, for example, up to 307 video lines of
720 pixels in a 4:2:2 format. After writing or reading
18 words of 16-bit width, a data transfer is performed from
the serial to parallel data registers (writing) or from the
parallel to the serial registers (reading). The field memory
has one write interface (controller and registers) to store
1fHdata and two read interfaces, one to read field delayed
1fH data for the noise reduction function and the other to
read 2fHdata for the following data processing. Since two
asynchronous clock domains are involved (SWCKint as
1fHclock and SRCKint as 2fHclock) the read and write
access to the memory array is controlled asynchronously
by the memory arbitration logic triggered via request and
acknowledge pulses.

The write operation starts with a reset write (RSTWint)
address pointer operation during the write enable (WEint)
LOW phase. The RSTWint LOW-to-HIGH transition,
referred to the rising edge of the write clock SWCKint,
must be at least 18 clock cycles ahead of the first written
data (WEint HIGH) and 18 clock cycles after the last
written data. The reset write transfers data temporarily
stored in theserial write registers to the memory arrayand
resets the write counter to the lowest address. Write
enable (WEint) is used to enable or disable a data write
operation. The WEintsignal controls the data inputs
D0 to D15.

In addition, the internal write address pointer is
incremented if WEint is HIGH at the positive transition of
the SWCKint write clock. The data is latched if WEint was
HIGH at the previous positive transition of SWCKint. Input
enable (IEint) LOW can also suppress the storage of the
datainto the memory arraybutdoes not influencethewrite
pointerincrement. It isused to freeze partsof the fielddata
e.g for PIP processing.

The read operation starts with a reset (RSTRint) of the
read address pointer during the read enable (REint) LOW
phase. The RSTRint LOW-to-HIGH transition, referred to
the rising edgeof the read clock SRCKint, must beat least
18 clock cycles ahead of the first read data (REint HIGH)
and18 clock cycles afterthe last read data.The reset read
resetstheread counter to the lowestaddressandrequests
a read operation of the data of the lowest address to the
serial read register. Read enable (REint) is used to enable
or disable the read operation. The REint controls the data
outputs Q0 to Q15. REint HIGH increments the read
counter.

In parallel to the write operation a read2 operation is done
using the same control signals as the write operation:
SWCKint, WEint and RSTWint. It reads the old data of the
previous field. The data Qold is needed as data input
(Dfielddelay) for the noise reduction.

When the WEint signal is HIGH it indicates that active
video (valid 1fH data) is to be stored. The start of WEint
HIGH is triggered by the H and V status bits of the ITU
data stream. The start of WEint HIGH can be delayed by
the control signals weint_hstart (number of clock delays)
andweint_vstart (number ofvideolines delay). Thestopof
WEint HIGH is controlled by weint_hstop and weint_vstop.

When the IEint signal is HIGH it indicatesthat active video
(valid 1fH data) is also to be stored. The video data is not
stored and earlier written data is maintained (frozen) if
WEint is HIGH and IEint is LOW.The startof IEintHIGH is
triggeredby the H and V status bitsofthe ITU data stream.
The start of IEint HIGH can be delayed by the control
signals ieint_hstart (number of clock delays) and
ieint_vstart (number ofvideo lines delay). The stop of IEint
HIGH is controlled by ieint_hstop and ieint_vstop.

RSTWint is triggered by the V status bit of the ITU data
stream.

RSTRintis identical to the VD output signal.
REint is provided by the following sample rate conversion

to gather 2fH data if it is needed.

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Philips Semiconductors Product specification

Sample rate converter with embedded high quality
dynamic noise reduction and expansion port

handbook, full pagewidth

D15 to D0 and IEint WEint RSTWint SWCKint

17

SERIAL WRITE REGISTER

18-WORD (×17)

18 × (16 + 1)

PARALLEL WRITE REGISTER

18-WORD (×17)

18 × (16 + 1)

MEMORY ARRAY

221184-WORD (×16)

address

and

control

SAA4979H

SERIAL WRITE CONTROLLER

write control
(requests
reset/next)

WRITE ADDRESS

COUNTER

READ2 ADDRESS

COUNTER

MEMORY

ARBITRATION

LOGIC

18 × 16

PARALLEL READ2 REGISTER

18-WORD (×16)

18 × 16

SERIAL READ2 REGISTER

18-WORD (×16)

read2
acknowledge

SERIAL READ2 CONTROLLER

WEint RSTWint SWCKint Qold15 to Qold0 Q15 to Q0

read2
control
(requests
reset/next)

PARALLEL READ REGISTER

SERIAL READ REGISTER

18 × 16

18-WORD (×16)

18 × 16

18-WORD (×16)

SERIAL READ CONTROLLER

1616

REint RSTRint SRCKint

read
control
(requests
reset/next)

READ ADDRESS

COUNTER

read
acknowledge

MHC190

Fig.5 Schematic diagram of 3.5-Mbit field memory.

2002 May 28 15

Philips Semiconductors Product specification

Sample rate converter with embedded high quality
dynamic noise reduction and expansion port

7.3 Digital processing at 2fH level

7.3.1 S

The sample rate conversion block is used to obtain
848 active pixels per line out of the original 720 pixels
according to the relation of the two sampling frequencies
(32 MHz and 27 MHz). The interpolation for phase
positions between the original samples is achieved with a
variable phase delay filter with 10 taps for luminance
signals and 6 taps for chrominance signals.

The conversion toa higher samplefrequency of 32 MHz is
done to improve the motion estimation performance in
combination with external feature ICs, which can process
up to 848 pixels per line at a 32 MHz clock. Bypassing this
function keeps the original 720 pixels per line (control
input: bypass_FSRC).

7.3.2 E

For a further extension of the system an expansion port is
available, which is applicable for eithera 4:2:2format or
a reduced 4:1:1 format for data input and output at a
32 MHz line-locked clock; see Table 3. However, the
internal data is processed in a 8-bit wide 4 :2:2format.

To generate the 4:1:1 format at the output the U and V
samples from the 4 : 2 : 2 data stream are filtered by a
low-pass filter, before being subsampled with a factor of 2
and formatted to 4:1:1 format. Bypassing this function
keeps the data in the 4:2:2 format.

AMPLE RATE CONVERSION

XPANSION PORT

An internal bandwidth detector is implemented to detect
whetherthe colour differencesignals provide eitherthe full
4:2:2bandwidth or a reduced 4 : 1 : 1 bandwidth.
Therefore absolute differences between original data and
downsampled data are calculated and can be read out by
the microcontroller (control output: UV_bw_detect). Low
absolute differences indicate that the original data does
not contain the full 4:2:2bandwidth. This information
canbe used toswitch the upsampleand downsample filter
on or off (control inputs: bypass_upsampling and
bypass_downsampling). Bandwidth detection is done
within a programmable window (control inputs: bw_hstart,
bw_hstop and bw_vstart, bw_vstop).

Inthe event ofa 4 : 1 : 1 format atthe input anupconverter
to 4:2:2 is applied with a linear interpolation filter for
creation of the extra samples. These are combined with
the original samples from the 4 : 1 : 1 stream.

The first phase of the YUV data stream is available on the
output bus twoclock cycles afterthe rising edge of theREI
input signal. The start position, when the first phase of the
YUV data stream arrives on the input bus, can be set via
the control register exp_hstart.

The luminance output signal is in 8-bit straight binary
format, whereas the chrominance output signals are in
twos complement format. The input data at the expansion
slot is expected in the same format. U and V input signals
are inverted if the corresponding control bit mid_uv_inv is
set.

SAA4979H

Table 3 YUV formats

OUTPUT PIN 4:1:1 FORMAT 4:2:2 FORMAT INPUT PIN

YO7 Y07 Y17 Y27 Y37 Y07 Y17 YI7
YO6 Y06 Y16 Y26 Y36 Y06 Y16 YI6
YO5 Y05 Y15 Y25 Y35 Y05 Y15 YI5
YO4 Y04 Y14 Y24 Y34 Y04 Y14 YI4
YO3 Y03 Y13 Y23 Y33 Y03 Y13 YI3
YO2 Y02 Y12 Y22 Y32 Y02 Y12 YI2
YO1 Y01 Y11 Y21 Y31 Y01 Y11 YI1

YO0 Y00 Y10 Y20 Y30 Y00 Y10 YI0
UVO7 U07 U05 U03 U01 U07 V07 UVI7
UVO6 U06 U04 U02 U00 U06 V06 UVI6
UVO5 V07 V05 V03 V01 U05 V05 UVI5
UVO4 V06 V04 V02 V00 U04 V04 UVI4
UVO3 −−−−U03 V03 UVI3
UVO2 −−−−U02 V02 UVI2
UVO1 −−−−U01 V01 UVI1
UVO0 −−−−U00 V00 UVI0

2002 May 28 16