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SAA2520
Stereo filter and codec for MPEG
layer 1 audio applications
Preliminary specification
File under Integrated Circuits, IC01
August 1993
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
FEATURES
• Stereo filtering and codec functions in a single chip
• MPEG coded interface
• Filtered data interface
• Baseband audio data interface
• LT interface to microcontroller
• Clock generator
• Low operating voltage capability.
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
SAA2520GP
(1)
Note
1. SOT205-1; 1996 August 26.
PINS PIN POSITION MATERIAL CODE
44 QFP plastic SOT205AG
SAA2520
GENERAL DESCRIPTION
The SAA2520 performs the sub-band filtering and audio
frame codec functions to provide efficient audio
compression/decompression for MPEG (11172-3) Layer1
applications. It is capable of functioning as a stand-alone
decoder but requires the addition of an adaptive masking
threshold processor (SAA2521) in order to function as a
highly efficient encoder.
PACKAGE
handbook, full pagewidth
FS256
SBDIR
SBEF
SWS
SCL
SDA
1
7
11
20
19
21
CLK24 X22OUT X24OUT
CLK22 X22IN X24IN
38 39 40 41 42 43 28,44
CLOCK GENERATOR
STEREO
SUB-BAND
FILTER
PROCESSOR
BASEBAND
INTERFACE
5,37
V
SS
SERIAL
FILTERED
DATA
INTERFACE
FDAF
FDAC FSYNC
V
DD
15
FRESET
SAA2520
CODEC
14 13 36 35 34 33 32 22 29 618 17 16
SYNCDAI
FDIR
SUB-BAND
SERIAL
INTERFACE
MICROPROCESSOR
INTERFACE & CONTROL
LTCLK
LTCNT1 LTENA
PWRDWN
LTDATA
RESET
8
SBDA
9
SBCL
10
SBWS
12
SBMCLK
2
MUTEDAC
3
DEEMDAC
4
ATTDAC
MLB125
URDALTCNT0
Fig.1 Block diagram.
August 1993 2
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
DD
X24IN
42
X22IN
X22OUT
41
40
SAA2520
handbook, full pagewidth
FS256
MUTEDAC
DEEMDAC
ATTDAC
V
SS
URDA
SBDIR
SBDA
SBCL
SBWS
SBEF
V
X24OUT
44
43
1
2
3
4
5
6
7
8
9
10
11
CLK24
39
V
CLK22
38
SS
LTCNT1
373635
LTCNT0
LTENAPWRDWN
34
33
32
31
30
29
28
27
26
25
24
23
LTCLK
LTDATA
T0
T1
RESET
V
DD
DSC0
DSC1
DSC2
DSC3
DSC4
SAA2520
handbook, full pagewidth
AUDIO
AMPLIFIER
DAC
MICROCONTROLLER
12
13
14
15
FDIR
SYNCDAI
FRESET
SBMCLK
Fig.2 Pin configuration.
digital audio interface
control
system micro interface
power down
reset
16
17
FDAF
FSYNC
18
19
SCL
FDAC
SAA2520
20
SWS
21
SDA
22
MLB126
MPEG interface
MPEG
source
MLB127
Fig.3 MPEG decoder system data flow diagram.
August 1993 3
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
SAA2520
audio applications
PINNING
SYMBOL PIN DESCRIPTION TYPE
2
FS256 1 (Filtered)-I
input with pull-down
MUTEDAC 2 DAC control/output expander O
DEEMDAC 3 DAC control/output expander O
ATTDAC 4 DAC control/output expander O
V
SS
5 supply ground (0 V)
URDA 6 unreliable drive processing data; CMOS level I
SBDIR 7 sub-band I
SBDA 8 sub-band I
SBCL 9 sub-band I
SBWS 10 sub-band I
SBEF 11 sub-band I
SBMCLK 12 sub-band I
input with pull-down
SYNCDAI 13 DAI synchronization pulse O
FDIR 14 (Filtered)-I
FRESET 15 reset signal for SAA2521 O
FSYNC 16 Filtered-I
FDAF 17 Filtered-I
pull-down
FDAC 18 Filtered-I
pull-down
SCL 19 I
SWS 20 I
SDA 21 I
2
S bit clock; 4 mA, 3-state output + CMOS input with pull-down I/O
2
S-word select; 4 mA, 3-state output + CMOS input with pull-down I/O
2
S baseband data filter; 4 mA, 3-state output + CMOS input with pull-down I/O
PWRDWN 22 power-down mode; CMOS level I
DSC4 23 test pin
DSC3 24 test pin
DSC2 25 test pin
DSC1 26 test pin
DSC0 27 test pin
V
DD
28 positive supply voltage (+5 V)
RESET 29 system reset; CMOS level with pull-down and hysteresis I
T1 30 test pin; do not connect
T0 31 test pin; do not connect
LTDATA 32 LT interface data; 4 mA, 3-state output + CMOS input with pull-down I/O
LTCLK 33 LT interface bit clock; CMOS level I
S clock; 256 × sample frequency. 12 mA 3-state output + CMOS
2
S direction: (SWBS, SBCL, SBDA); CMOS level I
2
S data; 4 mA, 3-state output + CMOS input with pull-down I/O
2
S bit clock; 4 mA, 3-state output + CMOS input with pull-down I/O
2
S word select; 4 mA, 3-state output + CMOS input with pull-down I/O
2
S byte error flag; CMOS level I
2
S clock, 6.144 MHz locked to FS256; 8 mA, 3-state output + CMOS
2
S direction: (FDAC, FDAF, SDA); O
2
S sync signal for SAA2521 O
2
S sub-band filter data; 4 mA, 3-state output + CMOS input with
2
S sub-band codec data; 4 mA, 3-state output + CMOS input with
I/O
O
I/O
I/O
August 1993 4
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
SAA2520
audio applications
SYMBOL PIN DESCRIPTION TYPE
LTENA 34 LT interface enable; CMOS level I
LTCNT0 35 LT interface control; CMOS level I
LTCNT1 36 LT interface control; CMOS level I
V
SS
CLK22 38 22.5792 MHz buffered output O
CLK24 39 24.576 MHz buffered output O
X22IN 40 22.5792 MHz crystal input I
X22OUT 41 22.5792 MHz crystal output O
X24IN 42 24.576 MHZ crystal input I
X24OUT 43 24.576 MHz crystal output O
V
DD
37 supply ground (0 V)
44 positive supply voltage (+5 V)
August 1993 5
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
handbook, full pagewidth
ALLOCATION &
SCALE FACTOR
INFORMATION
TABLE
SCALING &
QUANTIZATION
Fig.4 Encoding mode.
base band
samples
from SAA2521
SUB-BAND
FILTER
sub - band
samples
allocation information
and scale factor indices
SYNC AND
CODING
INFORMATION
quantized samples
FORMATTER
MLB128
SAA2520
MPEG
OUTPUT
DATA
handbook, full pagewidth
MPEG
input
data
FORMATTER
DE–
sync/coding
allocation
scale factor
quantized
samples
CONTROL
SCALE
FACTOR
ARRAY
& ALLOCATION
DEQUANTIZATION
Fig.5 Decoding mode.
MULTIPLY
OUTPUT
CONTROL
sub-band
samples
MLB129
SUB-BAND
FILTER
base band
samples
August 1993 6
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
FUNCTIONAL DESCRIPTION
Coding System
MPEG coding achieves highly efficient digital encoding of
audio signals by using an algorithm based on the
characteristics of the human auditory system.
The broad-band audio signal is split into 32 sub-band
signals during encoding. For each of the sub-band signals
the masking threshold is calculated. The samples of the
sub-bands are incorporated in the signal with an accuracy
that is determined by the signal to masking threshold ratio
for that sub-band.
During decoding, the sub-band signals are reconstructed
and combined into a broadband audio signal. The
integrated filter processor performs the splitting (encoding)
and joining (decoding) including the corresponding
formatting functions.
For encoding, a SAA2521 is necessary to calculate the
masking threshold and required accuracy of the sub-band
samples.
SAA2520
After sync and coding information, allocation data and the
scale factors are used to correctly fill the scale factor array.
This is followed by a process of multiplication to provide
de-quantization and de-scaling of the samples.
The decoded sub-band samples, which are represented in
24-bit two's complement notation, are processed by the
sub-band filters and reconstituted into a single digital audio
signal.
RESET
Reset must be active under the following conditions:
1. From system power-up until CLK24 has executed
more than 24 clock cycles.
2. From the falling edge of PWRDWN for a period
equivalent to 24 cycles of CLK24 + oscillator start-up
time. This is typically >1 ms, however, this value is
crystal dependent.
PWRDWN
Encoding (See Fig.4)
An encoding algorithm table is used during the coding
process but, due to the Adaptive Allocation functions of the
SAA2521, this may change with every frame. The table is
therefore calculated for each frame by the SAA2521 and
then transferred to the SAA2520.
A frame contains 2 × 384 samples of Left and Right audio
data. This results in 12 samples per sub-band
(32 sub-bands). The samples of the greatest amplitude are
used to determine the scale factor for a given sub-band.
All samples are then scaled to represent a fraction of the
greatest amplitude.
Once scaled, the samples are quantized to reduce the
number of bits to correspond with the allocation table as
calculated by the SAA2521. Synchronization and coding
information data is then added to result in a fully encoded
MPEG signal.
Decoding (See Fig.5)
All essential information (synchronization, system
information, scale factors and encoded sub-band
samples) are conveyed by incoming data. Decoding is
repeated for every frame.
A HIGH input applied to this pin will halt all internally
generated clock signals. As a result, chip activity will halt
completely with outputs frozen in the state which was
current at the time of PWRDWN activation.
The bi-directional outputs: LTDATA, FDAC, FDAF, SDA,
SBWS, SBCL and SBDA will be 3-stated.
Crystal Oscillators
A 24.576 MHz crystal together with some external
components form the 24.576 MHz oscillator (pins 42 and
43). Similarly a 22.5792 MHz oscillator (pins 40 and 41) is
formed by similar peripheral components together with an
appropriate crystal (see Fig.6).
The component values shown apply only to crystals from
the Philips 4322 156 series which exhibit an equivalent
series resistance of ≤ 40 Ω.
August 1993 7
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
handbook, full pagewidth
Component values apply only to crystals from the Philips 4322 156 series.
C2 33 pF
C1 33 pF
C3 33 pF
C4 33 pF
22.5792
MHz
X1
24.576
MHz
X2
R1
1 MΩ
R2 1 kΩ
R4
1 MΩ
R3 1 kΩ
X22OUT
X24OUT
Fig.6 Crystal oscillator components.
X22IN
X24IN
SAA2520
40
41
42
43
SAA2520
MLB130
channel
SWS
SCL
SDA
bit :
left 32 bits
1
MSB LSB
18 bits
4
0001716151
210
13 bits
Fig.7 Transfer of SDA data (Standard I2S default format).
1716151
MSB
right
4
MLA923 - 2
August 1993 8
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
channel
SWS
SCL
SDA
bit :
18 bits
1
3
4
MSB LSB
Fig.8 Transfer of SDA data (alternative format).
left 32 bits
0001716151
210
14 bits
1716151
MSB
SAA2520
right
4
MLA924 - 2
channel
SWS
SCL
FDAC/
FDAF
bit :
left 32 bits
1
2322212
MSB LSB
02010
0
Fig.9 Transfer of FDAF and FDAC (filtered) data.
right
7 bits
0
2322212
MSB
0
MLA925 - 2
August 1993 9
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
channel
SWS
FSYNC
sub-band
LRLLLLLLRRRRRR
31 0 1 31 0 1
Fig.10 SWS related to phase of FSYNC.
SAA2520
MBC148 - 1
Baseband Interface Signals
The interface between the SAA2520 and the baseband input/output circuitry consists of the following signals:
SWS bi-directional word (channel) select FS
SCL bi-directional bit clock 64FS
SDA bi-directional baseband data
FDIR output decoding mode (direction control)
The SWS signal indicates the channel of the sample signal
(either LEFT or RIGHT) and is equal to the sampling
frequency FS.
Operating at a frequency of 64 times that is used for
sampling, the bit clock dictates that each SWS period
contains 64 SDA data bits. Of these, a maximum of 36 are
used to transfer data (samples may have a length up to
18-bits). Samples are transferred most significant bit first.
Both SWS and SDA change state at the negative edge of
SCL.
This baseband data is transferred between the SAA2520
and the input/output using either Standard I2S (default) or
the alternative format shown in Fig.8.
August 1993 10
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
Interface between SAA2520 and SAA2521 consists of the following signals:
ILTERED-I
F
SWS bi-directional word select (common to I2S) FS
SCL bi-directional bit clock (common to I
FDAC bi-directional codec data
FDAF bi-directional filter data
FSYNC output synchronization FS/32
Filtered data is transferred between SAA2520 filter/codec
functions and the SAA2521 using the format shown in
Fig.9.
The frequency of the SWS signal is equal to the sample
frequency FS and the bit clock SCL is 64 times the sample
frequency. Each period of SWS contains 64 data-bits, 48
of which are used to transfer data. The half period in which
SWS is LOW is used to transfer the information of the
LEFT channel while the following half period during which
SWS is HIGH carries the data of the RIGHT channel.
The 24-bit samples are transferred most significant bit first.
This bit is transferred in the bit clock period with a 1-bit
delay following the change in SWS. Both SWS and
FDAF/FDAC change state at the negative edge of SCL.
The SAA2521 may be synchronized to the sub-band
codec using the FSYNC signal, which defines the SWS
period in which the samples of sub-band 0 (containing the
lowest frequency components) are transferred
(see Fig.10).
SAA2521
The operation of SAA2521 and the input/output circuitry is
controlled by three signals shown in Table 1.
2
S INTERFACE
AND INPUT/OUTPUT MODE CONTROL
2
S) 64FS
MPEG C
The interface that carries the MPEG coded signal uses
the following signals:
The MPEG I
SBWS bi-directional word selection
SBCL bi-directional bit clock
SBDA bi-directional sub-band coded data
SBEF input error signal
Operation is further controlled by:
SBDIR input direction of data flow
URDA input unreliable encoded data signal
The SBMCLK signal is the main frequency from which
other clock signals are derived. In encode mode this
division is performed internally. In decode mode the
external source should provide SBWS and SBCL.
The frequency of the signal is equal to 1/32nd of the bit
rate. The frequency of the bit clock SBCL is twice that of
the bit rate. Some examples of the frequencies are given
in Table 2.
ODED INTERFACE
2
S interface
SAA2520
FRESET and SYNCDAI are given whenever:
− FS256, SCL and SWS outputs switch between
high and low impedance
− FS256 frequency is changed
(12.288/11.2896/8.192 MHz)
− FDIR is switching
− bit rate is changing
− system reset is active
August 1993 11
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
SAA2520
audio applications
Table 1 SAA2521 input/output control.
FRESET output request a general reset of SAA2521
FDIR output '1' for decoding and '0' for encoding mode (common to I2S)
SYNCDAI output pulse for synchronization of digital input/output (TDA1315)
Table 2 Frequency examples.
BIT RATE
(k BITS/s)
384 12 768
256 8 512
192 6 384
128 4 256
ENCODE MODE
The following modes are supported:
Stereo or 2-channel mono with allowable bit rates of 384,
256, 192 and 128 kbits/s; audio sampling frequencies of
48, 44.1 and 32 kHz.
SBWS FREQUENCY
(kHz)
SBCL FREQUENCY
(kHz)
D
ECODE MODE
The following modes are supported:
Stereo and joint stereo, 2-channel mono and 1-channel
mono with allowable bit rates in the range 448 to 32 k
bits/s; audio sampling frequencies of 48, 44.1 and 32 kHz.
August 1993 12
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
T
FS256
SCL
SWS, SDA, FDAF, FDAC, FSYNC
output
SDA, FDAF, FDAC
input
t
fH fL
t
t
d1
t
sL
t
h2
t
d2
SAA2520
t
d1
t
T
c
t
t
h1
su
sH
MEA642 - 3
Fig.11 Filtered I2S interface timing (master mode - FS256, SCL and SWS are input).
Notes to Fig.11
T FS256 cycle time (f
FS256 cycle time (fs = 44.1 kHz)
FS256 cycle time (fs = 32 kHz)
T
c
t
fH
SCL cycle time 4T ns nominal
FS256 HIGH time (fs = 48 kHz)
FS256 HIGH time (fs = 44.1 kHz)
FS256 HIGH time (fs = 32 kHz)
t
fL
FS256 LOW time (fs = 48 kHz)
FS256 LOW time (f
FS256 LOW time (fs = 32 kHz)
t
SH
t
SL
t
S
SCL HIGH time ≥ 2T - 20 ns
SCL LOW time ≥ 2T - 20 ns
SDA, FDAF, FDAC input set-up
before FS256 HIGH ≥ 20 ns
t
H1
SDA, FDAF, FDAC input hold
after FS256 HIGH ≥ 30 ns
t
H2
SDA, FDAF, FDAC output hold
after FS256 HIGH ≤ 0 ns
t
D1, 2
FS256 HIGH to SCL, SWS,
SDA, FDAF, FDAC output valid ≤ 50 ns
= 48 kHz)
s
= 44.1 kHz)
s
81.4 ns nominal
88.6 ns nominal
122.1 ns nominal
≥ 35 ns
≥ 38 ns
≥ 35 ns
≥ 35 ns
≥ 38 ns
≥ 75 ns
August 1993 13
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
T
FS256
SCL
SDA, FDAF, FDAC, FSYNC
output
t
t
sH
t
h1
T
t
d
t
fL
c
fH
SAA2520
t
sL
SWS, SDA, FDAF, FDAC
input
Notes to Fig.12
t
fH
t
fL
t
sH
t
sL
t
H1
FS256 HIGH time ≥ 35 ns
FS256 LOW time ≥ 35 ns
SCL HIGH time ≥ T + 35 ns
SCL LOW time ≥ T + 35 ns
SDA, FDAF, FDAC output
hold after SCL HIGH ≥ 2T - 15 ns
t
D
SCL HIGH to SDA, FDAF
FDAC output valid ≤ 3T + 60 ns
t
s
SDA, FDAF, FDAC input
valid after SCL HIGH ≥ 20 ns
t
H2
SDA, FDAF, FDAC input
hold after SCL HIGH ≥ T + 20 ns
t
su
t
h2
Fig.12 Filtered I2S interface timing (slave mode - FS256, SCL and SWS are input).
MEA644 - 3
August 1993 14
Philips Semiconductors Preliminary specification
,
Stereo filter and codec for MPEG layer 1
audio applications
FRESET
SYNCDAI
FDIR
SDA
FDAF
FDAC
t
d0
t
t
d3
d2
t
d4
HIGH Z
t
d6
HIGH Z
SWS
FS256
SCL
t
sH
HIGH Z
SAA2520
t
d1
t
d5
HIGH Z
SDA
Notes to Fig.13
t
t
t
t
t
t
DO
SH
D1
D2
D3
D4
FRESET HIGH to SYNCDAI HIGH ≥ 300 ns
SYNCDAI HIGH time ≥ 1280 ns
SYNCDAI LOW to FRESET LOW ≥ 790 ns
FDIR hold to FRESET HIGH ≤ 20 ns
FRESET HIGH to FDIR valid ≤ 20 ns
SDA change to high impedance
after FRESET HIGH ≥ 0 ns
t
D5
SDA remains high impedance
after FRESET LOW ≥ 0 ns
t
D6
FDAF, FDAC change to high impedance
after FRESET HIGH ≤ 20 ns
t
D7
FDAF, FDAC remain high impedance
t
d7
HIGH Z
t
d8
FDAF
FDAC
HIGH Z
Fig.13 Mode switch timing.
≤ 170 ns
≤ 170 ns
t
d9
SWS
FS256
SCL
MEA646 - 1
August 1993 15
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
Notes to Fig.13
after FRESET HIGH ≥ 460 ns
t
D8
t
D9
FS256, SWS, SCL change
to high impedance before SYNCDAI HIGH ≥ 140 ns
FS256, SWS, SCL remain HIGH
impedance after SYNCDAI HIGH ≥ 140 ns
32 bits
SBWS
SAA2520
SBCL
SBDA
bit :
SBEF
0001020
15 bits1
3
byte 0 byte 1 byte 2
10111
2
13141
LSBMSB
5
1
MSB
16171
8
Fig.14 Transferring MPEG data to and from the SAA2520.
202
1
9
1
MEA649 - 2
2
2
August 1993 16
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
MPEG Coded Interface (Sub-band I2S)
The MPEG coded data is transferred to and from the
SAA2520 using the format shown in Fig.14.
Each period of SBWS contains 64 data bits, 32 of which
are used to convey data. The half-period during which
SBWS is logic 0 is used to transfer the first 16-bits (0 to 15)
of a sub-band slot. The remaining half-period during which
SBWS is logic 1 carries the remaining 16-bits (16 to 31).
Thus one period of SBWS corresponds with one slot of the
sub-band signal.
Bits 0 and 16 are transferred in the bit clock period, one
bit-time after the change in SBWS. Both SBWS and SBDA
change state during the negative edge of SBCL.
In decode mode a byte error flag SBEF is also transferred.
This occurs approximately in the middle of the
corresponding byte (byte 0 = bits 0 to 7,
byte 1 = bits 8 to 15 etc).
SAA2520
Encoding mode
SBCL, SBWS and SBDA are generated by the SAA2520.
However, if the SBDIR signal is logic 1, the output buffers
are not enabled and these signals do not appear on the
pins. This mode is available to permit a change of
operating mode whilst the bus signals are driven from an
external source.
Decoding mode
SBCL, SBWS and SBDA are generated by an external
source.
Table 3 contains a summary of the source signals in the
various modes.
Table 3 Modes and source signals.
source of:
Mode FDIR SBDIR SBWS SBCL SBDA SBEF SBMCLK
Encode 0 0 INT INT INT ---- INT note 1
Encode 0 1 EXT EXT EXT ---- INT note 2
Decode 1 0 INT INT INT EXT INT note 3
Decode 1 1 EXT EXT EXT EXT INT
Notes
1. During encoding the SBEF signal is ‘don’t care’.
2. Incoming data is not decoded. The SAA2520 operates in the encoding mode and the data does not enter the
interface.
3. Operation is undefined. The SAA2520 is in decoding mode whilst the SBWS, SBCL and SBDA output drivers are
enabled.
August 1993 17
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
t
mL
SBMCLK
T
sc
SBCL
SBWS
SBDA
t
cL
t
t
d2
d1
SAA2520
T
s
t
mH
t
cH
MEA645 - 2
Fig.15 Sub-band I2S interface timing (master mode - SBCL, SBWS and SBDA are output).
Notes to Fig.15
T SBMCLK cycle time 120 to 205 ns (163 ns nominal)
t
t
T
t
t
t
t
mH
mL
c
CH
CL
D1
D2
SBMCLK HIGH time ≥ 35 ns
SBMCLK LOW time ≥ 75 ns
SBCL cycle time (384 kB/s)
SBCL cycle time (256 kB/s)
SBCL cycle time (192 kB/s)
SBCL cycle time (128 kB/s)
SBCL HIGH time (384 kB/s)
SBCL HIGH time (256 kB/s)
SBCL HIGH time (192 kB/s)
SBCL HIGH time (128 kB/s)
SBCL LOW time (384 kB/s)
SBCL LOW time (256 k/Bs)
SBCL LOW time (192 kB/s)
SBCL LOW time (128 kB/s)
8T ns nominal
12T ns nominal
16T ns nominal
24T ns nominal
≥ 4T - 20 ns
≥ 6T - 20 ns
≥ 8T - 20 ns
≥ 12T - 20 ns
≥ 4T - 20 ns
≥ 6T - 20 ns
≥ 8T - 20 ns
≥ 12T - 20 ns
SBWS, SBDA hold to SBCL LOW ≤ 20 ns
SBCL LOW to SBWS, SBDA valid ≤ 20 ns
August 1993 18
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
SBWS
SBCL
SBDA
SBEF
SBCL
0 1 2 3 4 5 6 7 8 9 10 11 12
T
t
su1
sc
t
t
cL
SAA2520
t
cH
h1
Notes to Fig.16
T
C
t
CH
t
CL
t
S1
t
H1
t
S2
t
H2
SBWS
SBDA
t
h2
SBEF
t
su2
MEA648 - 2
Fig.16 Sub-band I2S interface timing (slave mode - SBCL, SBWS and SBDA are input).
SBCL cycle time (see note 1) 6.86T to 96T ns (8T ns nominal)
SBCL HIGH time ≥ T + 30 ns
SBCL LOW time ≥ T + 30 ns
SBWS, SBDA input set-up
before SBCL HIGH ≥ T + 30 ns
SBWS, SBDA input hold
after SBCL HIGH ≥30 ns
SBCL HIGH to SBEF valid ≤ T - 30 ns
SBEF hold after SBCL HIGH
≥ 2T- 30 ns
Note 1:
Minimum at bit rate = 448 kB/s
Nominal at bit rate = 384 kB/s
Maximum at bit rate = 32 kB/s
August 1993 19
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
t
d1
HIGH Z
Fig.17 Sub-band I2S mode switch timing.
Notes to Fig.17
t
D1
t
D2
SBDIR HIGH to SBCL, SBWS, SBDA high impedance ≤ 50 ns
SBCL, SBWS, SBDA after SBDIR LOW high impedance ≥ 240 ns
t
d2
HIGH Z
MEA647 - 1
SAA2520
SBDIR
SBCL
SBWS
SBDA
August 1993 20
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
SAA2520
audio applications
Microcontroller interface
The SAA2520 has an interface connection to the serial interface of a microcontroller. The following signals are used:
LTCLK input bit clock
LTDATA bi-directional serial data
LTCNT0 input control line 0
LTCNT1 input control line 1
LTENA input enable
The SAA2520 microcontroller interface is enabled only if
LTENA (pin 34) is logic 1. Information to or from the
SAA2520 is conveyed in serial 8 or 16-bit units, whilst the
type of information is controlled by LTCNT0 (pin 35) and
LTCNT1 (pin 36).
A transfer commences when the microcontroller sets the
control lines to the correct combination for the required
action. LTENA is set to logic 1. The SAA2520 determines
its required action and prepares to transfer data. When the
microcontroller supplies the LTCLK, data is transferred to
or from the SAA2520 in units of 8-bits. 16-bit transfers are
conveyed as two 8-bit units during which LTENA remains
high.
During the transfer of 8-bit units, the least significant bit is
first to be transferred. When 16-bit units are transferred the
most significant byte is sent first.
E
XTENDED SETTINGS (LTCNT1 = 0, LTCNT0 = 0)
Four information bits together with four address bits are
transferred in this mode. The order in which the bits appear
on the interface is:
D0..D1..D2..D3..A0..A1..A2..A3
Table 4 Extended Settings.
BIT
A3
0 0 0 0 CODEC external settings (see Table 5)
0 0 0 1 FILTER settings (see note 1)
0 0 1 0 not used
.. .. .. .. ..
1 1 1 1 not used
Table 5 Extended Settings.
BIT DESIGNATION DEFAULT FUNCTION
D0 MUTEDAC 1 connected to DAC mute input
D1 ATTDAC 0 connected to DAC attenuation input
D2 DEEMDAC 0 emphasis control for DAC circuit
D3 HOLDCLKOK 0 selects CLKOK hold mode
Note
If not used for DAC control, the MUTEDAC, ATTDAC and DEEMDAC can be used as general purpose output expanders.
BIT
A2
BIT
A1
BIT
A0
DESCRIPTION
August 1993 21
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
Bits D0 to D3 are copied directly to the corresponding
output pins/mode flip-flop.
For HOLDCLKOK = logic 1. When CLKOK drops it will
remain LOW until set by an encode/decode mode, sample
frequency, external 256FS or bit rate index change.
Note 1.
When D0 = logic 1 (default) I
= logic 0 the alternative mode is selected. The setting of D0
remains dormant until activated by the occurrence of
FRESET.
A
LLOCATION/SCALE FACTOR INFORMATION (LTCNT1 =
LOGIC 0, LTCNT0 = LOGIC 1)
For encoding, the allocation and scale factor arrays can be
filled using this mode. To completely fill the allocation array
16 complete transfers of 16-bits are required. After the first
transfer of allocation information a check must be made to
determine when the SAA2520 is ready to receive the
remaining information. This will ensure synchronization
with the internal program of the SAA2520. Transfer of the
allocation information is completed by sending the internal
settings.
2
S mode is selected. For D0
SAA2520
This is then followed by the scale factor information.
In the event that only internal settings information is sent,
then a default allocation of logic 0 will be assigned to all
sub-bands. If in addition no internal settings are sent then
the previous settings remain valid.
The allocation information is transferred in 4-bit units.
Each of these units contains the number of bits allocated
to the sub-band, MINUS 1, except in the case of a logic 0
value, which indicates that no bits are allocated to that
sub-band.
Scale factor information is transferred in units of 8-bits,
containing the 6-bit scale factor which is extended to 8-bits
by adding two logic 0’s at the most significant end.
In the case of stereo encoding the channels are indicated
by L (left) and R (right). This changes to I and II in the case
of 2 channel mono encoding.
Table 6 Allocation information format.
msb bits lsb channel sub-band
B15 - B14 - B13 - B12 L or I 0 .. 30 (even)
B11 - B10 - B9 - B8 R or II 0 .. 30 (even)
B7 - B6 - B5 - B4 L or I 1 .. 31 (odd)
B3 - B2 - B1 - B0 R or II 1 .. 31 (odd)
Table 7 Scalefactor information format.
msb bits lsb channel sub-band
B15 ................ B8 L or I 0 .. 31
B7 ................ B0 R or II 0 .. 31
August 1993 22
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
SAA2520
audio applications
INTERNAL SETTINGS (LTCNT1 = LOGIC 1, LTNCT 0 = LOGIC 0)
The operation of the codec is controlled by the bits transferred in this mode.
Table 8 Internal Settings (LTCNT1 = logic 1, LTNCT 0 = logic 0).
msb lsb name function valid in
S15 ... S12 bit rate index bit rate indication encode
S11 ... S10 sample frequency 44.1, 48 or 32 kHz
indication
S9 decode 1 = decode; 0 = encode encode/decode
S8 EXT 256FS 1 = external;
0 = internal 256FS
S7 2-channel mono 1 = 2-CH mono;
0 = stereo
S6 MUTE 1 = mute; 0 = no mute encode/decode
S5 not used
S4 CH1 1 = CH1; 0 = CH2 decode
S3 ... S2 Tr0 to Tr1 transparent bits encode
S1 ... S0 EMPHASIS emphasis indication encode
encode
encode/decode
encode
Table 9 Internal Settings (LTCNT1 = logic 1, LTCNT0 = logic 0).
msb lsb bit rate
1100384 kbits/s default value
1000256 kbits/s
0110192 kbits/s
0100128 kbits/s
The bit rate index indicates the bit rate of the encoded
signal and is only effective in the encode mode.
The decode bit determines the operation mode of the
SAA2520. The default value is logic 1 (decoding mode).
EXT 256FS in the encoding mode determines whether or
not the SAA2520 is master or slave of the Filtered-I2S
interface (default is logic 0, master mode).
2CH MONO is used in the encoding mode to determine
whether the sub-band signal is generated as a stereo or
2-channel mono signal. Default value is logic 0.
MUTE is used in both the encoding and decoding modes
to mute the information to or from the Filtered-I2S interface
(the default value is logic 0).
CH1 is utilized in the decoding mode to select one of the
2-channel mono signals to be decoded (default is
I - channel 1). A value of 0 results in channel 2 being
decoded).
The transparent bits are copied in the sub-band signal,
default is 00.
The information from S15 to S10, S7 and S3 to S0 will be
copied into the sub-band signal.
August 1993 23
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
Table 10 Sample frequency indication.
msb lsb sample frequency
0 0 44.1 kHz default value
0 1 48 kHz
1 0 32 kHz
1 1 not used
Table 11 EMPHASIS indication.
msb lsb emphasis
0 0 no emphasis default value
0 1 50/15 µs
1 0 reserved
1 1 CCITT J.17
Before sending internal settings the microcontroller should
check whether or not the SAA2520 is ready-to-receive.
However, this does not apply for the transfer of internal
settings to end a transfer of allocation information.
SAA2520
S
TATUS (LTCNT = LOGIC 1, LTNCT0 = LOGIC 1)
Table 12 Status information 16-bit units.
msb lsb name function valid in
T15 ... T12 bit rate index bit rate indication encode/decode
T11 ... T10 sample frequency 44.1, 48 or 32 kHz indication encode/decode
T9 ready-to-receive 1 = ready; 0 = not ready encode/decode
T8 not used
T7 T6 MODE sub-band signal mode indication encode/decode
T5 SYNC synchronization indication decode
T4 CLKOK 1 = o.k.; 0 = not o.k. encode/decode
T3 T2 Tr0 to Tr1 transparent bits encode/decode
T1 ... T0 EMPHASIS emphasis indication encode/decode
The bit rate index indicates the bit rate of the sub-band
signal in units of 32 kbits/s. bit rate index 0000 indicates
the ‘free format’ condition. bit rate 1111 is illegal and
should not be found.
The coding of the sample frequency indication is equal
to the one in the internal settings.
August 1993 24
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
Table 13 MODE identification.
msb lsb mode output
0 0 stereo L and R
0 1 joint stereo L and R
1 0 2 channel mono I or II as selected
1 1 1 channel mono mono; no selection
Ready-to-receive indicates whether the SAA2520 is ready
to receive allocation, scale factor or internal setting
transfers. This should be checked in order to synchronize
the transfer of such information.
In 2 channel mono decode mode the selected samples are
transferred to both output channels. The same occurs with
all samples in 1-channel mono decode mode. In both of
these instances the L and R filter output channels are
identical.
In decode mode the SYNC bit is logic 0 when the SAA2520
is unable to decode the sub-band frames. This will occur in
the following situations:
• with the loss of synchronisation
• when in correct allocation information is received for two
or more subsequent frames (SBEF was HIGH).
• when the URDA input pin is HIGH
SAA2520
In these situations the SAA2520 data output will be muted.
The SYNC bit will return to logic 1 as soon as the decoder
is resynchronized to the incoming sub-band data.
CLKOK indicates whether the 256FS clock corresponds to
specified sample frequency. The CLKOK bit is set to logic
1 after a change in sample frequency, operation mode or
EXT256FS setting. It drops to logic 0 as soon as the
256FS clock deviates from the nominal frequency by more
than approximately 0.2%. Return to logic 1 will only occur
automatically when the extended setting
CLKOK-hold-mode is logic 0.
The transparent bits are copied from the MPEG coded
signal.
The EMPHASIS indication is as defined in the internal
settings. It can be used to apply the correct de-emphasis.
Note: the two bytes of the status are 'sampled' at different
moments so the information may not result from the same
sub-band frame.
August 1993 25
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
handbook, full pagewidth
LTENA
LTCNT0/1
LTCLK
LTDATA
01234567
lsb msb
SAA2520
MLB131
handbook, full pagewidth
Fig.18 Transfer of data on SAA2520 microcontroller interface.
LTENA
16 bits allocation / scale factor information 16 bits allocation / scale factor information
LTCLKC
MLB132
Fig.19 The LTENA line must return to logic 0 between information transfers.
August 1993 26
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
handbook, full pagewidth
LTENA
LTCNT0/1
LTCLK
LTDATA
bit :
8
1011121314 0
9
SAA2520
2
4
1
3
6
5
715
MLB133
handbook, full pagewidth
LTENA
LTCNT0/1
LTCLK
LTDATA
OUTPUT
Fig.20 Order of settings and status bits on the SAA2520 microcontroller interface.
LTENA must remain HIGH
t
D6
8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
MLB134
tD6 delay LTCLK HIGH to LTDATA valid output for bit 0 in 16-bit transfers
Fig.21 16-bit transfers.
August 1993 27
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
t
el
handbook, full pagewidth
LTENA
LTCLK
LTCDATA
input
LTCDATA
output
t
D1
hiZ
t
H1
t
D3
t
D2
t
CL
t
LTCNT0
LTCNT1
S2
t
CH
t
t
D6
t
H3
t
S1
t
D5
H2
SAA2520
t
H4
t
D4
hiZ
MLB135
Notes to Fig.22
t
eL
t
CH
t
CL
t
D1
t
D2
t
D3
t
D4
t
H4
t
D5
t
D6
t
S1
t
H1
t
S2
t
H2
t
H3
t
H4
Fig.22 Microcontroller interface timing.
LTENA LOW time ≥ 190 ns
LTCLK HIGH time ≥ 190 ns
LTCLK LOW time ≥ 190 ns
LTENA HIGH to LTCLK HIGH ≥ 190 ns
LTENA HIGH to LTDATA
output low impedance ≥ 0 ns
LTENA HIGH to LTDATA output valid ≤ 380 ns
LTENA LOW to LTDATA high impedance ≤50 ns
LTENA hold after LTCLK HIGH ≥355 ns
LTCLK HIGH to LTENA HIGH ≥ 190 ns
LTCLK HIGH to LTDATA output valid
for bit 0 (see Fig.21)
for first bit in the second 8-bit unit
≤ 355 ns
≤ 520 ns
LTCNT0/1 set-up before LTENA HIGH ≥ 190 ns
LTCNT0/1 hold after LTENA HIGH ≥ 190 ns
LTDATA set-up before LTCLK HIGH ≥ 190 ns
LTDATA input hold after LTCLK HIGH ≥ 30 ns
LTDATA output hold after LTCLK HIGH ≥ 145 ns
LTENA hold after LTCLK HIGH ≥355 ns
August 1993 28
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
SAA2520
audio applications
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DD
V
I
I
SS
I
DD
I
I
I
O
P
tot
T
stg
T
amb
V
es1
V
es2
Notes
1. Input voltage should not exceed 6.5 V unless otherwise specified
2. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor
3. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.
supply voltage −0.5 6.5 V
input voltage note 1 −0.5 VDD + 0.5 V
supply current from V
supply current in V
DD
SS
− 160 mA
− 160 mA
input current −10 10 mA
output current −20 20 mA
total power dissipation − 880 mW
storage temperature range −55 150 °C
operating ambient temperature range - 40 85 °C
electrostatic handling note 2 −1500 1500 V
electrostatic handling note 3 −70 70 V
DC CHARACTERISTICS
= −40 to 85 °C; VDD = 3.8 to 5.5 V unless otherwise specified.
T
amb
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply
V
I
I
DD
DD
DD
supply voltage range 3.8 5.0 5.5 V
operating current VDD = 5 V (note 1) − 82 110 mA
operating current VDD = 3.8 V (note 1) − 58 80 mA
Inputs URDA, SBDIR, SBEF, LTCLK, LTCNT0, LTNCT1, X22IN, X24IN
V
IH
V
IL
−I
I
+I
I
HIGH level input voltage 0.7V
DD
−− V
LOW level input voltage −−0.3V
input current Vi = 0 V;
T
= 25 °C
amb
input current Vi = 5.5 V;
T
= 25 °C
amb
−−10 µA
−−10 µA
DD
V
Inputs PWRDWN, LTENA
V
IH
V
IL
+I
I
HIGH level input voltage 0.7V
DD
−− V
LOW level input voltage −−0.3V
input current Vi = VDD;
T
= 25 °C
amb
40 − 250 µA
DD
V
August 1993 29
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
SAA2520
audio applications
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Input RESET
V
tlh
V
thl
V
hys
+I
I
positive-going threshold −−0.8V
negative-going threshold 0.2V
hystersis (V
input current Vi = VDD;
T
tlh
amb
- V
) − 1.5 − V
thl
40 − 250 µA
= 25 °C
DD
−− V
Outputs MUTEDAC, DEEMDAC, ATTDAC, SYNCDAI, FDIR, FRESET, FSYNC, CLK22
V
OH
V
OL
HIGH level output voltage +Io = 2 mA VDD−0.5 −− V
LOW level output voltage −Io = 2 mA −−0.4 V
Outputs CLK24
V
OH
V
OL
HIGH level output voltage +Io = 8 mA VDD−0.5 −− V
LOW level output voltage −Io = 8 mA −−0.4 V
Inputs/outputs SBDA, SBCL, SBWS, FDAF, FDAC, SCL, SWS, SDA, LTDATA
V
OH
V
OL
HIGH level output voltage +Io = 2 mA VDD−0.5 −− V
LOW level output voltage −Io = 2 mA −−0.4 V
Outputs SBDA, SBCL, SBWS, FDAF, FDAC, SCL, SWS, SDA, LTDATA in 3-state
V
IH
V
IL
I
I
HIGH level input voltage 0.7V
DD
−− V
LOW level input voltage −−0.3V
input current Vi = VDD;
T
= 25 °C
amb
40 − 250 µA
Input/output SBMCLK
V
OH
V
OL
HIGH level output voltage +Io = 8 mA VDD−0.5 −− V
LOW level output voltage −Io = 8 mA −−0.4 V
Output SBMCLK in 3-state
V
IH
V
IL
I
I
HIGH level input voltage 0.7V
DD
−− V
LOW level input voltage −−0.3V
input current Vi = VDD;
T
= 25 °C
amb
40 − 250 µA
Input/output FS256
V
OH
V
OL
HIGH level output voltage +Io = 12 mA VDD−0.5 −− V
LOW level output voltage −Io = 12 mA −−0.4 V
Output FS256 in 3-state
V
IH
V
IL
I
I
HIGH level input voltage 0.7V
DD
−− V
LOW level input voltage −−0.3V
input current Vi = VDD;
T
= 25 °C
amb
40 − 250 µA
Note
1. For load impedances representative of the application.
DD
DD
DD
DD
V
V
V
V
August 1993 30
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
SAA2520
audio applications
AC CHARACTERISTICS
T
= −40 to 85 °C; VDD = 3.8 to 5.5 V unless otherwise specified.
amb
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Inputs
C
I
X24IN and X22IN
f crystal frequency at X22OUT,
f crystal frequency at X24OUT,
gm mutual conductance 100 kHz 1.5 −−mA/V
A
v
C
fb
C
O
Outputs
C
O
Inputs URDA, RESET, LTDATA, LTCLK, LTENA, LTCNT0, LTCNT1
t
SU
t
HD
Outputs LTDATA, MUTEDAC, DEEMDAC, ATTDAC, SYNCDAI, FDIR, FRESET
t
d
Inputs FDAF, FDAC, SDA, SCL, SWS
t
SU
t
HD
Outputs FDAF, FDAC, SDA, SCL, SWS, FSYNC
t
d
Inputs SBDA, SBCL, SBWS, URDA, SBDIR, SBEF
t
SU
t
HD
Outputs SBDA, SBCL, SBWS
t
d
FS256
T FS256 cycle time f
T FS256 cycle time f
T FS256 cycle time f
T
C
input capacitance −− 10 pF
note 1 21 22.5792 24 MHz
CLK22
note 1 23 24.576 26 MHz
CLK24
small signal gain Av = gm.R
3.5 −−V/V
o
feedback capacitance −− 5pF
output capacitance −− 10 pF
output capacitance −− 10 pF
setup time to X24IN 15 −−ns
hold time to X24IN 60 −−ns
propagation delay from X24IN −− 80 ns
setup time to FS256 15 −−ns
hold time to FS256 25 −−ns
propagation delay from FS256 −− 50 ns
setup time to SBMCLK 15 −−ns
hold time to SBMCLK 25 −−ns
propagation delay from SBMCLK −− 50 ns
= 48 kHz − 81.4 − ns
s
= 44.1 kHz − 88.6 − ns
s
= 32 kHz − 122.1 − ns
s
SCL cycle time − 4T − ns
August 1993 31
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
SAA2520
audio applications
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
FS256 master mode (FS256,SCL and SWS are output)
t
fH
t
fH
t
fH
t
fL
t
fL
t
fL
t
sH
t
sL
t
s
t
H1
t
H2
t
D1,2
FS256 HIGH time fs = 48 kHz 35 −−ns
FS256 HIGH time fs = 44.1 kHz 38 −−ns
FS256 HIGH time fs = 32 kHz 75 −−ns
FS256 LOW time fs = 48 kHz 35 −−ns
FS256 LOW time fs = 44.1 kHz 38 −−ns
FS256 LOW time fs = 32 kHz 75 −−ns
SCL HIGH time 2T-20 −−ns
SCL LOW time 2T-20 −−ns
SDA, FDAF, FDAC input setup
20 −−ns
time before FS256 HIGH
SDA, FDAF, FDAC input hold time
30 −−ns
after FS256 HIGH
SDA, FDAF, FDAC output hold
0 −−ns
time after FS256 HIGH
FS256 HIGH-to SCL, SWS, SDA,
−− 50 ns
FDAF, FDAC output valid
FS256 slave mode (FS256, SCL and SWS are input)
t
fH
t
fL
t
sH
t
sL
t
H1
FS256 HIGH time 35 −−ns
FS256 LOW time 35 −−ns
SCL HIGH time T+35 −−ns
SCL LOW time T+35 −−ns
SDA, FDAF, FDAC output hold
2T-15 −−ns
time after SCL HIGH
t
D
SCL HIGH-to SDA, FDAF, FDAC
−− 3T+60 ns
output valid
t
S
SDA, FDAF, FDAC input valid
20 −−ns
after SCL HIGH
t
H2
SDA, FDAF, FDAC input hold time
T+20 −−ns
after SCL HIGH
SBMCLK
T SBMCLK cycle time 120 163 205 ns
t
t
mH
mL
SBMCLK HIGH time 35 −−ns
SBMCLK LOW time 75 −−ns
August 1993 32
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
SAA2520
audio applications
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
SBMCLK master mode (SBCL, SBWS and SBDA are output)
T
C
T
C
T
C
T
C
t
cH
t
cH
t
cH
t
cH
t
cL
t
cL
t
cL
t
cL
t
D1
t
D2
SBMCLK slave mode (SBCL, SBWS and SBDA are input)
T
C
t
cH
t
cL
t
S1
t
H1
t
S2
t
H2
SBCL cycle time 384 kB/s − 8T − ns
SBCL cycle time 256 kB/s − 12T − ns
SBCL cycle time 192 kB/s − 16T − ns
SBCL cycle time 128 kB/s − 24T − ns
SBCL HIGH time 384 kB/s 4T − 20 −−ns
SBCL HIGH time 256 kB/s 6T − 20 −−ns
SBCL HIGH time 192 kB/s 8T − 20 −−ns
SBCL HIGH time 128 kB/s 12T − 20 −−ns
SBCL LOW time 384 kB/s 4T − 20 −−ns
SBCL LOW time 256 kB/s 6T − 20 −−ns
SBCL LOW time 192 kB/s 8T − 20 −−ns
SBCL LOW time 128 kB/s 12T − 20 −−ns
SBWS, SBDA hold to SBCL LOW 20 −−ns
SBWS, SBDA valid after SBCL 0 −− 20 ns
SBCL cycle time note 2 6.86T 8T 96T ns
SBCL HIGH time T + 30 −−ns
SBCL LOW time T + 30 −−ns
SBWS, SBDA setup time before SBCL
T + 30 −−ns
HIGH
SBWS, SBDA hold time after SBCL
30 −−ns
HIGH
delay before SBEF valid after SBCL
−− T− 30 ns
HIGH
SBEF hold time after SBCL
2T − 30 −−ns
HIGH
Notes
1. % deviation from nominal frequency must be the same for X24, X22, and FS256 inputs to within 0.2%
2. Minimum value for bit rate = 448 kB/s
Typical value for bit rate = 384 kB/s
Maximum value for bit rate = 32 kB/s
August 1993 33
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
PACKAGE OUTLINE
QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm
c
y
X
33 23
34
Z
22
E
A
SAA2520
SOT205-1
e
w M
b
p
B
v M
scale
(1)
eH
H
19.2
1
18.2
e
pin 1 index
2.3
2.1
b
0.25
12
11
Z
w M
p
D
H
D
p
0.50
0.35
D
0 5 10 mm
(1) (1)(1)
cE
D
0.25
0.14
14.1
13.9
14.1
13.9
44
1
DIMENSIONS (mm are the original dimensions)
A
UNIT A1A2A3b
max.
2.60
0.25
0.05
mm
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
v M
D
E
A
B
E
19.2
18.2
H
E
LL
2.0
1.2
A
p
A
2
A
1
detail X
Z
D
0.152.35 0.10.3
2.4
1.8
(A )
3
L
p
L
Zywv θ
E
o
2.4
7
o
1.8
0
θ
OUTLINE
VERSION
SOT205-1
IEC JEDEC EIAJ
133E01A
REFERENCES
August 1993 34
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
97-08-01
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“IC Package Databook”
Reflow soldering
Reflow soldering techniques are suitable for all QFP
packages.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our
Reference Handbook”
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
(order code 9398 652 90011).
“Quality
(order code 9397 750 00192).
SAA2520
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
August 1993 35
Philips Semiconductors Preliminary specification
Stereo filter and codec for MPEG layer 1
SAA2520
audio applications
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
August 1993 36
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