Philips psmn2r9-25ylc Datasheet

Page 1
PSMN2R9-25YLC
LFPAK
N-channel 25 V 3.15 mΩ logic level MOSFET in LFPAK using NextPower technology
Rev. 1 — 2 May 2011 Product data sheet

1. Product profile

1.1 General description

Logic level enhancement mode N-channel MOSFET in LFPAK package. This product is designed and qualified for use in a wide ran ge of industrial, communications and domestic equipment.

1.2 Features and benefits

High reliability Power SO8 package,
Low parasitic inductance and
resistance
Optimised for 4.5V Gate drive utilising
NextPower Superjunction technology
Ultra low QG, QGD and QOSS for high
system efficiencies at low and high loads

1.3 Applications

DC-to-DC convertersLithium-ion battery protectionLoad switching
Power OR-ingServer power suppliesSync rectifier

1.4 Quick reference data

Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
V
DS
I
D
P
tot
T
j
drain-source voltage
drain current Tmb=25°C; VGS=10V;
total power dissipation
junction temperature
25 °C ≤ Tj≤ 175 °C - - 25 V
[1]
--100A
see Figure 1 Tmb=25°C; see Figure 2 --92W
-55 - 175 °C
Page 2
NXP Semiconductors
m
Table 1. Quick reference data …continued
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
R
DSon
Dynamic characteristics
Q
GD
Q
G(tot)
[1] Continuous current is limited by package.

2. Pinning information

drain-source on-state resistance
gate-drain charge
total gate charge
PSMN2R9-25YLC
N-channel 25 V 3.15 mΩ logic level MOSFET in LFPAK using
VGS= 4.5 V; ID=25A;
=25°C;
T
j
see Figure 12 V
=10V; ID=25A;
GS
Tj=25°C; see Figure 12
VGS= 4.5 V; ID=25A; V
=12V;
DS
see Figure 14; see Figure 15
- 3.45 4.1 mΩ
- 2.65 3.15 mΩ
-4.4-nC
-16-nC
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1Ssource 2Ssource
mb
3Ssource 4 G gate mb D mounting base;
connected to drain
1234
SOT669 (LFPAK;
Power-SO8)

3. Ordering information

Table 3. Ordering information
Type number Package
PSMN2R9-25YLC LFPAK;
Name Description Version
plastic single-ended surface-mounted package; 4 leads SOT669
Power-SO8

4. Marking

G
bb076
D
S
Table 4. Marking codes
Type number Marking code
[1]
PSMN2R9-25YLC 2C925L
[1] % = placeholder for manufacturing site code.
PSMN2R9-25YLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 2 May 2011 2 of 15
Page 3
NXP Semiconductors

5. Limiting values

PSMN2R9-25YLC
N-channel 25 V 3.15 mΩ logic level MOSFET in LFPAK using
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
T
sld(M)
V
ESD
Source-drain diode
I
S
I
SM
Avalanche ruggedness
E
DS(AL)S
drain-source voltage 25 °C ≤ Tj≤ 175 °C - 25 V drain-gate voltage 25 °C ≤ Tj≤ 175 °C; RGS=20kΩ -25V gate-source voltage -20 20 V drain current VGS=10V; Tmb=25°C; see Figure 1
=10V; Tmb= 100 °C; see Figure 1 -91A
V
GS
peak drain current pulsed; tp≤ 10 µs; Tmb=25°C;
[1]
- 100 A
- 517 A
see Figure 4 total power dissipation Tmb=25°C; see Figure 2 -92W storage temperature -55 175 °C junction temperature -55 175 °C peak soldering temperature - 260 °C electrostatic discharge voltage MM (JEDEC JESD22-A115) 380 - V
source current Tmb=25°C - 83 A peak source current pulsed; tp≤ 10 µs; Tmb= 25 °C - 517 A
non-repetitive drain-source avalanche energy
VGS=10V; T
V
≤ 25 V; unclamped; RGS=50Ω;
sup
=25°C; ID= 100 A;
j(init)
-47mJ
see Figure 3
[1] Continuous current is limited by package.
PSMN2R9-25YLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 2 May 2011 3 of 15
Page 4
NXP Semiconductors
03na19
003aaf 809
PSMN2R9-25YLC
N-channel 25 V 3.15 mΩ logic level MOSFET in LFPAK using
003aaf795
(A)
150
I
D
120
90
(1)
60
30
0
0 50 100 150 200
T
(°C)
mb
Fig 1. Continuous drain current as a function of
mounting base temperature
3
10
I
AL
(A)
2
10
120
P
der
(%)
80
40
0
0 20015050 100
Tmb (°C)
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
(1)
10
(2)
1
-1
10
-3
10
-2
10
-1
10
1 10
t
(ms )
AL
Fig 3. Single pulse avalanche rating; avalanche current as a function of avalanche time
PSMN2R9-25YLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 2 May 2011 4 of 15
Page 5
NXP Semiconductors
PSMN2R9-25YLC
N-channel 25 V 3.15 mΩ logic level MOSFET in LFPAK using
10
I
D
4
003aaf796
(A)
3
10
10
Limit R
2
DSon
= VDS / I
D
tp =10 μs
100 μs
10
DC
1 ms
10 ms
1
-1
10
0.1 1 10 100
100 ms
V
DS
(V)
Fig 4. Safe operating area; continuous and peak drain cur rents as a function of drain-source voltage

6. Thermal characteristics

Table 6. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
R
th(j-mb)
thermal resistance from junction to mounting base
see Figure 5 - 1.46 1.64 K/W
003aaf797
Z
10
th(j-mb )
(K/W)
1
δ
= 0.5
0.2
0.1
-1
10
0.05
P
δ =
t
p
T
0.02
single shot
-2
10
1e-6 10
t
p
T
-5
-4
10
-3
10
-2
10
-1
10
t
1
t
(s)
p
Fig 5. Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN2R9-25YLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 2 May 2011 5 of 15
Page 6
NXP Semiconductors

7. Characteristics

PSMN2R9-25YLC
N-channel 25 V 3.15 mΩ logic level MOSFET in LFPAK using
Table 7. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V
(BR)DSS
V
GS(th)
I
DSS
I
GSS
R
DSon
drain-source breakdown voltage
gate-source threshold voltage
drain leakage current VDS=25V; VGS=0V; Tj=25°C --1µA
gate leakage current VGS=16V; VDS=0V; Tj= 25 °C - - 100 nA
drain-source on-state resistance
ID=250µA; VGS=0V; Tj=25°C 25--V
=250µA; VGS=0V; Tj= -55 °C 22.5 - - V
I
D
ID=1mA; VDS=VGS; Tj=25°C;
1.05 1.54 1.95 V
see Figure 10; see Figure 11
=10mA; VDS=VGS; Tj=150°C 0.5--V
I
D
=1mA; VDS=VGS; Tj=-55°C --2.25V
I
D
=25V; VGS=0V; Tj= 150 °C - - 100 µA
V
DS
=-16V; VDS=0V; Tj= 25 °C - - 100 nA
V
GS
VGS=4.5V; ID=25A; Tj=25°C;
- 3.45 4.1 mΩ
see Figure 12 V
=4.5V; ID=25A; Tj=150°C;
GS
--6.6mΩ
see Figure 12; see Figure 13
=10V; ID=25A; Tj=25°C;
V
GS
- 2.65 3.15 mΩ
see Figure 12 V
=10V; ID=25A; Tj= 150 °C;
GS
--5.05mΩ
see Figure 12; see Figure 13
R
G
gate resistance f =1MHz - 2 4 Ω
Dynamic characteristi cs
Q
Q Q
G(tot)
GS GS(th)
total gate charge ID=25A; VDS=12V; VGS=10V;
see Figure 14
=25A; VDS=12V; VGS=4.5V;
I
D
see Figure 14 I
=0A; VDS=0V; VGS=10V - 29 - nC
D
; see Figure 15
; see Figure 15
gate-source charge ID=25A; VDS=12V; VGS=4.5V; pre-threshold
see Figure 14
; see Figure 15
-33-nC
-16-nC
-5-nC
-3.4-nC
gate-source charge
Q
GS(th-pl)
post-threshold
-1.6-nC
gate-source charge
Q V
C C C
GD
GS(pl)
iss oss rss
gate-drain charge - 4.4 - nC gate-source plateau
voltage input capacitance VDS=12V; VGS= 0 V; f = 1 MHz; output capacitance - 501 - pF reverse transfer
ID=25A; VDS=12V; see Figure 14; see Figure 15
Tj=25°C; see Figure 16
-2.55-V
- 2083 - pF
- 160 - pF
capacitance
t
d(on)
t
r
t
d(off)
t
f
PSMN2R9-25YLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 2 May 2011 6 of 15
turn-on delay time VDS=12V; RL=0.5Ω; VGS=4.5V;
R
=4.7Ω
rise time - 19 - ns
G(ext)
turn-off delay time - 32 - ns fall time - 13 - ns
- 19.5 - ns
Page 7
NXP Semiconductors
003aaf 798
003aaf 799
PSMN2R9-25YLC
N-channel 25 V 3.15 mΩ logic level MOSFET in LFPAK using
Table 7. Characteristics …continued
Symbol Parameter Conditions Min Typ Max Unit
Q
oss
output charge VGS=0V; VDS=12V; f=1MHz;
Source-drain diode
V
SD
t
rr
Q
r
t
a
source-drain voltage IS=25A; VGS=0V; Tj=25°C;
reverse recovery time IS=25A; dIS/dt = -100 A/µs; VGS=0V; recovered charge - 23 - nC reverse recovery rise
time
t
b
reverse recovery fall time
=25°C
T
j
see Figure 17
VDS=12V VGS=0V; IS=25A; dIS/dt = -100 A/µs;
VDS=12V; see Figure 18
- 18.5 - nC
-0.81.1V
-32-ns
-18-ns
-14-ns
100
10
I
D
(A)
80
60
40
20
0
01234
4.5
3.03.5
2.8
2.6
VGS (V) =
2.4
2.2
(V)
V
DS
Fig 6. Output characteristics; drain current as a
function of drain-source voltage; typical values
10
R
DS on
(mΩ)
8
6
4
2
0
0 4 8 12 16
(V)
V
GS
Fig 7. Drain-source on-state resistance as a function
of gate-source voltage; typical values
PSMN2R9-25YLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 2 May 2011 7 of 15
Page 8
NXP Semiconductors
003aaf 804
003aaf 806
003aaf 803
003aaf 802
PSMN2R9-25YLC
N-channel 25 V 3.15 mΩ logic level MOSFET in LFPAK using
160
g
fs
(S )
120
80
40
0
0 20406080100
(A)
I
D
Fig 8. Forward transconductance as a fun ction of
drain current; typical values
-1
10
I
D
(A)
-2
10
Min
-3
10
Typ Ma x
100
I
D
(A)
80
60
40
20
0
01234
Tj = 25 °CTj = 150 °C
(V)
V
GS
Fig 9. Transfer characteristics; drain current as a
function of gate-source voltage; typical value s
3
V
GS(th)
(V)
Ma x ( 1 mA )
2
ID=5mA
1mA
-4
10
Min ( 5 mA )
1
-5
10
-6
10
0123
Fig 10. Sub-threshold drain current as a function of
V
(V)
GS
Fig 11. Gate-source threshold voltage as a function of
gate-source voltage
PSMN2R9-25YLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
0
-60 0 60 120 180 T
(°C)
j
junction temperature
Product data sheet Rev. 1 — 2 May 2011 8 of 15
Page 9
NXP Semiconductors
003aaf 800
003aaf 801
08
003aaf 807
PSMN2R9-25YLC
N-channel 25 V 3.15 mΩ logic level MOSFET in LFPAK using
20
R
DS on
(mΩ)
16
12
8
4
0
0 20406080100
2.6
2.8
VGS (V) =
I
D
3.0
3.5
4.5
10
(A)
Fig 12. Drain-source on-state resistance as a fun ction
of drain current; typical values
V
DS
2
a
1.5
1
0.5
0
-60 0 60 120 180
VGS=10V
4.5V
T
(°C)
j
Fig 13. Normalized drain-source on-state resistance
factor as a function of junction temperature
10
V
GS
(V)
8
I
D
V
GS(pl)
V
V
GS(th)
GS
Q
GS1QGS2
Q
GS
Q
G(tot)
6
4
2
Q
GD
0
003aaa5
0 10203040
12V
VDS = 5V
20V
Q
(nC )
G
Fig 14. Gate charge waveform definitions Fig 15. Gate-source vo ltage as a function of gate
charge; typical values
PSMN2R9-25YLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 2 May 2011 9 of 15
Page 10
NXP Semiconductors
003aaf 805
003aaf 808
003aaf 444
0
4
10
C
(pF)
3
10
2
10
0.1 1 10 100
PSMN2R9-25YLC
N-channel 25 V 3.15 mΩ logic level MOSFET in LFPAK using
100
I
S
(A)
80
C
is s
C
oss
C
rs s
V
(V)
DS
60
40
20
0
0 0.4 0.8 1.2
Tj = 25 °CTj = 150 °C
(V)
V
SD
Fig 16. Input, output and reverse tran sfer capacitances
as a function of drain-source voltage; typical values
I
D
(A)
Fig 18. Reverse reco very timing definition
Fig 17. Sourc e current as a function of source-drain
voltage; typical values
t
rr
t
a
t
b
0.25 I
RM
I
RM
t (s )
PSMN2R9-25YLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 2 May 2011 10 of 15
Page 11
NXP Semiconductors
Plastic single-ended surface-mounted package (LFPAK; Power-SO8); 4 leads
SOT669
N-channel 25 V 3.15 mΩ logic level MOSFET in LFPAK using

8. Package outline

A
E
b
2
A
c
L
1
D
H
mounting
base
2
2
PSMN2R9-25YLC
C
E
1
b
3
b
4
D
1
L
2
DIMENSIONS (mm are the original dimensions)
UNIT
1.20
mm
1.01
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT669 MO-235
A
0.15
0.00
1
234
e
A
A
1
2
1.10
0.95
bcA e
3
0.50
0.25 4.20 1.27 0.25 0.1
0.35
IEC JEDEC JEITA
1/2 e
b
4.41
3.62
b
2
2.2
2.0
w
M
A
0 2.5 5 mm
scale
(1)
D
0.25
0.19
c
0.30
0.24
2
4.10
3.80
b
3
b
4
0.9
0.7
REFERENCES
A
D
c
1
max
X
(A )
wy
2
ISSUE DATE
3
θ
yC
θ
8° 0°
06-03-16 11-03-25
C
A
1
L
1.3
0.8
L
L
1
1.3
0.8
detail X
(1)
(1)
E
5.0
4.8
(1)
E
1
3.3
3.1
H
L
6.2
0.85
5.8
0.40
EUROPEAN
PROJECTION
Fig 19. Package outline SOT669 (LFPAK; Power-SO8)
PSMN2R9-25YLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 2 May 2011 11 of 15
Page 12
NXP Semiconductors

9. Revision history

PSMN2R9-25YLC
N-channel 25 V 3.15 mΩ logic level MOSFET in LFPAK using
Table 8. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PSMN2R9-25YLC v.1 20110502 Product data sheet - -
PSMN2R9-25YLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 2 May 2011 12 of 15
Page 13
NXP Semiconductors
PSMN2R9-25YLC
N-channel 25 V 3.15 mΩ logic level MOSFET in LFPAK using

10. Legal information

10.1 Data sheet status

Document status
Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document cont ains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was p ublished and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
[1] [2]
Product status
[3]
Definition

10.2 Definitions

Preview — The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied u pon to co nt ain det ailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

10.3 Disclaimers

Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semi conductors’ aggregat e and cumulative liabil ity towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including withou t limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied pri or to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonabl y be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.
Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteri stics sections of this document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default , damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third part y customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.
PSMN2R9-25YLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 2 May 2011 13 of 15
Page 14
NXP Semiconductors
PSMN2R9-25YLC
N-channel 25 V 3.15 mΩ logic level MOSFET in LFPAK using
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpret ed or construed as an offer to sell products that is open f or acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It i s neither qua lif ied nor test ed in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equ ipment or applications.
, unless otherwise

11. Contact information

For more information, please visit: http://www.nxp.com
In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and st andards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, da mages or failed produ ct cl aims resulting from custome r design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

10.4 Trademarks

Notice: All referenced brands, prod uct names, service names and trad emarks are the property of their respective owners.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V .
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
For sales office addresses, please send an email to: [email protected]
PSMN2R9-25YLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 2 May 2011 14 of 15
Page 15
NXP Semiconductors
N-channel 25 V 3.15 mΩ logic level MOSFET in LFPAK using

12. Contents

1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 General description . . . . . . . . . . . . . . . . . . . . . .1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3
6 Thermal characteristics . . . . . . . . . . . . . . . . . . .5
7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .6
8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .11
9 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .12
10 Legal information. . . . . . . . . . . . . . . . . . . . . . . .13
10.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 1 3
10.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
10.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .13
10.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .14
11 Contact information. . . . . . . . . . . . . . . . . . . . . .14
PSMN2R9-25YLC
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected]
Document identifier: PSMN2R9-25YLC
Date of release: 2 May 2011
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