Philips PSMN015-100B, PSMN015-100P Datasheet
DISCRETE SEMICONDUCTORS
DATA SH EET
PSMN015-100B; PSMN015-100P
N-channel TrenchMOS
(TM)
transistor
Product specification August 1999
Philips Semiconductors Product specification
N-channel TrenchMOS
(TM)
transistor
PSMN015-100B; PSMN015-100P
FEATURES SYMBOL QUICK REFERENCE DATA
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• Low thermal resistance
g
d
V
= 100 V
DSS
ID = 75 A
DS(ON)
≤ 15 mΩ
R
s
GENERAL DESCRIPTION
SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in
each package at each voltage rating.
Applications:-
• d.c. to d.c. converters
• switched mode power supplies
The PSMN015-100P is supplied in the SOT78 (TO220AB) conventional leaded package.
The PSMN015-100B is supplied in the SOT404 surface mounting package.
PINNING SOT78 (TO220AB) SOT404 (D2PAK)
PIN DESCRIPTION
1 gate
2 drain
1
3 source
tab drain
tab
123
tab
2
13
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
T
, T
j
Drain-source voltage Tj = 25 ˚C to 175˚C - 100 V
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ - 100 V
Gate-source voltage - ± 20 V
Continuous drain current Tmb = 25 ˚C - 75
T
= 100 ˚C - 53 A
mb
Pulsed drain current Tmb = 25 ˚C - 240 A
Total power dissipation Tmb = 25 ˚C - 230 W
Operating junction and - 55 175 ˚C
stg
storage temperature
2
A
1 It is not possible to make connection to pin:2 of the SOT404 package
2 Maximum continuous current limited by package
August 1999 2 Rev 1.100
Philips Semiconductors Product specification
(TM)
transistor
PSMN015-100B; PSMN015-100PN-channel TrenchMOS
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
E
AS
Non-repetitive avalanche Unclamped inductive load, IAS = 74 A; - 481 mJ
energy t
= 100 µs; Tj prior to avalanche = 25˚C;
p
V
≤ 50 V; RGS = 50 Ω; VGS = 10 V; refer
DD
to fig:15
I
AS
Non-repetitive avalanche - 75 A
current
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction - 0.65 K/W
to mounting base
R
th j-a
Thermal resistance junction SOT78 package, in free air 60 - K/W
to ambient SOT404 package, pcb mounted, minimum 50 - K/W
footprint
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
V
GS(TO)
R
DS(ON)
I
GSS
I
DSS
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
d
L
s
Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 100 - - V
voltage T
= -55˚C 89 - - V
j
Gate threshold voltage VDS = VGS; ID = 1 mA 2.0 3.0 4.0 V
T
= 175˚C 1.0 - - V
j
T
= -55˚C - - 6 V
j
Drain-source on-state VGS = 10 V; ID = 25 A - 12 15 mΩ
resistance T
= 175˚C - - 41 mΩ
j
Gate source leakage current VGS = ±10 V; VDS = 0 V - 2 100 nA
Zero gate voltage drain VDS = 100 V; VGS = 0 V; - 0.05 10 µA
current T
Total gate charge ID = 75 A; V
= 80 V; VGS = 10 V - 109 - nC
DD
= 175˚C - - 500 µA
j
Gate-source charge - 20 - nC
Gate-drain (Miller) charge - 50 - nC
Turn-on delay time VDD = 50 V; RD = 1.8 Ω; - 30 - ns
Turn-on rise time VGS = 10 V; RG = 5.6 Ω -80-ns
Turn-off delay time Resistive load - 150 - ns
Turn-off fall time - 95 - ns
Internal drain inductance Measured from tab to centre of die - 3.5 - nH
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH
Internal source inductance Measured from source lead to source - 7.5 - nH
bond pad
C
iss
C
oss
C
rss
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 4720 - pF
Output capacitance - 650 - pF
Feedback capacitance - 380 - pF
August 1999 3 Rev 1.100
Philips Semiconductors Product specification
(TM)
transistor
PSMN015-100B; PSMN015-100PN-channel TrenchMOS
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
S
I
SM
V
SD
t
rr
Q
rr
Continuous source current - - 75 A
(body diode)
Pulsed source current (body - - 240 A
diode)
Diode forward voltage IF = 25 A; VGS = 0 V - 0.8 1.2 V
Reverse recovery time IF = 20 A; -dIF/dt = 100 A/µs; - 90 - ns
Reverse recovery charge VGS = 0 V; VR = 30 V - 0.3 - µC
August 1999 4 Rev 1.100
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