Philips PSMN010-55D Datasheet
Philips Semiconductors Product specification
N-channel logic level TrenchMOS transistor PSMN010-55D
FEATURES SYMBOL QUICK REFERENCE DATA
• ’Trench’ technology V
DSS
= 55 V
• Very low on-state resistance
• Fast switching ID = 75 A
• Logic level compatible
R
DS(ON)
≤ 10.5 mΩ (VGS = 10 V)
R
DS(ON)
≤ 12 mΩ (VGS = 5 V)
GENERAL DESCRIPTION PINNING SOT428 (DPAK)
SiliconMAXproductsusethelatest PIN DESCRIPTION
Philips Trench technology to
achieve the lowest possible 1 gate
on-state resistance in each
package at each voltage rating. 2 drain
1
Applications:- 3 source
• d.c. to d.c. converters
• switched mode power supplies tab drain
The PSMN010-55D is supplied in
the SOT428 (Dpak) surface
mounting package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DSS
Drain-source voltage Tj = 25 ˚C to 175˚C - 55 V
V
DGR
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ -55V
V
GS
Continuous gate-source - ± 15 V
voltage
V
GSM
Peak pulsed gate-source Tj ≤ 150 ˚C - ± 20 V
voltage
I
D
Continuous drain current Tmb = 25 ˚C; VGS = 5 V - 75
2
A
Tmb = 100 ˚C; VGS = 5 V - 57 A
I
DM
Pulsed drain current Tmb = 25 ˚C - 240 A
P
D
Total power dissipation Tmb = 25 ˚C - 125 W
Tj, T
stg
Operating junction and - 55 175 ˚C
storage temperature
d
g
s
1
2
3
tab
1 It is not possible to make connection to pin 2 of the SOT428 package.
2 Continuous current rating limited by package.
October 1999 1 Rev 1.200
Philips Semiconductors Product specification
N-channel logic level TrenchMOS transistor PSMN010-55D
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
E
AS
Non-repetitive avalanche Unclamped inductive load, IAS = 74 A; - 264 mJ
energy tp = 100 µs; Tj prior to avalanche = 25˚C;
VDD ≤ 25 V; RGS = 50 Ω; VGS = 5 V
I
AS
Non-repetitive avalanche - 75 A
current
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction - - 1.2 K/W
to mounting base
R
th j-a
Thermal resistance junction SOT428 package, pcb mounted, minimum - 50 - K/W
to ambient footprint
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V
voltage Tj = -55˚C 42 - - V
V
GS(TO)
Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2 V
Tj = 175˚C 0.5 - - V
Tj = -55˚C - - 2.3 V
R
DS(ON)
Drain-source on-state VGS = 10 V; ID = 25 A - 7.4 10.5 mΩ
resistance VGS = 5 V; ID = 25 A - 8.6 12 mΩ
VGS = 4.5 V; ID = 25 A - 9.1 13 mΩ
VGS = 5 V; ID = 25 A; Tj = 175˚C - - 25 mΩ
I
GSS
Gate source leakage current VGS = ±10 V; VDS = 0 V - 0.02 100 nA
I
DSS
Zero gate voltage drain VDS = 25 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA
Q
g(tot)
Total gate charge ID = 75 A; V
DD
= 44 V; VGS = 5 V - 55 - nC
Q
gs
Gate-source charge - 13 - nC
Q
gd
Gate-drain (Miller) charge - 28 - nC
t
d on
Turn-on delay time VDD = 30 V; RD = 1.2 Ω; - 19 - ns
t
r
Turn-on rise time VGS = 10 V; RG = 10 Ω - 114 - ns
t
d off
Turn-off delay time Resistive load - 250 - ns
t
f
Turn-off fall time - 216 - ns
L
d
Internal drain inductance Measured tab to centre of die - 3.5 - nH
L
s
Internal source inductance Measured from source lead to source - 7.5 - nH
bond pad
C
iss
Input capacitance VGS = 0 V; VDS = 20 V; f = 1 MHz - 3300 - pF
C
oss
Output capacitance - 560 - pF
C
rss
Feedback capacitance - 370 - pF
October 1999 2 Rev 1.200
Philips Semiconductors Product specification
N-channel logic level TrenchMOS transistor PSMN010-55D
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
S
Continuous source current - - 75 A
(body diode)
I
SM
Pulsed source current (body - - 240 A
diode)
V
SD
Diode forward voltage IF = 25 A; VGS = 0 V - 0.95 1.2 V
t
rr
Reverse recovery time IF = 25 A; -dIF/dt = 100 A/µs; - 70 - ns
Q
rr
Reverse recovery charge VGS = 0 V; VR = 25 V - 0.16 - µC
October 1999 3 Rev 1.200
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