Philips PNX3000 Service Manual

INTEGRATED CIRCUITS

DATA SH EET

PNX3000

Analog front end for digital video
processors

Preliminary specification 2003 Dec 08

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

CONTENTS

1 FEATURES
2 GENERAL DESCRIPTION
3 ORDERING INFORMATION
4 QUICK REFERENCE DATA
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION

7.1 Vision IF

7.2 DTV IF

7.3 Sound IF

7.4 CVBS/YC source selector

7.5 RGB/YPbPr source selector

7.6 Video ADCs and anti-alias filters

7.7 Audio source selectors and A to D converters

7.8 Microphone inputs

7.9 Clock generation, timing circuitry and black
level clamping

7.10 Data link transmitters

7.11 I2C-bus transceiver

7.12 Power supply circuit

7.13 East-west interface

8I

8.1 Input control registers

8.2 Output status registers

2

C-BUS SPECIFICATION

PNX3000

9 LIMITING VALUES
10 THERMAL CHARACTERISTICS
11 QUALITY SPECIFICATION

11.1 Latch-up performance
12 CHARACTERISTICS
13 TEST AND APPLICATION INFORMATION

13.1 Power supply decoupling

13.2 Application diagram
14 PACKAGE OUTLINE
15 SOLDERING

15.1 Introduction to soldering surface mount
packages

15.2 Reflow soldering

15.3 Wave soldering

15.4 Manual soldering

15.5 Suitability of surface mount IC packages for
wave and reflow soldering methods

16 DATA SHEET STATUS
17 DEFINITIONS
18 DISCLAIMERS
19 PURCHASE OF PHILIPS I2C COMPONENTS

2003 Dec 08 2

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

1 FEATURES

• Multi-standard vision IF circuit with alignment-free PLL
demodulator without external components

• Internal (switchable)time-constant for the IF AGC circuit

• DTV IF circuit for gain control of digital broadcast

TV signals

• Sound IF amplifier with separate AGC circuit for
quasi-split sound

• IF circuit can also be used for intercarrier sound

• Analog demodulator for AM sound

• Integrated sound trap and group delay correction

• Video ident function detects the presence of a video

signal

• Video source selector with four external CVBS or YC
inputs and two analog CVBS outputs with independent
source selection for each output

• Two linearinputs for 1fHor 2fHRGB signalswith source
selector; the RGB signals are converted to YUV before
A to D conversion; both inputs can also be used as
YPbPr input for DVD or set top box

• Integrated anti-alias filters for video Analog to Digital
Converters (ADCs)

• Four10-bit videoADCsfor theconversion of CVBS,YC,
YUV and down-mixed sound IF signals

• Up to three different A to D converted video channels
are available simultaneously (e.g. CVBS, YC and YUV)

• Audio source selector with five stereo inputs for analog
audio and two microphone inputs

• Two microphone amplifiers with adjustable gain

• Three analog audio outputs for SCART and line out with

independent source selection for each output

PNX3000

• Four 1-bitaudio sigma delta ADCs for the conversion of
audio and microphone signals

• Threeserial datalink transmitters forinterfacing withthe
digitalvideo processor atabitrate of 594 Mbit/sperdata
link

• Voltage to current converter for driving external
east-west power amplifier

• I2C-bus transceiver with selectable slave address and
maskable interrupt output.

2 GENERAL DESCRIPTION

The PNX3000 is an analog front end for digital video
processors. It contains an IF circuit for both analog and
digital broadcast signals, input selectors and ADCs for
analog video and audio signals. The digital output signals
are made available via three serial data links.

The IC has a supply voltage of 5 V. The supply voltage of
the analog audio partcan be 5 V or 8 V, depending onthe
maximum signal amplitudes that are required.

The PNX3000 is available in two versions. The only
difference is the specification of the sound trap filter. The
PNX3000HL/N2 is recommended for intercarrier sound
applications, and has a sound carrier suppression better
than 28 dB. The PNX3000HL/N2/S6 is recommended for
quasi split sound applications, and has a sound carrier
suppression better than 24 dB.

3 ORDERING INFORMATION

PACKAGE SOUND

TYPE NUMBER

PNX3000HL/N2 LQFP128 plastic lowprofile quad flat package;128 leads;
PNX3000HL/N2/S6 ≥ 24

2003 Dec 08 3

NAME DESCRIPTION VERSION

SOT425-1 ≥ 28

body 14 × 20 × 1.4 mm

CARRIER

SUPPRESSION

(dB)

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

4 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

P

I

P

V

CC(1ASW)

, V

CC(2ASW)

ICC(ASW) audio supply current note 1 − 3.5 5.0 mA

Input signals

V

i(VIF)(dif)(rms)

V

i(DTVIF)(dif)(rms)

V

i(SIF)(rms)

V

i(CVBS/Y)(p-p)

V

i(RGB)(b-w)

V

i(Y)(p-p)

V

i(Pb)(p-p)

V

i(Pr)(p-p)

Video ADCs

B

v(−3dB)

f

sample

RES resolution − 10 − bit

Analog output signals

V

o(CVBS)(p-p)

I

o(TUNERAGC)

main supply voltage 4.75 5.0 5.25 V
main supply current − 285 320 mA
audio supply voltage note 1 4.75 8.0 8.4 V

video IF amplifier sensitivity (differential;RMS

− 75 150 µV

value)
video DTV IF amplifier sensitivity (differential;

− 75 150 µV

RMS value)
sound IF amplifier sensitivity (RMS value) −3dB − 45 tbf dBµV
CVBS or Y input voltage (peak-to-peak value) − 1.0 1.76 V
RGB inputs (black-to-white value) note 2 − 0.7 1.0 V
luminance input signal (peak-to-peak value) note 2 − 1.0 1.43 V
Pb input signal (peak-to-peak value) note 2 − 0.7 1.0 V
Pr input signal (peak-to-peak value) note 2 − 0.7 1.0 V

−3 dB signal bandwidth 1fHmode − 9 − MHz
sample frequency 1fHmode − 27 − MHz

analog CVBS output voltage (peak-to-peak

− 2.0 − V

value)
tuner AGC output current range 0 − 1mA

Notes

1. The supply voltage for the analog audio part of the IC can be 5 or 8 V. For a supply voltage of 5 V the maximum
signal amplitudes at in- and outputs are 1 V (RMS). For a supply voltage of 8 V the maximum amplitudes are
2 V (RMS).

2. The RGB inputs canalso beused asYPbPr input. The selection is made viathe I2C-bus. The YPbPr inputsensitivity
is in accordance with the DVD player specification.

2003 Dec 08 4

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

5 BLOCK DIAGRAM

handbook, full pagewidth

SIFAGC

QSS

2

AM sound

CLP_YUV

RGB/YUV

MIC1

SIF

AMP

VIF

AMP

MATRIX

&

SWITCH

MIC

AMPS

MIC2

AUDIO SWITCH

(DIGITAL OUT)

ICLP

MIXER

&
AM SND
DEMOD

Fpc

VIF
PLL

&

DTVIF
MIXER

L1/AMint

R1/AMext

L2/MIC1/PipMono

R2/MIC2/AM R

SIFIN

VIFIN

DTVIFIN

DTVIFAGC

TUNERAGC

DTVIFPLL

VIFPLL

CVBS0
CVBS1

CVBS2

CVBS/Y3
CVBS/Y4

YCOMB
CCOMB

CVBS_DTV

R1/PR1/V1

G1/Y1/Y1

B1/PB1/U1
R2/PR2/V2

G2/Y2/Y2

B2/PB2/U2

MIC1

MIC2

2

2

IF

SWITCH

2

CVBS_IF

C3
C4

2

2

AM

int

1×

CVBSOUTIF

SNDTRAP

&

GROUP

DELAY

CVBS
PRIM.

SWITCH

CLP_PRIM

CVBS

SWITCH

CVBS

SWITCH

CLP_SEC

6.75 MHz

CVBSOUTA

CVBSOUTB

OUT

&

SEC.

A

L

D

A

R

D

A

L

D

A

D

AUDIO SWITCH
(ANALOG OUT)

2NDSIFEXT

(FMRAD)

2nd SIF internal

DTV 1st IF

DTV 2nd IF

CVBS/Y_PRIM

VIDEO
IDENT

2

2

AUDIO
AMPS

C

2ndSIF

AGC
DET

VCA

CVBS_SEC

Yyuv

U

V

primary digital audio

secondary digital audio

ICLP

ICLP

297 MHz

SWITCH

A

A

ICLP

A

D

CLK

A

D

CLK

DATALINK

27 MHz

CLOCK

D

CLK

D

CLK

10

10

PLL

ADC
PLL

CLP_PRIM

PNX3000

10

10 4

54 MHz13.5 MHz

CLP_YUV
CLP_SEC

DATA

LINK 1

297 MHz

DATA

LINK 3

297 MHz

DATA

LINK 2

297 MHz

BAND

DIVIDER

TIMING

CIRCUIT

GAP
REF

2

4

4

PNX3000

DTVOUT

DLINK1

2NDSIFAGC

DLINK3

DLINK2

BGDEC

VDEFLO

VDEFLS

VAUDO

VAUDS
RREF

VD2V5

XREF

13.5 or 27 MHz

HV_PRIM

HV_SEC

VDEFL

VAUD

R1 R2 R3 R4 R5

L1 L2 L3 L4 L5

AM

EXT

DSNDL1 LINEL

DSNDR1

Fig.1 Block diagram.

2003 Dec 08 5

DSNDL2

DSNDR2

LINER

SCART1L

SCART1R

SCART2R

SCART2L

EWVIN EWIOUT

VOLTAGE

TO

CURRENT

REW

I2C-BUS

INTERFACE

ADR SCL SDA

IRQ

MCE430

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

6 PINNING

SYMBOL PIN DESCRIPTION

CVBS2 1 CVBS2 input
VAUDO 2 DC output voltage for supply of audio DACs in digital decoder
VAUDS 3 sense voltage input for audio DACs supply
CVBS/Y3 4 external CVBS/Y3 input
C3 5 external CHROMA3 input
GND(VSW) 6 ground video switch
BGDEC 7 bandgap decoupling
CVBS/Y4 8 external CVBS/Y4 input
C4 9 external CHROMA4 input
FUSE 10 fused lead
GND(FILT) 11 ground filters
CVBS_DTV 12 input for CVBS encoded signal from DTV decoder
RREF 13 reference current input
V

CC(FILT)

YCOMB 15 Y signal input from 3D Comb filter
CCOMB 16 C signal input from 3D Comb filter
AMEXT 17 external AM mono input
TESTPIN3 18 test pin 3; must be left open
CVBSOUTA 19 CVBS or Y+CHROMA output A
VDEFLO 20 DC output voltage for supply of deflection DACs in digital decoder
VDEFLS 21 sense input voltage for deflection DACs supply
CVBSOUTB 22 CVBS or Y+CHROMA output B
FUSE 23 fused lead
TESTPIN2 24 test pin 2; connect to ground
R1/PR1/V1 25 R input 1 of RGB signal Pr input 1 of YPbPr signal or V input 1 of YUV signal
G1/Y1/Y1 26 G input 1 of RGB signal or Y input 1 of YPbPr signal or Y input 1 of YUV signal
B1/PB1/U1 27 B input 1 of RGB signal Pb input 1 of YPbPr signal or U input 1 of YUV signal
V

CC(RGB)

GND(RGB) 29 ground RGB matrix
R2/PR2/V2 30 R input 2 of RGB signal Pr input 2 of YPbPr signal or V input 2 of YUV signal
G2/Y2/Y2 31 G input 2 of RGB signal or Y input 2 of YPbPr signal or Y input 2 of YUV signal
B2/PB2/U2 32 B input 2 of RGB signal Pb input 2 of YPbPr signal or U input 2 of YUV signal
FUSE 33 fused lead
GND(VADC) 34 ground video ADCs
V

CC(VADC)

EWVIN 36 east-west input voltage
EWIOUT 37 east-west output current
REW 38 east-west voltage to current conversion resistor
ADR 39 I2C-bus address selection input
XREF 40 XTAL reference frequency input

14 supply voltage filters (5 V)

28 supply voltage RGB matrix (5 V)

35 supply voltage video ADCs (5 V)

2003 Dec 08 6

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

SYMBOL PIN DESCRIPTION

FUSE 41 fused lead
IRQ 42 interrupt request output
SDA 43 I2C-bus serial data input and output
SCL 44 I2C-bus serial clock input
HV_SEC 45 horizontal and vertical sync input for secondary video channel
HV_PRIM 46 horizontal and vertical sync input for primary video channel
VD2V5 47 decoupling of internal digital supply voltage
GND(DIG) 48 digital ground
V

CC(DIG)

STROBE3N 50 strobe negative data link 3
STROBE3P 51 strobe positive data link 3
DATA3N 52 data negative data link 3
DATA3P 53 data positive data link 3
FUSE 54 fused lead
STROBE2N 55 strobe negative data link 2
STROBE2P 56 strobe positive data link 2
DATA2N 57 data negative data link 2
DATA2P 58 data positive data link 2
GND(I2D) 59 ground data links
STROBE1N 60 strobe negative data link 1
STROBE1P 61 strobe positive data link 1
DATA1N 62 data negative data link 1
DATA1P 63 data positive data link 1
V

CC(I2D)

SCART2R 65 audio output for SCART2 right
SCART2L 66 audio output for SCART2 left
LINER 67 audio line output right
LINEL 68 audio line output left
SCART1R 69 audio output for SCART1 right
SCART1L 70 audio output for SCART1 left
FUSE 71 fused lead
DSNDR2 72 audio signal input from digital decoder right 2
DSNDL2 73 audio signal input from digital decoder left 2
DSNDR1 74 audio signal input from digital decoder right 1
DSNDL1 75 audio signal input from digital decoder left 1
GND(AADC) 76 ground audio ADCs
V

CC(AADC)

FUSE 78 fused lead
R4 79 right input audio 4
L4 80 left input audio 4
R3 81 right input audio 3

49 digital supply voltage (5 V)

64 supply voltage data links (5 V)

77 supply voltage audio ADCs (5 V)

PNX3000

2003 Dec 08 7

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

SYMBOL PIN DESCRIPTION

L3 82 left input audio 3
R2 83 right input audio 2
L2 84 left input audio 2
R1 85 right input audio 1
L1 86 left input audio 1
GND(2ASW) 87 ground 2 audio switch
V

CC(2ASW)

VAADCREF 89 decoupling of reference voltage for audio ADCs
VAADCN 90 0 V reference voltage for audio ADCs (GND)
VAADCP 91 full scale reference voltage for audio ADCs (5 V)
MIC2N 92 microphone input 2, negative
MIC2P 93 microphone input 2, positive
MIC1N 94 microphone input 1, negative
MIC1P 95 microphone input 1, positive
FUSE 96 fused lead
GND(1ASW) 97 ground 1 audio switch
V

CC(1ASW)

SIFINP 99 sound IF input, positive
SIFINN 100 sound IF input, negative
SIFAGC 101 control voltage for sound IFAGC
DTVIFAGC 102 control voltage for DTV IFAGC
DTVIFINP 103 DTV IF input, positive
DTVIFINN 104 DTV IF input, negative
TUNERAGC 105 tuner AGC output
FUSE 106 fused lead
VIFINP 107 vision IF input, positive
VIFINN 108 vision IF input, negative
DTVIFPLL 109 output loop filter DTV IF PLL demodulator
V

CC(IF)

VIFPLL 111 output loop filter VIF PLL demodulator
GND(1IF) 112 ground 1 IF circuit
2NDSIFEXT 113 second sound IF input
2NDSIFAGC 114 second sound IF AGC capacitor
GND(2IF) 115 ground 2 IF circuit
DTVOUTP 116 DTV output, positive
DTVOUTN 117 DTV output, negative
V

CC(SUP)

FUSE 119 fused lead
CVBSOUTIF 120 CVBS output of IF circuit
GND(SUP) 121 ground of supply circuit
V

CC(1VSW)

88 supply voltage 2 audio switch (audio output buffers; 5 or 8 V)

98 supply voltage 1 audio switch (audio input buffers; 5 or 8 V)

110 supply voltage IF circuit (5 V)

118 supply voltage of supply circuit (5 V)

122 supply voltage 1 of video switch (5 V)

PNX3000

2003 Dec 08 8

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

SYMBOL PIN DESCRIPTION

CVBS0 123 CVBS0 input for CVBS from IF part
TESTPIN1 124 test pin 1; connect to ground
V

CC(2VSW)

CVBS1 126 CVBS1 input
R5 127 right input audio 5
L5 128 left input audio 5

125 supply voltage 2 of video switch (5 V)

PNX3000

2003 Dec 08 9

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

handbook, full pagewidth

CVBS2
VAUDO
VAUDS

CVBS/Y3

C3

GND(VSW)

BGDEC

CVBS/Y4

C4

FUSE

GND(FILT)

CVBS_DTV

RREF

V

CC(FILT)

YCOMB
CCOMB

AMEXT

TESTPIN3

CVBSOUTA

VDEFLO

VDEFLS

CVBSOUTB

FUSE

TESTPIN2

R1/PR1/V1

G1/Y1/Y1

B1/PB1/U1
V

CC(RGB)

GND(RGB)
R2/PR2/V2

G2/Y2/Y2

B2/PB2/U2

FUSE

GND(VADC)

V

CC(VADC)

EWVIN

EWIOUT

REW

CC(2VSW)

R5L5CVBS1

V

127

128

126

125

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

CC(1VSW)

TESTPIN1

CVBS0

V

124

123

122

GND(SUP)
121

CC(SUP)

CVBSOUTIF

FUSE

V

120

119

118

PNX3000HL

DTVOUTN

DTVOUTP

GND(2IF)

117

116

115

2NDSIFAGC

2NDSIFEXT

GND(1IF)

114

113

112

CC(IF)

VIFPLL

V

111

110

DTVIFPLL

VIFINN

VIFINP

109

108

107

FUSE

TUNERAGC

106

105

DTVIFINN

DTVIFINP

104

103

102
101
100

PNX3000

DTVIFAGC
SIFAGC
SIFINN
SIFINP

99

V

98

CC(1ASW)

97

GND(1ASW)

96

FUSE

95

MIC1P
MIC1N

94

MIC2P

93

MIC2N

92

VAADCP

91

VAADCN

90

VAADCREF

89

V

88

CC(2ASW)

GND(2ASW)

87

L1

86

R1

85

L2

84

R2

83

L3

82

R3

81

L4

80

R4

79

FUSE

78

V

77

CC(AADC)

GND(AADC)

76

DSNDL1

75

DSNDR1

74

DSNDL2

73

DSNDR2

72

FUSE

71

SCART1L

70

SCART1R

69

LINEL

68

LINER

67

SCART2L

66

SCART2R

65

40394142434445464748495051525354555657585960616263

IRQ

SCL

FUSE

SDA

HV_SEC

HV_PRIM

VD2V5

GND(DIG)

CC(DIG)

V

STROBE3N

STROBE3P

ADR

XREF

Fig.2 Pinning configuration.

2003 Dec 08 10

DATA3P

DATA3N

FUSE

STROBE2N

DATA2P

DATA2N

STROBE2P

GND(I2D)

STROBE1N

DATA1P

DATA1N

STROBE1P

64

CC(I2D)

V

MCE429

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

7 FUNCTIONAL DESCRIPTION

7.1 Vision IF

The IF amplifier contains 3 AC-coupled control stages
which have a total gain control range of more than 66 dB.

The video signal is demodulated by means of an
alignment-free PLL carrier regenerator with an internal
VCO. This VCO is calibrated by means of a digital control
circuit which uses the external crystal frequency as a
reference. The frequency setting for the various standards
(33.4, 33.9, 38, 38.9, 45.75 and58.75 MHz) isrealised via
theI2C-bus.To improve performanceforphase modulated
carrier signals the control speed of the PLL can be
increased by setting bit FFI.

TheAFC outputis generated bythe digital controlcircuit of
the IF PLL demodulator and can be read via the I2C-bus.
For fast search tuning systems the window of the AFC can
be increased with a factor of three with bus bit AFW.

The AGC-detector operates ontop syncor topwhite level.
The demodulation polarityis switchedvia the I2C-bus. The
AGC detector capacitor is integrated. The time-constant
can be chosen via I2C-bus bits AGC1 and AGC0. The
AGC has also an external mode which is activated by bit
AGCM. In this mode the IF gain is determined by an
external voltage on pin DTVIFAGC.

The IC has an integrated sound trap filter. The filter is
constructed as a cascade of three separate traps, to
realizesufficient suppression ofthefirst andsecondsound
carriers. The trap frequencies are selectedvia theI2C-bus.

The IChas an integrated group delay correction filter. The
filtercan be switchedbetween the PAL BGcurve and aflat
group delay response characteristic. This has the
advantage thatin multi-standard receivers the video SAW
filter does not need to be switchable.

PNX3000

that is approximately 4 MHz higher than the incoming
1st IF centre frequency.

In DTV 2nd IF mode the 2nd IF signal is obtained by
down-mixing the incoming DTV IF signal with the IF VCO
signal.The low-passfilteredDTV 2nd IFsignalis available
as a differential signal at the DTV output. This signal may
have a maximum bandwidth of 10 MHz. The VCO
frequency is programmed via the I2C-bus in steps of
250 kHz.

In DTV mode the AGC time constant is determined by a
capacitor on pin DTVIFAGC. There are two AGC modes:
internal and external. Inthe internal AGC mode thegain is
controlled by an internal AGC detector. The external AGC
mode is activated by bit AGCM. In this mode the
appropriate AGC pin is used as input, so that the IF gain
can be controlled by the DTV channel decoder.

The IF PLL has two pins for connection of the PLL loop
filters, one for analog TV and one for DTV. This allows
each loop filter to be optimized for its application.

7.3 Sound IF

The PNX3000 has a separate sound IF input to enable
quasi-split sound applications. The sound IF amplifier is
similar to the vision IF amplifier and has a gain control
range of about 55 dB. The AGC detector measures the
average level of the AM or FM SIF carrier and ensures a
constant signal amplitude for the AM demodulator and
Quasi-Split Sound (QSS) mixer.

The single reference QSSmixer isrealised by a multiplier.
In this multiplier the SIF signal is converted to the
intercarrier frequency by mixing it with the regenerated
picture carrier from the video IF VCO. With this system a
high performance stereo sound processing can be
achieved.

7.2 DTV IF

Apartfrom processing analogTV signals,the IF circuit can
also be used to preprocess digital TV signals before they
aresent to aDTVchannel decoder. Forthis application the
two modes of operation are DTV 1st IF and DTV 2nd IF.
For both operating modes the IF PLL must be set to
synthesizer mode.

In DTV 1st IF mode only the AGC function of the IF circuit
is used, so the DTV channel decoder must be able to
handle the 1st IF frequency. Because the AGC detector
operates on the down-mixed 2nd IF signal, it is still
importantto programa valid frequency for theIF VCO. Itis
recommended to set the frequency of the VCO to a value

2003 Dec 08 11

For applications without a SIF SAW filter the IC can also
be used in intercarrier mode. In this mode the composite
video signalfrom the VIFamplifier is fedto the QSSmixer
and converted to the intercarrier frequency.

AM sound demodulation is realised in the analog domain
by the QSS mixer. The modulated SIF signal is multiplied
in phase with the limited SIF signal. The demodulator
output signal is low-pass filtered for suppression of the
carrier harmonics. The demodulated AM signal can be
digitized by one of the audio ADCs.

The QSS mixer can also be used for down-mixing an
FM radio IF signal to an intercarrier frequency, so that it
can be demodulated by the digital decoder. The IF PLL
must be set to synthesizer mode in this case. The
preferred solution is to supply the FM radio signal via a

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

separate SAW or ceramic filter to the DTV input of the
PNX3000. The reason isthat theselectivity ofa SAW filter
for TV sound is not sufficient for FM radio and, if the SIF
input is used, no tuner AGC information is available.

For high performance FM radio it is recommended that a

10.7 MHz FM radio IF signal is supplied to the external
2nd SIF input. In thiscase the IF signal must befiltered by
an external bandpass filter, that also functions as an
anti-alias filter. Thelow-pass filterbefore the2nd SIF ADC
must be bypassed by setting bus bit SLPM.

The IC includes a separate AGC circuit for the 2nd SIF
signal. This AGC is needed for intercarrier sound
applications and when an external sound IF signal is
supplied to the 2nd SIF input. The AGC amplifier is
preceded by a second order high-pass filter for
suppression of video signal components. The AGC time
constant is determined by an external capacitor.

7.4 CVBS/YC source selector

The video input selector consists of four independent
sourceselectors, thatcanselect betweentheCVBS signal
coming from the IF part and four external CVBS signals.
Two of the external CVBS inputs can also be used as
YC input. One selector is used to select the signal for of
the primary video channel. A second selector selects the
CVBS or YC signal for the secondary channel. The third
and fourth selectors are used to select analog outputs
CVBS A and B, which can be used for SCART or line
output.

The primary channel can be a CVBS or YC signal. If a
YC signal is selected for the secondary channel or for the
external CVBS outputs A or B, the luminance and
chrominance signals are added to obtain a CVBS signal.

The IC has an extraYC input for connection of a3D comb
filter. The combsignal canonly beselected forthe primary
videochannel. Theinput pin CVBS_DTV allowsan analog
CVBS signal derived from a digital broadcast (MPEG)
signal to be recorded with an analog VCR. This signal
cannot be selected for the primary video channel.

The video identification circuit detects the presence of a
video signal on the CVBS_IF input (pin CVBS0). The
identification output isnormally usedto detect transmitters
during search tuning and can be readvia the I2C-bus. The
circuit can also be used to monitor the selected primary
CVBS or YC signal. Either mode is selected by bit VIM.

PNX3000

7.5 RGB/YPbPr source selector

The IC has two RGB inputs. Both inputs can also be used
as YPbPr input for connecting video sources with an
YPbPr outputlike a DVD player. The RGB inputs can also
be used for fast insertion of RGB signals (for instance on
screen display menus) in the primary CVBS signal. The
fast insertion switch is located in the digital video
processor.

The RGB signals are converted to YUV before further
processing. The YUV output signal is digitized by two
ADCs. The U and V components have half the bandwidth
of the Y signal, therefore the U and V signals are
multiplexed and digitized by one ADC.

7.6 Video ADCs and anti-alias filters

The PNX3000 contains four video ADCs for analog and
digitalvideo broadcast signals.Theclock frequencyforthe
ADCs is either 27 or 54 MHz. Two analog signals can be
multiplexed at the input of one ADC. Then the clock
frequencyof the ADCis54 MHz and thesamplefrequency
of each channel is 27 MHz.

The video ADCs are 10-bit folding ADCs. The sample
frequency for standard 1fH video signals is 27 MHz. For
the YUV channel the sample frequency of the U and V
components is half the sample frequency of the Y signal.

For 2fHYPbPr or RGB input signals (for instance 480 p or
1080i ATSC signals), thefrequency thatis usedto sample
the YUV signals is twice as high as for 1fH signals. The
sample frequency is 54 MHz for Y and 27 MHz for
U and V. The high sample frequency requires two data
links to transport the video data to the digital video
processor.

The anti-alias filters before the ADCs limit the signal
bandwidth to prevent aliasing effects. The filters for YUV
can be bypassed by means of two separate bits: bit BPY
for the Y filter and bit BPUV for the U and V filters. This
enables the use of external anti-alias filterswith increased
bandwidth for 2fH, RGB or YPbPr input signals.

Table 1 shows the signal bandwidths and sample rates for
the various types of video signals. Table 2 shows which
video signals are sent to the digital video processor for
both data link modes.

2003 Dec 08 12

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

Table 1 Overview of anti-alias filter bandwidths and video signal sample rates.

SIGNAL TYPE

CVBS 8 9 27
YCY8927

YUV 1f

H

YUV 2f

H

DTV − 10 12 −
2nd SIF − 8927

7.7 Audio source selectors and A to D converters

The PNX3000 contains two different audio source
selectors.The first selectorselectswhichaudio signals are
routed to the audio ADCs for further processing in the
digital domain. The two microphone inputs are also
connected to this selector. The selector has two outputs, a
primary channel and a secondary channel. The primary
audio channel is used for one stereo signal. The
secondary audio channel can carry a second stereo
signal, or two microphone signals, or one mono signal and
one microphone signal or one mono signal and one
AM sound signal.

The second selectorselects whichaudio signalsare fed to
the analog audio outputs for SCART and line out. This
selectoralso hastwo stereo inputsfor demodulatedsound
signals coming from the digital video processor.

The gain from an external audio input to an analog output
is 1. A supply voltage of 5 V allows input and output
amplitudes of 1 V (RMS) full scale. The PNX3000 has
separate supply voltage pins for the audio selector circuit.
To allow for input and output amplitudes of 2 V (RMS) full
scale, as required for compliance with the SCART
specification, an audio supply voltage of 8 V must be used.

The audio ADCs are 1-bit sigma-delta converters that
operate at a clock frequency of 6.75 MHz. The audio
A to Dclock issynchronous with the video A to Dclock, so
that audio and video data can be sent over the same data
links. The effective audio sample rate is

f

clk

52.7=

--------- ­128

ksps.

SIGNAL

COMPONENT

C8927
Y8927
U 4 4.5 13.5
V 4 4.5 13.5
Y 161854
U8927
V8927

SIGNAL BAND

−1.0 dB (MHz)

7.8 Microphone inputs

The IC has two microphone inputs. One microphoneinput
can beused for voice control of the TV set with the help of
an intelligent voice command decoder. The second input
can be used for connection of a microphone for Karaoke.

To allow the use of microphones with different sensitivities
the gain of each microphone amplifier is switchable
between two values via the I2C-bus.

7.9 Clock generation, timing circuitry and black

The IC contains two PLL circuits that derive the sample
clock for theADCs andthe bitand wordclocks for the data
links from an external reference frequency. The reference
frequency must be a stable frequency of either 13.5 MHz
or 27 MHz from a crystal oscillator. The internal reference
frequency isalways 13.5 MHz. Ifthe external frequencyis
27 MHz a prescaler must be activated by bus bit FXT.

One PLL is used to multiply the 13.5 MHz reference
frequencyto the27 and54 MHz clockfrequenciesthat are
needed for the video ADCs. A second PLL is used to
obtain the 297 MHz bit clock for the data link transmitters.

A special timing circuit is used to generate the horizontal
and vertical timing pulses that are needed in the IF part,
and also for clamping the black level of the selected video
signals to a defined value at theoutput of the video ADCs.
The horizontal and vertical timing information of the
primary and secondary video channels must be supplied
by the digital video processor on pins HV_PRIM and
HV_SEC. The signal on these pins must consist of a
horizontal timing pulse that starts just before and ends just

SIGNAL BAND

−3.0 dB (MHz)

level clamping

SAMPLE

FREQUENCY (MHz)

2003 Dec 08 13

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

afterthe horizontalsync pulse ofthe selectedvideo signal.
To enable detection of the vertical blanking period, the
horizontal pulses must be wider during a number of lines
in the vertical blanking interval.

The clamp signal inside the IC is generated with the help
of the external horizontal timing pulse and the 13.5 MHz
clock. The verticaltiming informationis usedto disable the
black level clamp, so that the black level is not disturbed
by the vertical sync pulse on the video signal. The clamp
pulsefor theYUV channel canbe derived fromthe primary
or the secondary HV pulse, and is selected by bus bit
CLPS.

To avoid signal disturbance, it is possible to disable the
black clamps when the horizontal PLL in the digital video
processor is not locked to the selected video signal. This
is done by bus bit CMP forthe primary CVBSchannel and
bus bit CMS for the secondary CVBS channel.

Special attention isrequired whenthe sameCVBS input is
selected for primary and secondary CVBS channels.
Inthis casetheblack levelclamp loop isonly closed forthe
primary CVBS input. Due to internal offsets this will
normally result in a deviation on the black level of the
digitized secondary CVBS output.

7.10 Data link transmitters

Three serial data links are used for transportation of the
digital video and audio data coming from the ADCs in the
PNX3000 to the digital video processor. The use of serial
data connections results ina considerablereduction in pin
count and thenumber ofconnection wiresthat are needed
between both ICs.

Thecommunicationbetween data linktransmitteranddata
link receiver consists of two signals, a data signal and a
strobe signal. The two signals together contain the data,
bit-sync and word-sync information. For optimal EMC
performance both data and strobe are low voltage
differential signals. The voltage swing on each wire is
300 mV.

Each data word sent over a data link consists of 44 bits:
4 video samples of 10 bits each, 2 audio bits and
2 word-sync bits. The word clock is 13.5 MHz. The data
rate on each of the three data links is 594 Mbit/s.

PNX3000

Table 2 shows which video signals are sent to the digital
video processor for both data link modes. In the standard
mode upto three video channels plus one sound IF signal
are digitized and transferred simultaneously over the data
links.

The distancebetween both ICs that are connected via the
data link must not be larger than about 10 centimetres.
The two wires for each differential signal should be paired
in the layout of the printed-circuit board.

2

7.11 I

The slave address of the I2C-bus transceiver in the
PNX3000 has two possible values, selected via the
ADR pin. The maximum bus clock frequency is 400 kHz,
and the voltage swing of SCL and SDA can be 3.3 or 5 V.
The I2C-bus transceiver also has a hardwired IRQ output
(open drain and LOW-active) for interruption of the
microprocessor when the value of an important status bit
in statusbyte 0 changes. The IRQ signal is maskable with
register 0FH.

7.12 Power supply circuit

An internal bandgap circuit generates a stable voltage of

1.25 V. This voltage is multiplied to a reference voltage of

2.3 V, and a digital supply voltage of 2.5 V. These two
voltages must be decoupled by external capacitors.
A1/2VP reference voltage for the audio ADCs also
requires an external decoupling capacitor. The PNX3000
contains two voltage regulators to supply the SDACs that
are used in the digital video processor. Each regulator
requires a few external components (one transistor, two
resistors and a decoupling capacitor). The output voltage
is adjustable between 1.25 and 3.3 V by selection of
external resistors values.

7.13 East-west interface

The PNX3000 contains a voltage to current converter that
serves as the interface between the voltage output of the
digital video processor and the current input of the
east-west stage of the vertical deflection amplifier
(TDA8358). The transconductance is determined by the
value of an external resistor.

C-bus transceiver

2003 Dec 08 14

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

Table 2 Overview of data link modes

MODE APPLICATION

0 standard CVBS/Y
1 YUV 2fH input Y

2

8I

C-BUS SPECIFICATION

The slave addresses of the IC are given in Table 3. The circuit operates at clock frequencies of up to 400 kHz.

Table 3 Slave addresses (9A or 9E)

A6 A5 A4 A3 A2 A1 A0 R/W

1 0 0 1 1 A1 1 1/0

Bit A1 is controlled via the ADR pin, when the pin is connected to ground A1 = 0 and when connected to the positive
supply line A1 = 1. When this pin is left open it is connected to ground via an internal resistor.

DATA LINK 1 DATA LINK 2 DATA LINK 3

VIDEO1 AUDIO1 VIDEO2 AUDIO2 VIDEO3 TEST

yuv

CL1R1Y

prim

L1 R1 U V L2 R2 CVBS

U,V L2 R2 CVBS

yuv

2nd SIF HV_P HV_S

sec

2nd SIF HV_P HV_S

sec

8.1 Input control registers

Table 4 Input control registers; valid subaddresses: 00 to 0F; auto-increment mode available for subaddresses

DATA BYTE POR

VALUE

(HEX)

FUNCTION

SUB

ADDR

D7 D6 D5 D4 D3 D2 D1 D0

Vision IF 0 00 AFN AFW IFS AGCM FFI PMOD AGC1 AGC0 00
Vision IF 1 01 IFON DSIF DFIF DTV IFLH SYNT SSIF QSS 00
IF PLL offset 02 IFGT VAI IFO5 IFO4 IFO3 IFO2 IFO1 IFO0 20
IF tuner take over 03 VA1 VA0 TTO5 TTO4 TTO3 TTO2 TTO1 TTO0 20
IF PLL frequency 04 FXT IFA IFB IFC 0 0 0 0 80
IF synthesizer

05 SF7 SF6 SF5 SF4 SF3 SF2 SF1 SF0 00

frequency
Filters 06 BPUV BPY 0 GD SLPM 0 ST1 ST0 00
Data link mode 07 DRND 0 0 HDTV 0 0 0 DM 00
Video switches 0 08 SEC3 SEC2 SEC1 SEC0 PRI3 PRI2 PRI1 PRI0 00
Video switches 1 09 VIM VSW CMS CMP CVA3 CVA2 CVA1 CVA0 36
Video switches 2 and

0A 0 MA2 MA1 MA0 CVB3 CVB2 CVB1 CVB0 76

audio mute
RGB switches 0B 0 RSEL MAT DVD 0 0 CMR CLPS 00
Audio switches ADC 0C MONO SEA2 SEA1 SEA0 MNM1 PRA2 PRA1 PRA0 00
Audio switches 0 0D DSG A1S2 A1S1 A1S0 MNM0 A0S2 A0S1 A0S0 00
Audio switches 1 0E 0 M2G AMX M1G MICON A2S2 A2S1 A2S0 00
IRQ mask status byte 0 0F 1

(1)

IM6 IM5 IM4 IM3 IM2 IM1 IM0 80

Note

1. The value of this bit cannot be changed.

2003 Dec 08 15

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

Table 5 AFC switch

AFN MODE

0 normal operation
1 AFC not active

Table 6 AFC window

AFW AFC WINDOW

0 normal
1 enlarged

Table 7 IF sensitivity

IFS IF SENSITIVITY

0 normal
1 reduced

Table 8 Internal or external AGC mode

AGCM MODE

0 internal
1 external

Table 9 Fast filter IF PLL

FFI CONDITION

0 normal time constant
1 increased time constant

Table 10 Video modulation standard

PMOD CONDITION

0 negative modulation (FM sound)
1 positive modulation (AM sound)

Table 11 IF AGC speed

AGC1 AGC0 AGC SPEED

0 0 0.7 × norm
0 1 norm
103× norm
116× norm

PNX3000

Table 12 IF amplifier on/off

IFON MODE

0 IF amplifier not active
1 normal operation

Table 13 Selection of signal on analog DTV output

DSIF DFIF MODE

0 0 DTV second IF Y
0 1 DTV first IF N
1 0 2nd SIF internal N
1 1 spare N/A

Table 14 Vision IF input select

DTV MODE

0 VIF input
1 DTVIF input

Table 15 Calibration of IF PLL demodulator

IFLH MODE

0 calibration system active
1 calibration system not active

Table 16 IF PLL mode

SYNT MODE

0 normal mode
1 synthesizer mode

Table 17 Second sound IF input

SSIF MODE

0 internal input
1 external input

Table 18 Sound operation

QSS MODE

0 intercarrier sound
1 quasi split sound

ACTIVE

LPF

2003 Dec 08 16