Philips PNX3000 Service Manual

INTEGRATED CIRCUITS

DATA SH EET

PNX3000

Analog front end for digital video
processors

Preliminary specification 2003 Dec 08

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

CONTENTS

1 FEATURES
2 GENERAL DESCRIPTION
3 ORDERING INFORMATION
4 QUICK REFERENCE DATA
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION

7.1 Vision IF

7.2 DTV IF

7.3 Sound IF

7.4 CVBS/YC source selector

7.5 RGB/YPbPr source selector

7.6 Video ADCs and anti-alias filters

7.7 Audio source selectors and A to D converters

7.8 Microphone inputs

7.9 Clock generation, timing circuitry and black
level clamping

7.10 Data link transmitters

7.11 I2C-bus transceiver

7.12 Power supply circuit

7.13 East-west interface

8I

8.1 Input control registers

8.2 Output status registers

2

C-BUS SPECIFICATION

PNX3000

9 LIMITING VALUES
10 THERMAL CHARACTERISTICS
11 QUALITY SPECIFICATION

11.1 Latch-up performance
12 CHARACTERISTICS
13 TEST AND APPLICATION INFORMATION

13.1 Power supply decoupling

13.2 Application diagram
14 PACKAGE OUTLINE
15 SOLDERING

15.1 Introduction to soldering surface mount
packages

15.2 Reflow soldering

15.3 Wave soldering

15.4 Manual soldering

15.5 Suitability of surface mount IC packages for
wave and reflow soldering methods

16 DATA SHEET STATUS
17 DEFINITIONS
18 DISCLAIMERS
19 PURCHASE OF PHILIPS I2C COMPONENTS

2003 Dec 08 2

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

1 FEATURES

• Multi-standard vision IF circuit with alignment-free PLL
demodulator without external components

• Internal (switchable)time-constant for the IF AGC circuit

• DTV IF circuit for gain control of digital broadcast

TV signals

• Sound IF amplifier with separate AGC circuit for
quasi-split sound

• IF circuit can also be used for intercarrier sound

• Analog demodulator for AM sound

• Integrated sound trap and group delay correction

• Video ident function detects the presence of a video

signal

• Video source selector with four external CVBS or YC
inputs and two analog CVBS outputs with independent
source selection for each output

• Two linearinputs for 1fHor 2fHRGB signalswith source
selector; the RGB signals are converted to YUV before
A to D conversion; both inputs can also be used as
YPbPr input for DVD or set top box

• Integrated anti-alias filters for video Analog to Digital
Converters (ADCs)

• Four10-bit videoADCsfor theconversion of CVBS,YC,
YUV and down-mixed sound IF signals

• Up to three different A to D converted video channels
are available simultaneously (e.g. CVBS, YC and YUV)

• Audio source selector with five stereo inputs for analog
audio and two microphone inputs

• Two microphone amplifiers with adjustable gain

• Three analog audio outputs for SCART and line out with

independent source selection for each output

PNX3000

• Four 1-bitaudio sigma delta ADCs for the conversion of
audio and microphone signals

• Threeserial datalink transmitters forinterfacing withthe
digitalvideo processor atabitrate of 594 Mbit/sperdata
link

• Voltage to current converter for driving external
east-west power amplifier

• I2C-bus transceiver with selectable slave address and
maskable interrupt output.

2 GENERAL DESCRIPTION

The PNX3000 is an analog front end for digital video
processors. It contains an IF circuit for both analog and
digital broadcast signals, input selectors and ADCs for
analog video and audio signals. The digital output signals
are made available via three serial data links.

The IC has a supply voltage of 5 V. The supply voltage of
the analog audio partcan be 5 V or 8 V, depending onthe
maximum signal amplitudes that are required.

The PNX3000 is available in two versions. The only
difference is the specification of the sound trap filter. The
PNX3000HL/N2 is recommended for intercarrier sound
applications, and has a sound carrier suppression better
than 28 dB. The PNX3000HL/N2/S6 is recommended for
quasi split sound applications, and has a sound carrier
suppression better than 24 dB.

3 ORDERING INFORMATION

PACKAGE SOUND

TYPE NUMBER

PNX3000HL/N2 LQFP128 plastic lowprofile quad flat package;128 leads;
PNX3000HL/N2/S6 ≥ 24

2003 Dec 08 3

NAME DESCRIPTION VERSION

SOT425-1 ≥ 28

body 14 × 20 × 1.4 mm

CARRIER

SUPPRESSION

(dB)

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

4 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

P

I

P

V

CC(1ASW)

, V

CC(2ASW)

ICC(ASW) audio supply current note 1 − 3.5 5.0 mA

Input signals

V

i(VIF)(dif)(rms)

V

i(DTVIF)(dif)(rms)

V

i(SIF)(rms)

V

i(CVBS/Y)(p-p)

V

i(RGB)(b-w)

V

i(Y)(p-p)

V

i(Pb)(p-p)

V

i(Pr)(p-p)

Video ADCs

B

v(−3dB)

f

sample

RES resolution − 10 − bit

Analog output signals

V

o(CVBS)(p-p)

I

o(TUNERAGC)

main supply voltage 4.75 5.0 5.25 V
main supply current − 285 320 mA
audio supply voltage note 1 4.75 8.0 8.4 V

video IF amplifier sensitivity (differential;RMS

− 75 150 µV

value)
video DTV IF amplifier sensitivity (differential;

− 75 150 µV

RMS value)
sound IF amplifier sensitivity (RMS value) −3dB − 45 tbf dBµV
CVBS or Y input voltage (peak-to-peak value) − 1.0 1.76 V
RGB inputs (black-to-white value) note 2 − 0.7 1.0 V
luminance input signal (peak-to-peak value) note 2 − 1.0 1.43 V
Pb input signal (peak-to-peak value) note 2 − 0.7 1.0 V
Pr input signal (peak-to-peak value) note 2 − 0.7 1.0 V

−3 dB signal bandwidth 1fHmode − 9 − MHz
sample frequency 1fHmode − 27 − MHz

analog CVBS output voltage (peak-to-peak

− 2.0 − V

value)
tuner AGC output current range 0 − 1mA

Notes

1. The supply voltage for the analog audio part of the IC can be 5 or 8 V. For a supply voltage of 5 V the maximum
signal amplitudes at in- and outputs are 1 V (RMS). For a supply voltage of 8 V the maximum amplitudes are
2 V (RMS).

2. The RGB inputs canalso beused asYPbPr input. The selection is made viathe I2C-bus. The YPbPr inputsensitivity
is in accordance with the DVD player specification.

2003 Dec 08 4

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

5 BLOCK DIAGRAM

handbook, full pagewidth

SIFAGC

QSS

2

AM sound

CLP_YUV

RGB/YUV

MIC1

SIF

AMP

VIF

AMP

MATRIX

&

SWITCH

MIC

AMPS

MIC2

AUDIO SWITCH

(DIGITAL OUT)

ICLP

MIXER

&
AM SND
DEMOD

Fpc

VIF
PLL

&

DTVIF
MIXER

L1/AMint

R1/AMext

L2/MIC1/PipMono

R2/MIC2/AM R

SIFIN

VIFIN

DTVIFIN

DTVIFAGC

TUNERAGC

DTVIFPLL

VIFPLL

CVBS0
CVBS1

CVBS2

CVBS/Y3
CVBS/Y4

YCOMB
CCOMB

CVBS_DTV

R1/PR1/V1

G1/Y1/Y1

B1/PB1/U1
R2/PR2/V2

G2/Y2/Y2

B2/PB2/U2

MIC1

MIC2

2

2

IF

SWITCH

2

CVBS_IF

C3
C4

2

2

AM

int

1×

CVBSOUTIF

SNDTRAP

&

GROUP

DELAY

CVBS
PRIM.

SWITCH

CLP_PRIM

CVBS

SWITCH

CVBS

SWITCH

CLP_SEC

6.75 MHz

CVBSOUTA

CVBSOUTB

OUT

&

SEC.

A

L

D

A

R

D

A

L

D

A

D

AUDIO SWITCH
(ANALOG OUT)

2NDSIFEXT

(FMRAD)

2nd SIF internal

DTV 1st IF

DTV 2nd IF

CVBS/Y_PRIM

VIDEO
IDENT

2

2

AUDIO
AMPS

C

2ndSIF

AGC
DET

VCA

CVBS_SEC

Yyuv

U

V

primary digital audio

secondary digital audio

ICLP

ICLP

297 MHz

SWITCH

A

A

ICLP

A

D

CLK

A

D

CLK

DATALINK

27 MHz

CLOCK

D

CLK

D

CLK

10

10

PLL

ADC
PLL

CLP_PRIM

PNX3000

10

10 4

54 MHz13.5 MHz

CLP_YUV
CLP_SEC

DATA

LINK 1

297 MHz

DATA

LINK 3

297 MHz

DATA

LINK 2

297 MHz

BAND

DIVIDER

TIMING

CIRCUIT

GAP
REF

2

4

4

PNX3000

DTVOUT

DLINK1

2NDSIFAGC

DLINK3

DLINK2

BGDEC

VDEFLO

VDEFLS

VAUDO

VAUDS
RREF

VD2V5

XREF

13.5 or 27 MHz

HV_PRIM

HV_SEC

VDEFL

VAUD

R1 R2 R3 R4 R5

L1 L2 L3 L4 L5

AM

EXT

DSNDL1 LINEL

DSNDR1

Fig.1 Block diagram.

2003 Dec 08 5

DSNDL2

DSNDR2

LINER

SCART1L

SCART1R

SCART2R

SCART2L

EWVIN EWIOUT

VOLTAGE

TO

CURRENT

REW

I2C-BUS

INTERFACE

ADR SCL SDA

IRQ

MCE430

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

6 PINNING

SYMBOL PIN DESCRIPTION

CVBS2 1 CVBS2 input
VAUDO 2 DC output voltage for supply of audio DACs in digital decoder
VAUDS 3 sense voltage input for audio DACs supply
CVBS/Y3 4 external CVBS/Y3 input
C3 5 external CHROMA3 input
GND(VSW) 6 ground video switch
BGDEC 7 bandgap decoupling
CVBS/Y4 8 external CVBS/Y4 input
C4 9 external CHROMA4 input
FUSE 10 fused lead
GND(FILT) 11 ground filters
CVBS_DTV 12 input for CVBS encoded signal from DTV decoder
RREF 13 reference current input
V

CC(FILT)

YCOMB 15 Y signal input from 3D Comb filter
CCOMB 16 C signal input from 3D Comb filter
AMEXT 17 external AM mono input
TESTPIN3 18 test pin 3; must be left open
CVBSOUTA 19 CVBS or Y+CHROMA output A
VDEFLO 20 DC output voltage for supply of deflection DACs in digital decoder
VDEFLS 21 sense input voltage for deflection DACs supply
CVBSOUTB 22 CVBS or Y+CHROMA output B
FUSE 23 fused lead
TESTPIN2 24 test pin 2; connect to ground
R1/PR1/V1 25 R input 1 of RGB signal Pr input 1 of YPbPr signal or V input 1 of YUV signal
G1/Y1/Y1 26 G input 1 of RGB signal or Y input 1 of YPbPr signal or Y input 1 of YUV signal
B1/PB1/U1 27 B input 1 of RGB signal Pb input 1 of YPbPr signal or U input 1 of YUV signal
V

CC(RGB)

GND(RGB) 29 ground RGB matrix
R2/PR2/V2 30 R input 2 of RGB signal Pr input 2 of YPbPr signal or V input 2 of YUV signal
G2/Y2/Y2 31 G input 2 of RGB signal or Y input 2 of YPbPr signal or Y input 2 of YUV signal
B2/PB2/U2 32 B input 2 of RGB signal Pb input 2 of YPbPr signal or U input 2 of YUV signal
FUSE 33 fused lead
GND(VADC) 34 ground video ADCs
V

CC(VADC)

EWVIN 36 east-west input voltage
EWIOUT 37 east-west output current
REW 38 east-west voltage to current conversion resistor
ADR 39 I2C-bus address selection input
XREF 40 XTAL reference frequency input

14 supply voltage filters (5 V)

28 supply voltage RGB matrix (5 V)

35 supply voltage video ADCs (5 V)

2003 Dec 08 6

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

SYMBOL PIN DESCRIPTION

FUSE 41 fused lead
IRQ 42 interrupt request output
SDA 43 I2C-bus serial data input and output
SCL 44 I2C-bus serial clock input
HV_SEC 45 horizontal and vertical sync input for secondary video channel
HV_PRIM 46 horizontal and vertical sync input for primary video channel
VD2V5 47 decoupling of internal digital supply voltage
GND(DIG) 48 digital ground
V

CC(DIG)

STROBE3N 50 strobe negative data link 3
STROBE3P 51 strobe positive data link 3
DATA3N 52 data negative data link 3
DATA3P 53 data positive data link 3
FUSE 54 fused lead
STROBE2N 55 strobe negative data link 2
STROBE2P 56 strobe positive data link 2
DATA2N 57 data negative data link 2
DATA2P 58 data positive data link 2
GND(I2D) 59 ground data links
STROBE1N 60 strobe negative data link 1
STROBE1P 61 strobe positive data link 1
DATA1N 62 data negative data link 1
DATA1P 63 data positive data link 1
V

CC(I2D)

SCART2R 65 audio output for SCART2 right
SCART2L 66 audio output for SCART2 left
LINER 67 audio line output right
LINEL 68 audio line output left
SCART1R 69 audio output for SCART1 right
SCART1L 70 audio output for SCART1 left
FUSE 71 fused lead
DSNDR2 72 audio signal input from digital decoder right 2
DSNDL2 73 audio signal input from digital decoder left 2
DSNDR1 74 audio signal input from digital decoder right 1
DSNDL1 75 audio signal input from digital decoder left 1
GND(AADC) 76 ground audio ADCs
V

CC(AADC)

FUSE 78 fused lead
R4 79 right input audio 4
L4 80 left input audio 4
R3 81 right input audio 3

49 digital supply voltage (5 V)

64 supply voltage data links (5 V)

77 supply voltage audio ADCs (5 V)

PNX3000

2003 Dec 08 7

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

SYMBOL PIN DESCRIPTION

L3 82 left input audio 3
R2 83 right input audio 2
L2 84 left input audio 2
R1 85 right input audio 1
L1 86 left input audio 1
GND(2ASW) 87 ground 2 audio switch
V

CC(2ASW)

VAADCREF 89 decoupling of reference voltage for audio ADCs
VAADCN 90 0 V reference voltage for audio ADCs (GND)
VAADCP 91 full scale reference voltage for audio ADCs (5 V)
MIC2N 92 microphone input 2, negative
MIC2P 93 microphone input 2, positive
MIC1N 94 microphone input 1, negative
MIC1P 95 microphone input 1, positive
FUSE 96 fused lead
GND(1ASW) 97 ground 1 audio switch
V

CC(1ASW)

SIFINP 99 sound IF input, positive
SIFINN 100 sound IF input, negative
SIFAGC 101 control voltage for sound IFAGC
DTVIFAGC 102 control voltage for DTV IFAGC
DTVIFINP 103 DTV IF input, positive
DTVIFINN 104 DTV IF input, negative
TUNERAGC 105 tuner AGC output
FUSE 106 fused lead
VIFINP 107 vision IF input, positive
VIFINN 108 vision IF input, negative
DTVIFPLL 109 output loop filter DTV IF PLL demodulator
V

CC(IF)

VIFPLL 111 output loop filter VIF PLL demodulator
GND(1IF) 112 ground 1 IF circuit
2NDSIFEXT 113 second sound IF input
2NDSIFAGC 114 second sound IF AGC capacitor
GND(2IF) 115 ground 2 IF circuit
DTVOUTP 116 DTV output, positive
DTVOUTN 117 DTV output, negative
V

CC(SUP)

FUSE 119 fused lead
CVBSOUTIF 120 CVBS output of IF circuit
GND(SUP) 121 ground of supply circuit
V

CC(1VSW)

88 supply voltage 2 audio switch (audio output buffers; 5 or 8 V)

98 supply voltage 1 audio switch (audio input buffers; 5 or 8 V)

110 supply voltage IF circuit (5 V)

118 supply voltage of supply circuit (5 V)

122 supply voltage 1 of video switch (5 V)

PNX3000

2003 Dec 08 8

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

SYMBOL PIN DESCRIPTION

CVBS0 123 CVBS0 input for CVBS from IF part
TESTPIN1 124 test pin 1; connect to ground
V

CC(2VSW)

CVBS1 126 CVBS1 input
R5 127 right input audio 5
L5 128 left input audio 5

125 supply voltage 2 of video switch (5 V)

PNX3000

2003 Dec 08 9

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

handbook, full pagewidth

CVBS2
VAUDO
VAUDS

CVBS/Y3

C3

GND(VSW)

BGDEC

CVBS/Y4

C4

FUSE

GND(FILT)

CVBS_DTV

RREF

V

CC(FILT)

YCOMB
CCOMB

AMEXT

TESTPIN3

CVBSOUTA

VDEFLO

VDEFLS

CVBSOUTB

FUSE

TESTPIN2

R1/PR1/V1

G1/Y1/Y1

B1/PB1/U1
V

CC(RGB)

GND(RGB)
R2/PR2/V2

G2/Y2/Y2

B2/PB2/U2

FUSE

GND(VADC)

V

CC(VADC)

EWVIN

EWIOUT

REW

CC(2VSW)

R5L5CVBS1

V

127

128

126

125

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

CC(1VSW)

TESTPIN1

CVBS0

V

124

123

122

GND(SUP)
121

CC(SUP)

CVBSOUTIF

FUSE

V

120

119

118

PNX3000HL

DTVOUTN

DTVOUTP

GND(2IF)

117

116

115

2NDSIFAGC

2NDSIFEXT

GND(1IF)

114

113

112

CC(IF)

VIFPLL

V

111

110

DTVIFPLL

VIFINN

VIFINP

109

108

107

FUSE

TUNERAGC

106

105

DTVIFINN

DTVIFINP

104

103

102
101
100

PNX3000

DTVIFAGC
SIFAGC
SIFINN
SIFINP

99

V

98

CC(1ASW)

97

GND(1ASW)

96

FUSE

95

MIC1P
MIC1N

94

MIC2P

93

MIC2N

92

VAADCP

91

VAADCN

90

VAADCREF

89

V

88

CC(2ASW)

GND(2ASW)

87

L1

86

R1

85

L2

84

R2

83

L3

82

R3

81

L4

80

R4

79

FUSE

78

V

77

CC(AADC)

GND(AADC)

76

DSNDL1

75

DSNDR1

74

DSNDL2

73

DSNDR2

72

FUSE

71

SCART1L

70

SCART1R

69

LINEL

68

LINER

67

SCART2L

66

SCART2R

65

40394142434445464748495051525354555657585960616263

IRQ

SCL

FUSE

SDA

HV_SEC

HV_PRIM

VD2V5

GND(DIG)

CC(DIG)

V

STROBE3N

STROBE3P

ADR

XREF

Fig.2 Pinning configuration.

2003 Dec 08 10

DATA3P

DATA3N

FUSE

STROBE2N

DATA2P

DATA2N

STROBE2P

GND(I2D)

STROBE1N

DATA1P

DATA1N

STROBE1P

64

CC(I2D)

V

MCE429

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

7 FUNCTIONAL DESCRIPTION

7.1 Vision IF

The IF amplifier contains 3 AC-coupled control stages
which have a total gain control range of more than 66 dB.

The video signal is demodulated by means of an
alignment-free PLL carrier regenerator with an internal
VCO. This VCO is calibrated by means of a digital control
circuit which uses the external crystal frequency as a
reference. The frequency setting for the various standards
(33.4, 33.9, 38, 38.9, 45.75 and58.75 MHz) isrealised via
theI2C-bus.To improve performanceforphase modulated
carrier signals the control speed of the PLL can be
increased by setting bit FFI.

TheAFC outputis generated bythe digital controlcircuit of
the IF PLL demodulator and can be read via the I2C-bus.
For fast search tuning systems the window of the AFC can
be increased with a factor of three with bus bit AFW.

The AGC-detector operates ontop syncor topwhite level.
The demodulation polarityis switchedvia the I2C-bus. The
AGC detector capacitor is integrated. The time-constant
can be chosen via I2C-bus bits AGC1 and AGC0. The
AGC has also an external mode which is activated by bit
AGCM. In this mode the IF gain is determined by an
external voltage on pin DTVIFAGC.

The IC has an integrated sound trap filter. The filter is
constructed as a cascade of three separate traps, to
realizesufficient suppression ofthefirst andsecondsound
carriers. The trap frequencies are selectedvia theI2C-bus.

The IChas an integrated group delay correction filter. The
filtercan be switchedbetween the PAL BGcurve and aflat
group delay response characteristic. This has the
advantage thatin multi-standard receivers the video SAW
filter does not need to be switchable.

PNX3000

that is approximately 4 MHz higher than the incoming
1st IF centre frequency.

In DTV 2nd IF mode the 2nd IF signal is obtained by
down-mixing the incoming DTV IF signal with the IF VCO
signal.The low-passfilteredDTV 2nd IFsignalis available
as a differential signal at the DTV output. This signal may
have a maximum bandwidth of 10 MHz. The VCO
frequency is programmed via the I2C-bus in steps of
250 kHz.

In DTV mode the AGC time constant is determined by a
capacitor on pin DTVIFAGC. There are two AGC modes:
internal and external. Inthe internal AGC mode thegain is
controlled by an internal AGC detector. The external AGC
mode is activated by bit AGCM. In this mode the
appropriate AGC pin is used as input, so that the IF gain
can be controlled by the DTV channel decoder.

The IF PLL has two pins for connection of the PLL loop
filters, one for analog TV and one for DTV. This allows
each loop filter to be optimized for its application.

7.3 Sound IF

The PNX3000 has a separate sound IF input to enable
quasi-split sound applications. The sound IF amplifier is
similar to the vision IF amplifier and has a gain control
range of about 55 dB. The AGC detector measures the
average level of the AM or FM SIF carrier and ensures a
constant signal amplitude for the AM demodulator and
Quasi-Split Sound (QSS) mixer.

The single reference QSSmixer isrealised by a multiplier.
In this multiplier the SIF signal is converted to the
intercarrier frequency by mixing it with the regenerated
picture carrier from the video IF VCO. With this system a
high performance stereo sound processing can be
achieved.

7.2 DTV IF

Apartfrom processing analogTV signals,the IF circuit can
also be used to preprocess digital TV signals before they
aresent to aDTVchannel decoder. Forthis application the
two modes of operation are DTV 1st IF and DTV 2nd IF.
For both operating modes the IF PLL must be set to
synthesizer mode.

In DTV 1st IF mode only the AGC function of the IF circuit
is used, so the DTV channel decoder must be able to
handle the 1st IF frequency. Because the AGC detector
operates on the down-mixed 2nd IF signal, it is still
importantto programa valid frequency for theIF VCO. Itis
recommended to set the frequency of the VCO to a value

2003 Dec 08 11

For applications without a SIF SAW filter the IC can also
be used in intercarrier mode. In this mode the composite
video signalfrom the VIFamplifier is fedto the QSSmixer
and converted to the intercarrier frequency.

AM sound demodulation is realised in the analog domain
by the QSS mixer. The modulated SIF signal is multiplied
in phase with the limited SIF signal. The demodulator
output signal is low-pass filtered for suppression of the
carrier harmonics. The demodulated AM signal can be
digitized by one of the audio ADCs.

The QSS mixer can also be used for down-mixing an
FM radio IF signal to an intercarrier frequency, so that it
can be demodulated by the digital decoder. The IF PLL
must be set to synthesizer mode in this case. The
preferred solution is to supply the FM radio signal via a

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

separate SAW or ceramic filter to the DTV input of the
PNX3000. The reason isthat theselectivity ofa SAW filter
for TV sound is not sufficient for FM radio and, if the SIF
input is used, no tuner AGC information is available.

For high performance FM radio it is recommended that a

10.7 MHz FM radio IF signal is supplied to the external
2nd SIF input. In thiscase the IF signal must befiltered by
an external bandpass filter, that also functions as an
anti-alias filter. Thelow-pass filterbefore the2nd SIF ADC
must be bypassed by setting bus bit SLPM.

The IC includes a separate AGC circuit for the 2nd SIF
signal. This AGC is needed for intercarrier sound
applications and when an external sound IF signal is
supplied to the 2nd SIF input. The AGC amplifier is
preceded by a second order high-pass filter for
suppression of video signal components. The AGC time
constant is determined by an external capacitor.

7.4 CVBS/YC source selector

The video input selector consists of four independent
sourceselectors, thatcanselect betweentheCVBS signal
coming from the IF part and four external CVBS signals.
Two of the external CVBS inputs can also be used as
YC input. One selector is used to select the signal for of
the primary video channel. A second selector selects the
CVBS or YC signal for the secondary channel. The third
and fourth selectors are used to select analog outputs
CVBS A and B, which can be used for SCART or line
output.

The primary channel can be a CVBS or YC signal. If a
YC signal is selected for the secondary channel or for the
external CVBS outputs A or B, the luminance and
chrominance signals are added to obtain a CVBS signal.

The IC has an extraYC input for connection of a3D comb
filter. The combsignal canonly beselected forthe primary
videochannel. Theinput pin CVBS_DTV allowsan analog
CVBS signal derived from a digital broadcast (MPEG)
signal to be recorded with an analog VCR. This signal
cannot be selected for the primary video channel.

The video identification circuit detects the presence of a
video signal on the CVBS_IF input (pin CVBS0). The
identification output isnormally usedto detect transmitters
during search tuning and can be readvia the I2C-bus. The
circuit can also be used to monitor the selected primary
CVBS or YC signal. Either mode is selected by bit VIM.

PNX3000

7.5 RGB/YPbPr source selector

The IC has two RGB inputs. Both inputs can also be used
as YPbPr input for connecting video sources with an
YPbPr outputlike a DVD player. The RGB inputs can also
be used for fast insertion of RGB signals (for instance on
screen display menus) in the primary CVBS signal. The
fast insertion switch is located in the digital video
processor.

The RGB signals are converted to YUV before further
processing. The YUV output signal is digitized by two
ADCs. The U and V components have half the bandwidth
of the Y signal, therefore the U and V signals are
multiplexed and digitized by one ADC.

7.6 Video ADCs and anti-alias filters

The PNX3000 contains four video ADCs for analog and
digitalvideo broadcast signals.Theclock frequencyforthe
ADCs is either 27 or 54 MHz. Two analog signals can be
multiplexed at the input of one ADC. Then the clock
frequencyof the ADCis54 MHz and thesamplefrequency
of each channel is 27 MHz.

The video ADCs are 10-bit folding ADCs. The sample
frequency for standard 1fH video signals is 27 MHz. For
the YUV channel the sample frequency of the U and V
components is half the sample frequency of the Y signal.

For 2fHYPbPr or RGB input signals (for instance 480 p or
1080i ATSC signals), thefrequency thatis usedto sample
the YUV signals is twice as high as for 1fH signals. The
sample frequency is 54 MHz for Y and 27 MHz for
U and V. The high sample frequency requires two data
links to transport the video data to the digital video
processor.

The anti-alias filters before the ADCs limit the signal
bandwidth to prevent aliasing effects. The filters for YUV
can be bypassed by means of two separate bits: bit BPY
for the Y filter and bit BPUV for the U and V filters. This
enables the use of external anti-alias filterswith increased
bandwidth for 2fH, RGB or YPbPr input signals.

Table 1 shows the signal bandwidths and sample rates for
the various types of video signals. Table 2 shows which
video signals are sent to the digital video processor for
both data link modes.

2003 Dec 08 12

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

Table 1 Overview of anti-alias filter bandwidths and video signal sample rates.

SIGNAL TYPE

CVBS 8 9 27
YCY8927

YUV 1f

H

YUV 2f

H

DTV − 10 12 −
2nd SIF − 8927

7.7 Audio source selectors and A to D converters

The PNX3000 contains two different audio source
selectors.The first selectorselectswhichaudio signals are
routed to the audio ADCs for further processing in the
digital domain. The two microphone inputs are also
connected to this selector. The selector has two outputs, a
primary channel and a secondary channel. The primary
audio channel is used for one stereo signal. The
secondary audio channel can carry a second stereo
signal, or two microphone signals, or one mono signal and
one microphone signal or one mono signal and one
AM sound signal.

The second selectorselects whichaudio signalsare fed to
the analog audio outputs for SCART and line out. This
selectoralso hastwo stereo inputsfor demodulatedsound
signals coming from the digital video processor.

The gain from an external audio input to an analog output
is 1. A supply voltage of 5 V allows input and output
amplitudes of 1 V (RMS) full scale. The PNX3000 has
separate supply voltage pins for the audio selector circuit.
To allow for input and output amplitudes of 2 V (RMS) full
scale, as required for compliance with the SCART
specification, an audio supply voltage of 8 V must be used.

The audio ADCs are 1-bit sigma-delta converters that
operate at a clock frequency of 6.75 MHz. The audio
A to Dclock issynchronous with the video A to Dclock, so
that audio and video data can be sent over the same data
links. The effective audio sample rate is

f

clk

52.7=

--------- ­128

ksps.

SIGNAL

COMPONENT

C8927
Y8927
U 4 4.5 13.5
V 4 4.5 13.5
Y 161854
U8927
V8927

SIGNAL BAND

−1.0 dB (MHz)

7.8 Microphone inputs

The IC has two microphone inputs. One microphoneinput
can beused for voice control of the TV set with the help of
an intelligent voice command decoder. The second input
can be used for connection of a microphone for Karaoke.

To allow the use of microphones with different sensitivities
the gain of each microphone amplifier is switchable
between two values via the I2C-bus.

7.9 Clock generation, timing circuitry and black

The IC contains two PLL circuits that derive the sample
clock for theADCs andthe bitand wordclocks for the data
links from an external reference frequency. The reference
frequency must be a stable frequency of either 13.5 MHz
or 27 MHz from a crystal oscillator. The internal reference
frequency isalways 13.5 MHz. Ifthe external frequencyis
27 MHz a prescaler must be activated by bus bit FXT.

One PLL is used to multiply the 13.5 MHz reference
frequencyto the27 and54 MHz clockfrequenciesthat are
needed for the video ADCs. A second PLL is used to
obtain the 297 MHz bit clock for the data link transmitters.

A special timing circuit is used to generate the horizontal
and vertical timing pulses that are needed in the IF part,
and also for clamping the black level of the selected video
signals to a defined value at theoutput of the video ADCs.
The horizontal and vertical timing information of the
primary and secondary video channels must be supplied
by the digital video processor on pins HV_PRIM and
HV_SEC. The signal on these pins must consist of a
horizontal timing pulse that starts just before and ends just

SIGNAL BAND

−3.0 dB (MHz)

level clamping

SAMPLE

FREQUENCY (MHz)

2003 Dec 08 13

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

afterthe horizontalsync pulse ofthe selectedvideo signal.
To enable detection of the vertical blanking period, the
horizontal pulses must be wider during a number of lines
in the vertical blanking interval.

The clamp signal inside the IC is generated with the help
of the external horizontal timing pulse and the 13.5 MHz
clock. The verticaltiming informationis usedto disable the
black level clamp, so that the black level is not disturbed
by the vertical sync pulse on the video signal. The clamp
pulsefor theYUV channel canbe derived fromthe primary
or the secondary HV pulse, and is selected by bus bit
CLPS.

To avoid signal disturbance, it is possible to disable the
black clamps when the horizontal PLL in the digital video
processor is not locked to the selected video signal. This
is done by bus bit CMP forthe primary CVBSchannel and
bus bit CMS for the secondary CVBS channel.

Special attention isrequired whenthe sameCVBS input is
selected for primary and secondary CVBS channels.
Inthis casetheblack levelclamp loop isonly closed forthe
primary CVBS input. Due to internal offsets this will
normally result in a deviation on the black level of the
digitized secondary CVBS output.

7.10 Data link transmitters

Three serial data links are used for transportation of the
digital video and audio data coming from the ADCs in the
PNX3000 to the digital video processor. The use of serial
data connections results ina considerablereduction in pin
count and thenumber ofconnection wiresthat are needed
between both ICs.

Thecommunicationbetween data linktransmitteranddata
link receiver consists of two signals, a data signal and a
strobe signal. The two signals together contain the data,
bit-sync and word-sync information. For optimal EMC
performance both data and strobe are low voltage
differential signals. The voltage swing on each wire is
300 mV.

Each data word sent over a data link consists of 44 bits:
4 video samples of 10 bits each, 2 audio bits and
2 word-sync bits. The word clock is 13.5 MHz. The data
rate on each of the three data links is 594 Mbit/s.

PNX3000

Table 2 shows which video signals are sent to the digital
video processor for both data link modes. In the standard
mode upto three video channels plus one sound IF signal
are digitized and transferred simultaneously over the data
links.

The distancebetween both ICs that are connected via the
data link must not be larger than about 10 centimetres.
The two wires for each differential signal should be paired
in the layout of the printed-circuit board.

2

7.11 I

The slave address of the I2C-bus transceiver in the
PNX3000 has two possible values, selected via the
ADR pin. The maximum bus clock frequency is 400 kHz,
and the voltage swing of SCL and SDA can be 3.3 or 5 V.
The I2C-bus transceiver also has a hardwired IRQ output
(open drain and LOW-active) for interruption of the
microprocessor when the value of an important status bit
in statusbyte 0 changes. The IRQ signal is maskable with
register 0FH.

7.12 Power supply circuit

An internal bandgap circuit generates a stable voltage of

1.25 V. This voltage is multiplied to a reference voltage of

2.3 V, and a digital supply voltage of 2.5 V. These two
voltages must be decoupled by external capacitors.
A1/2VP reference voltage for the audio ADCs also
requires an external decoupling capacitor. The PNX3000
contains two voltage regulators to supply the SDACs that
are used in the digital video processor. Each regulator
requires a few external components (one transistor, two
resistors and a decoupling capacitor). The output voltage
is adjustable between 1.25 and 3.3 V by selection of
external resistors values.

7.13 East-west interface

The PNX3000 contains a voltage to current converter that
serves as the interface between the voltage output of the
digital video processor and the current input of the
east-west stage of the vertical deflection amplifier
(TDA8358). The transconductance is determined by the
value of an external resistor.

C-bus transceiver

2003 Dec 08 14

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

Table 2 Overview of data link modes

MODE APPLICATION

0 standard CVBS/Y
1 YUV 2fH input Y

2

8I

C-BUS SPECIFICATION

The slave addresses of the IC are given in Table 3. The circuit operates at clock frequencies of up to 400 kHz.

Table 3 Slave addresses (9A or 9E)

A6 A5 A4 A3 A2 A1 A0 R/W

1 0 0 1 1 A1 1 1/0

Bit A1 is controlled via the ADR pin, when the pin is connected to ground A1 = 0 and when connected to the positive
supply line A1 = 1. When this pin is left open it is connected to ground via an internal resistor.

DATA LINK 1 DATA LINK 2 DATA LINK 3

VIDEO1 AUDIO1 VIDEO2 AUDIO2 VIDEO3 TEST

yuv

CL1R1Y

prim

L1 R1 U V L2 R2 CVBS

U,V L2 R2 CVBS

yuv

2nd SIF HV_P HV_S

sec

2nd SIF HV_P HV_S

sec

8.1 Input control registers

Table 4 Input control registers; valid subaddresses: 00 to 0F; auto-increment mode available for subaddresses

DATA BYTE POR

VALUE

(HEX)

FUNCTION

SUB

ADDR

D7 D6 D5 D4 D3 D2 D1 D0

Vision IF 0 00 AFN AFW IFS AGCM FFI PMOD AGC1 AGC0 00
Vision IF 1 01 IFON DSIF DFIF DTV IFLH SYNT SSIF QSS 00
IF PLL offset 02 IFGT VAI IFO5 IFO4 IFO3 IFO2 IFO1 IFO0 20
IF tuner take over 03 VA1 VA0 TTO5 TTO4 TTO3 TTO2 TTO1 TTO0 20
IF PLL frequency 04 FXT IFA IFB IFC 0 0 0 0 80
IF synthesizer

05 SF7 SF6 SF5 SF4 SF3 SF2 SF1 SF0 00

frequency
Filters 06 BPUV BPY 0 GD SLPM 0 ST1 ST0 00
Data link mode 07 DRND 0 0 HDTV 0 0 0 DM 00
Video switches 0 08 SEC3 SEC2 SEC1 SEC0 PRI3 PRI2 PRI1 PRI0 00
Video switches 1 09 VIM VSW CMS CMP CVA3 CVA2 CVA1 CVA0 36
Video switches 2 and

0A 0 MA2 MA1 MA0 CVB3 CVB2 CVB1 CVB0 76

audio mute
RGB switches 0B 0 RSEL MAT DVD 0 0 CMR CLPS 00
Audio switches ADC 0C MONO SEA2 SEA1 SEA0 MNM1 PRA2 PRA1 PRA0 00
Audio switches 0 0D DSG A1S2 A1S1 A1S0 MNM0 A0S2 A0S1 A0S0 00
Audio switches 1 0E 0 M2G AMX M1G MICON A2S2 A2S1 A2S0 00
IRQ mask status byte 0 0F 1

(1)

IM6 IM5 IM4 IM3 IM2 IM1 IM0 80

Note

1. The value of this bit cannot be changed.

2003 Dec 08 15

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

Table 5 AFC switch

AFN MODE

0 normal operation
1 AFC not active

Table 6 AFC window

AFW AFC WINDOW

0 normal
1 enlarged

Table 7 IF sensitivity

IFS IF SENSITIVITY

0 normal
1 reduced

Table 8 Internal or external AGC mode

AGCM MODE

0 internal
1 external

Table 9 Fast filter IF PLL

FFI CONDITION

0 normal time constant
1 increased time constant

Table 10 Video modulation standard

PMOD CONDITION

0 negative modulation (FM sound)
1 positive modulation (AM sound)

Table 11 IF AGC speed

AGC1 AGC0 AGC SPEED

0 0 0.7 × norm
0 1 norm
103× norm
116× norm

PNX3000

Table 12 IF amplifier on/off

IFON MODE

0 IF amplifier not active
1 normal operation

Table 13 Selection of signal on analog DTV output

DSIF DFIF MODE

0 0 DTV second IF Y
0 1 DTV first IF N
1 0 2nd SIF internal N
1 1 spare N/A

Table 14 Vision IF input select

DTV MODE

0 VIF input
1 DTVIF input

Table 15 Calibration of IF PLL demodulator

IFLH MODE

0 calibration system active
1 calibration system not active

Table 16 IF PLL mode

SYNT MODE

0 normal mode
1 synthesizer mode

Table 17 Second sound IF input

SSIF MODE

0 internal input
1 external input

Table 18 Sound operation

QSS MODE

0 intercarrier sound
1 quasi split sound

ACTIVE

LPF

2003 Dec 08 16

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

Table 19 IF AGC operation mode

IFGT MODE

0 non gated operation
1 gated operation; note 1

Note

1. Gated operation improves weak signal performance.
Gated operation is automatically disabled if CVBS_IF
is not selected as primary or secondary video signal.
In this situation bit IFLH should be set to 1 to avoid
recalibration of the IF VCO for white video patterns.

Table 20 CVBS IF output signal amplitude correction for

system I

VAI

PMOD = 0 PMOD = 1

0 no correction no correction
1 amplitude +8% amplitude − 8%

Table 21 IF PLL offset adjustment

IFO5 TO IFO0

(HEX)

00 tbf
20 no correction
3F tbf

Table 22 CVBS IF output signal amplitude

OUTPUT SIGNAL AMPLITUDE

VA1 VA0

0 0 no correction no correction
0 1 spare spare
1 0 amplitude −5% amplitude +5%
1 1 amplitude +5% amplitude −5%

Table 23 IF AGC tuner take over

MODE

CONTROL

PMOD = 0 PMOD = 1

PNX3000

Table 24 External reference frequency

FXT CONDITION

0 13.5 MHz
1 27 MHz

Table 25 PLL demodulator frequency setting

IFA IFB IFC IF FREQUENCY

0 0 0 58.75 MHz
0 0 1 45.75 MHz
0 1 0 38.90 MHz
0 1 1 38.00 MHz
1 0 0 33.40 MHz
1 1 0 33.90 MHz

Table 26 IF VCO synthesizer frequency (SF7 to SF0);

note 1

SF7 TO SF0

(DECIMAL
NUMBER)

95 f = 24 MHz

255 f = 64 MHz

Note

1. f

Table 27 Bypass UV anti-alias filters

BPUV MODE

Table 28 Bypass Y

=(N+1)× 250 kHz; where 95 ≤ N ≤ 255.

synth

0 normal operation
1 UV anti-alias filters bypass

anti-alias filter

yuv

BPY MODE

0 normal operation
1Y

anti-alias filter bypass

yuv

FREQUENCY

TTO5 TO TTO0

(HEX)

3F tuner take over at IF input signal of

0.4 mV

00 tuner take over at IF input signal of

80 mV

2003 Dec 08 17

CONTROL

Table 29 Group delay correction

GD MODE

0 group delay correction bypass
1 group delay correction active

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

Table 30 2nd SIF LPF mode

SLPM MODE

0 2nd SIF LPF active
1 2nd SIF LPF bypass (for FM radio 10.7 MHz)

Table 31 Sound trap frequency

ST1 ST0 FREQUENCY

0 0 5.5 MHz
0 1 4.5 MHz
1 0 6.0 MHz
1 1 6.5 MHz

Table 32 Data link transmitter test mode

DRND MODE

0 normal operation
1 pseudo random test mode; note 1

Note

1. The pseudo random mode can be used for in-circuit
testing of the data link connections between data link
transmitter in the analog front end IC and data link
receiver in the digital video processor IC.

PNX3000

SEC3 SEC2 SEC1 SEC0

1011Y+C3
0100CVBS4
1100Y+C4
0101CVBS_DTV

other CVBS_IF

Table 36 Selection of primary video channel

PRI3 PRI2 PRI1 PRI0

0000CVBS_IF
0001CVBS1
0010CVBS2
0011CVBS3
1011Y+C3
0100CVBS4
1100Y+C4
1110YC_COMB

other CVBS_IF

Table 37 Video ident mode

SELECTED

SELECTED

SIGNAL

SIGNAL

Table 33 YUV 2fH clamp pulse timing

HDTV MODE

0 normal timing (480p signal)
1 HDTV timing (1080i signal)

Table 34 Data link modes; note 1

DM APPLICATION MODE

0 Normal 0
1 YUV 2f

Note

1. See Table 2 in chapter “Functional description”.

Table 35 Selection of secondary video signal

SEC3 SEC2 SEC1 SEC0

0000CVBS_IF
0001CVBS1
0010CVBS2
0011CVBS3

H

SELECTED

1

SIGNAL

VIM MODE

0 ident coupled to CVBS_IF
1 ident coupled to selected primary CVBS signal

Table 38 IF video mute

VSW MODE

0 normal operation
1 CVBSOUTIF muted

Table 39 Clamp mode secondary CVBS channel

CMS MODE

0 top sync clamping mode
1 black level clamping mode

Table 40 Clamp mode primary CVBS channel

CMP MODE

0 top sync clamping mode
1 black level clamping mode

2003 Dec 08 18

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

Table 41 Selection of CVBS output A

CVA3 CVA2 CVA1 CVA0

0000CVBS_IF
0001CVBS1
0010CVBS2
0011CVBS3
1011Y+C3
0100CVBS4
1100Y+C4
0101CVBS_DTV

other output muted

Table 42 Mute SCART2 audio output

MA2 MODE

0 normal operation
1 SCART2 audio output muted

Table 43 Mute SCART1 audio output

MA1 MODE

0 normal operation
1 SCART1 audio output muted

Table 44 Mute LINE audio output

MA0 MODE

0 normal operation
1 LINE audio output muted

SELECTED

SIGNAL

PNX3000

Table 46 Selection of RGB/YUV input

RSEL SELECTED SIGNAL

0 RGB1 input
1 RGB2 input

Table 47 RGB/YUV input mode

MAT DVD MODE

0 0 YUV input; note 1
0 1 YPbPr input; note 2
1 0 RGB input; note 3
1 1 spare

Notes

1. YUV input is an Y, −(B−Y) and −(R−Y) input with the
specification:

a) Y = 1.43 V (p-p); U = 1.33 V (p-p);

V = 1.05 V (p-p).

b) These signal amplitudes are based on a colour bar

signal with 75% saturation.

2. YPbPr input with the specification:
a) Y = 1.0 V (p-p); Pb = 0.7 V (p-p); Pr = 0.7 V (p-p).
b) These signal amplitudes are based on a colour bar

signal with 100% saturation.

3. RGB input with the specification:
a) R = 0.7 × V
b) These signal amplitudes are based on a colour bar

signal with 100% saturation.

Table 48 Clamp mode for RGB and YUV signals

; G = 0.7 × V

B-W

; B = 0.7 × V

B-W

B-W

.

Table 45 Selection of CVBS output B

CVB3 CVB2 CVB1 CVB0

0000CVBS_IF
0001CVBS1
0010CVBS2
0011CVBS3
1011Y+C3
0100CVBS4
1100Y+C4
0101CVBS_DTV

other output muted

2003 Dec 08 19

SELECTED

SIGNAL

CMR MODE

0 top sync clamp mode
1 black level clamp mode

Table 49 Clamp pulse selection for RGB and YUV signals

CLPS MODE

0 clamp pulse of primary channel
1 clamp pulse of secondary channel

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

Table 50 Selection of secondary audio channel

SEA2 SEA1 SEA0 SELECTED SIGNAL

0 0 0 AMint (L) and AMext (R);

note 1
0 0 1 L1 and R1
0 1 0 L2 and R2
0 1 1 L3 and R3
1 0 0 L4 and R4
1 0 1 L5 and R5
1 1 0 MIC1 (L) and MIC2 (R)
1 1 1 AMext (L) and AMint (R);

note 1

Note

1. Selection between AMint and AMext must be done by
digital video processor.

Table 51 Secondary audio channel mode

MONO MNM1 MNM0 MODE

0 −−stereo; see Table 50
1 0 0 mono (L) and AMint (R);

note 1

1 0 1 mono (L) and AMext (R);

note 1

1 1 0 mono (L) and MIC1 (R);

note 1

1 1 1 mono (L) and MIC2 (R);

note 1

Note

1. Mono is (L + R)/2; when AM is selected in Table 50,
mono is AMint for SEA[2:0] = 000 and AMext for
SEA[2:0] = 111. A more comprehensive table can be
found in the application note.

PNX3000

Table 52 Selection of primary audio channel

PRA2 PRA1 PRA0 SELECTED SIGNAL

0 0 0 AMint (L) and AMext (R);

note 1
0 0 1 L1 and R1
0 1 0 L2 and R2
0 1 1 L3 and R3
1 0 0 L4 and R4
1 0 1 L5 and R5
1 1 1 AMext (L) and AMint (R);

note 1

Note

1. Selection between AMint and AMext must be done by
digital video processor.

Table 53 Gain from DSND inputs to SCART outputs

DSG GAIN

0 0 dB; to be used with 5 V audio supply
1 6 dB; to be used with 8 V audio supply

Table 54 Selection of SCART1 audio output

AMX A1S2 A1S1 A1S0

0000AMint
0001LR1
0010LR2
0011LR3
0100LR4
0101LR5
0110DSND1
0111DSND2
1000AMext

SELECTED

SIGNAL

2003 Dec 08 20

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

Table 55 Selection of LINE audio output

AMX A0S2 A0S1 A0S0

0000AMint
0001LR1
0010LR2
0011LR3
0100LR4
0101LR5
0110DSND1
0111DSND2
1000AMext

Table 56 Microphone input 2 gain

M2G GAIN

0low
1 high

Table 57 Microphone input 1 gain

SELECTED

SIGNAL

PNX3000

Table 59 Selection of SCART2 audio output

AMX A2S2 A2S1 A2S0

0000AMint
0001LR1
0010LR2
0011LR3
0100LR4
0101LR5
0110DSND1
0111DSND2
1000AMext.

Table 60 IRQ mask bits for status byte 0

IM6 TO IM0 IRQ OUTPUT

0 IRQ output not activated
1 IRQ output is activated when the

corresponding status bit changes
value

SELECTED

SIGNAL

(1)

M1G GAIN

0low
1 high

Table 58 Microphone amplifiers on/off

MICON MODE

0 microphone amplifiers not active
1 normal operation

8.2 Output status registers

Table 61 Output status registers; subaddresses must not be sent, they are automatically incremented

FUNCTION

Status byte 0 00 POR MSUP ASUP ROK LOCK VID AFA AFB
Status byte 1 01 00000DCF0AGC
Reserved 02 00000000
Status byte 3 03 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

SUB

ADDR

D7 D6 D5 D4 D3 D2 D1 D0

Note

1. The IRQ output is always activated if status bit
POR = 1.

DATA BYTE

2003 Dec 08 21

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

Table 62 Power-on-reset

POR CONDITION

0 normal
1 Power-down

Table 63 Main supply

MSUP CONDITION

0 main supply not OK
1 main supply OK

Table 64 Audio supply

ASUP CONDITION

0 audio supply not OK
1 audio supply OK

Table 65 Reference frequency

ROK CONDITION

0 reference frequency not present
1 reference frequency present

Table 66 IF PLL lock indication

LOCK INDICATION

0 IF PLL not locked
1 IF PLL locked

Table 67 Video identification

PNX3000

Table 68 AFC output

AFA AFB CONDITION

0 0 outside window; too low
0 1 outside window; too high
1 0 in window; below reference
1 1 in window; above reference

Table 69 Data link current test

DCF INDICATION

0 data link current test OK
1 data link current test FAIL

Table 70 Tuner AGC output

AGC INDICATION

0 tuner gain reduction active
1 no gain reduction of tuner

Table 71 Mask version indication

ID7 ID6 ID5 ID4 ID3 MASK VERSION

00000N1A or N1B version
00001−
00010N1C version
00011N1D version
00100N1E or N1F version
00101N2B version

VID INDICATION

0 no video signal detected
1 video signal detected

2003 Dec 08 22

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

9 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

P

V

CC(1ASW)

V

CC(2ASW)

T

stg

T

amb

T

sol

T

j

V

esd

10 THERMAL CHARACTERISTICS

main supply voltage − 6.0 V

,

audio supply voltage − 9.0 V

storage temperature −25 +150 °C
ambient temperature 0 70 °C
soldering temperature for 5 s − 260 °C
operating junction temperature − 150 °C
electrostatic discharge voltage Human body model; C = 100 pF;

R = 1.5 kΩ

pin SDA − 1500 V
all other pins − 2000 V

Machine model; C = 200 pF; R = 0 Ω−200 +200 V

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air; note 1 30 K/W

Note

1. The value given forthe thermalresistance from junction to ambientshould onlybe considered as an indication. Most
of the dissipated heat is conveyed to the ambient air through the Printed-Circuit Board (PCB) on which the IC is
mounted. The actual value of the thermal resistance depends on the number of metal layers, size and layout of the
PCB, and also on the dissipation of other components on the PCB.

11 QUALITY SPECIFICATION

In accordance with document

“SNW-FQ-611D”

.

11.1 Latch-up performance

At T

• Positive stress test: I

• Negative stress test: I

=70°C all pins meet the following specification:

amb

≥ 100 mA or V

trigger

≤−100 mA or V

trigger

trigger

trigger

≥ 1.5 V

≤−0.5 V

P(max)

P(max)

.

2003 Dec 08 23

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

12 CHARACTERISTICS

VCC=5V; T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

P

OWER SUPPLIES

V

P

I

P

V

CC(1ASW)

V

CC(2ASW)

I

CC(ASW)

V

CC(SUP)

V

CC(ASW1)

P

tot

REFERENCE VOLTAGES
V

BGDEC

V

RREF

V

VD2V5

V

POR

VOLTAGE REGULATORS
V

,

AUDO

V

DEFLO

V

,

AUDS

V

DEFLS

Video IF circuit

=25°C; unless otherwise specified.

amb

main supply voltage 4.75 5.0 5.25 V
main supply current − 285 320 mA

,

audio supply voltage note 1 4.75 8.0 8.4 V

audio supply current note 1 − 3.5 5.0 mA
minimum required voltage

− 4.0 − V

to set status bit MSUP
minimum required voltage

− 4.0 − V

to set status bit ASUP
total power dissipation − 1.45 1.70 W

bandgap decoupling

2.20 2.30 2.40 V

voltage on pin BGDEC
voltage on pin RREF 2.19 2.30 2.41 V
digital supply decoupling

2.35 2.50 2.65 V

voltage at pin VD2V5
Power-On Reset (POR)

1.8 2.0 2.2 V

level on pin VD2V5

output voltage range note 2 1.25 − 3.30 V

voltage at feedback pin 1.24 1.27 1.31 V

VIDEO IF AMPLIFIER INPUTS
V

i(dif)(rms)

input sensitivity
(differential; RMS value)

AGC set −−−

fi= 38.9 MHZ − 75 150 µV
fi= 45.75 MHz − 75 150 µV
fi= 58.75 MHz − 75 150 µV

R

i(dif)

input resistance

note 3 − 2 − kΩ

(differential)

C

i(dif)

input capacitance

note 3 − 3 − pF

(differential)

∆G

v

V

i(max)(dif)(rms)

gain control range 64 −− dB
maximum input signal

(differential; RMS value)

2003 Dec 08 24

150 −− mV

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

PLL DEMODULATOR; notes 4 and 5
∆f

VCO

f

cr(PLL)

t

d(ident)

VIDEO AMPLIFIER OUTPUT: PIN CVBSOUTIF; note 6
V

o(z)

V

o(ts)

V

o(w)

V

o(dem)(p-p)

∆V

o

Z

o(v)

I

bias(int)

I

source(max)

B

v(−3dB)

G

dif

ϕ

dif

NL

vid

V

clamp

N

clamp

N

ins

d

blue

d

yellow

S/N signal-to-noise ratio notes 10 and 14 −−−

∆V

rc

free-running frequency
offset of VCO

catching range PLL without SAW filter; referred to

PLL not locked; deviation from
nominal setting

−500 − 0 kHz

±1 −− MHz

selected IF system frequency

delay time of identification bit LOCK = 1 −−20 ms

zero signal output level negative modulation; note 7 − 3.5 − V

positive modulation; note 7 − 1.1 − V
top sync level negative modulation 1.3 1.4 1.5 V
white level positive modulation − 3.4 − V
demodulated CVBSoutput

signal (peak-to-peak value)
difference in amplitude

between negative and

recommended settings for bits

VA1 and VA0; note8

recommended settings for bits

VA1 and VA0; note8

1.8 2.0 2.2 V

− 015%

positive modulation
video output impedance − 150 250 Ω
internal bias current of

− 0.9 − mA
NPN emitter follower
output transistor

maximum source current −−1mA
bandwidth of demodulated

at −3 dB; before sound trap 6 9 − MHz

video output signal
differential gain negative modulation; note 9 − 25 %

positive modulation; note 9 − 35 %
differential phase notes 9 and 10 −−5 deg
video non-linearity note 11 −−5%
white spot clamp level − 3.8 − V
noise inverter clamping

note 12 − 0.9 − V
level

noise inverter insertion

note 12 − 2.3 − V
level

intermodulation at ‘blue’ notes 10 and 13

Voat 0.92 or 1.1 MHz 60 66 − dB
Voat 2.66 or 3.3 MHz 60 66 − dB

intermodulation at ‘yellow’ notes 10 and 13

Voat 0.92 or 1.1 MHz 56 62 − dB
Voat 2.66 or 3.3 MHz 60 66 − dB

weighted 56 60 − dB
unweighted 49 53 − dB

residual carrier signal note 10 − 5.5 − mV

2003 Dec 08 25

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

∆V

rc(2H)

IF AND TUNER AGC; note 15

Timing of IFAGC

MVI modulated video

t

res

Tuner take over adjustment (via I2C-bus)

V

start(min)(rms)

V

start(max)(rms)

Tuner control output

V

o(max)

V

o(sat)

I

o(TUNERAGC)

I

L

∆V

i

AFC OUTPUT (VIA I2C-BUS); note 16
f

AFC

∆f

w

∆f

lw

DTV IF circuit

residual 2nd harmonic of

note 10 − 2.5 − mV
carrier signal

30% AM for 1 V to 100 mV;
interference

0 to 200 Hz (B/G standard)
response time IF input signal amplitude

−−10 %

− 2 − ms

increase of 52 dB; positive and

negative modulation; IFAGC

time constant set to normal

IF input signal amplitude

decrease of 52 dB

negative modulation − 50 − ms
positive modulation − 100 − ms

minimum starting level for

− 0.4 0.8 mV
tuner take over (RMS
value)

maximum starting level for

100 150 − mV
tuner take over (RMS
value)

maximum tuner AGC

maximum tuner gain; note 3 −−5V

output voltage
output saturation voltage minimum tuner gain; Io=1mA −−300 mV
tuner AGC output current

0 − 1mA
range

leakage current RFAGC −−1 µA
input signal variation for

0.5 2 4 dB

complete tuner control

AFC resolution − 2 − bits
window sensitivity − 125 − kHz
window sensitivity in large

− 275 − kHz

window mode

DTV IF AMPLIFIER INPUT
V

i(dif)(rms)

input sensitivity

fi between 30 and 60 MHz − 75 150 µV

(differential; RMS value)

R

i(dif)

input resistance

note 3 − 2 − kΩ

(differential)

2003 Dec 08 26

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

C

i(dif)

∆G

v

V

i(max)(dif)(rms)

DTV IF MIXER
f

osc

N

ϕ(osc)

PB

ll

PB

ul

PBR pass-band ripple −−0.5 dB
B

sb

α

sb

EXTERNAL AGC CONTROL
∆V

i

Z

i

DTV OUTPUT (DOWN-MIXED OUTPUT SIGNAL)
V

o(dif)(p-p)

V

o(dif)(p-p)(max)

Z

o(dif)

V

O

I

bias(int)

I

source(max)

Sound IF circuit

input capacitance

note 3 − 3 − pF

(differential)
gain control range 64 −− dB
maximum input signal

150 −− mV
(differential; RMS value)

oscillator frequency step size 250 kHz 24 − 64 MHz
oscillator phase noise carrier to noise ratio in dBc/Hz −−92 − dB
lower limit pass-band −−1.0 MHz
upper limit pass-band 10.0 −− MHz

stop band − 44 − MHz
stop band attenuation 40 −− dB

voltage range for full

1 − 3V
control of the amplifier

input impedance 1 −− MΩ

differential output signal
(peak-to-peak value)

internal AGC mode; no
modulation

DTV 1st IF mode; f = 40 MHz − 0.68 − V
DTV 2nd IF mode; f = 4 MHz − 1.20 − V

maximum allowed
differential output signal
(peak-to-peak value)

internal AGC mode; no
modulation; note 17

DTV 1st IF mode; f = 40 MHz − 0.95 − V
DTV 2nd IF mode; f = 4 MHz − 1.68 − V

output impedance

− 150 −Ω

(differential)
DC output level DTV 1st IF mode − 1.15 − V

DTV 2nd IF mode − 3.0 − V

internal bias current of

− 2 − mA

emitter followers
maximum allowed source

−−2mA

current

SOUND IF AMPLIFIER
V

i(rms)

input sensitivity (RMS

−3dB − 45 tbf dBµV

value)

V

i(max)(rms)

maximum input signal
(RMS value)

R

i(dif)

input resistance

note 3 − 2 − kΩ

(differential)

2003 Dec 08 27

tbf 100 − dBµV

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

C

i(dif)

∆G

v

α

ct(SIF-VIF)

SOUND IF INTERCARRIER OUTPUT ON DTV OUTPUT,FMMODULATION; note 18
V

o(dif)(rms)

B

−3dB

∆V

r(SC)(rms)

Z

o(dif)

V

O

I

bias(int)

I

source(max)

S/N

W

AM SOUND OUTPUT; note 20
V

o(rms)

THD total harmonic distortion 54% modulation − 0.5 1.0 %

B

−3dB

S/N

W

PSRR power supply ripple

input capacitance

note 3 − 3 − pF

(differential)
gain control range − 55 − dB
crosstalk attenuation

50 −− dB
between SIF and VIF input

differential output signal

SC1; sound carrier 2 off 75 100 125 mV

amplitude (RMS value)
bandwidth (−3 dB) 7.5 8.5 − MHz
residual IF sound carrier

− 2 − mV

(RMS value)
output impedance

− 150 −Ω

(differential)
DC output voltage − 1.3 − V
internal bias current of

− 2 − mA

emitter followers
maximum allowed source

− 2 − mA

current
weighted S/N ratio

(SC1/SC2)

ratio of PC/SC1 at vision IF
input of 40 dB or higher;
note 19

black picture 53/48 58/55 − dB
white picture 52/47 55/53 − dB
6 kHz sinewave

44/42 48/46 − dB

(black-to-white modulation)
250 kHz sine wave

44/25 48/30 − dB

(black-to-white modulation)
sound carrier subharmonics

45/44 51/50 − dB

(f = 2.75 MHz ± 3 kHz)
sound carrier subharmonics

46/45 52/51 − dB

(f = 2.87 MHz ± 3 kHz)

AF output signal amplitude

54% modulation 400 500 600 mV

(RMS value)

80% modulation − tbf 5.0 %

−3 dB AF bandwidth 100 125 − kHz
weighted signal-to-noise

54% modulation 47 53 − dB

ratio

5 V main supply − 17 − dB

rejection ratio

2003 Dec 08 28

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2nd sound IF AGC circuit

2ND SOUND IF EXTERNAL INPUT
∆V

i(rms)

∆fi input frequency range note 21 4 − 10.7 MHz
R

i

C

i

2ND SOUND IF AGC
∆G gain control range − 25 − dB

I

ch(AGC)

I

dch(AGC)

DIGITAL OUTPUT
n

d(p-p)

Sound trap and group delay correction filter

input voltage range (RMS

18 − 320 mV
value)

input resistance note 3 − 25 − kΩ
input capacitance note 3 − 3 − pF

charge current AGC pin FM mode −−12.5 µA

AM mode −−2.5 µA

discharge current AGC pin FM mode −−50 µA

AM mode −−2.5 µA
overload − 1 − mA

decimal digital output level
(peak-to-peak value)

FM mode − 716 −
AM mode; no modulation − 358 −

SOUND TRAP
B

v(−3dB)

∆V

chrom(p)

−3 dB video bandwidth
(sound trap + group delay)

peaking at chroma

f

= 4.5 MHz 3.90 4.00 − MHz

SC1

f

= 5.5 MHz 4.80 4.90 − MHz

SC1

f

= 6.0 MHz 5.25 5.35 − MHz

SC1

f

= 6.5 MHz 5.70 5.80 − MHz

SC1

subcarrier frequency

α

SC1

attenuation at first sound
carrier f

SC1

PNX3000HL/N2; all trap
frequencies

PNX3000HL/S6; all trap
frequencies

α

SC2

attenuation at second
sound carrier f

SC2

f = 4.726 MHz; f
f = 5.742 MHz; f
f = 6.55 MHz; f

f = 6.742 MHz; f
GROUP DELAY CORRECTION; figures 6 and 7; note 22
t

d(g)

group delay f = 4.43 MHz; sound trap

frequency 5.5 MHz; sound trap

only

f = 4.43 MHz; sound trap

frequency 5.5 MHz; sound trap

plus group delay correction

filter

− 1.0 2.0 dB

28 33 − dB

24 30 − dB

= 4.5 MHz 21 27 − dB

SC1

= 5.5 MHz 21 27 − dB

SC1

= 6.0 MHz 12 18 − dB

SC1

= 6.5 MHz 18 24 − dB

SC1

− 180 − ns

− 170 − ns

2003 Dec 08 29

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Video switches

CVBS AND YC SWITCHES
V

i(CVBS/Y)(p-p)

V

i(CVBS/Y)(clip)

I

i(CVBS/Y)

α

sup(CVBSn)

V

i(C)(p-p)

Z

i(C)

VIDEO IDENT FUNCTION
V

sync(min)

t

d(ident)

ANALOG CVBS OUTPUTS: PINS CVBSOUTA AND CVBSOUTB
Z

o

V

o(p-p)

V

O

DIGITAL OUTPUTS

CVBS or Y input voltage

− 1.0 1.76 V

(peak-to-peak value)
CVBS or Y clipping level black-to-peak video − 1.33 − V
CVBS or Y input current outside clamp pulse − 0 −µA

during clamp pulse −10 − +10 µA

suppression of

note 10 50 −− dB

non-selected CVBS input
signal

chrominance input voltage

100% colour bar; note 3 − 885 1264 mV

(peak-to-peak value)
chrominance input

− 50 − kΩ

impedance

minimum sync pulse

70 100 140 mV

amplitude
delay time of identification

after the Video IF AGChas
stabilized on a new

I2C status bit VID = 1; after the

Video IF AGC hasstabilized on

a new transmitter

−−10 ms

transmitter

output impedance −−250 Ω
output signal amplitude

at input signal of 1.0 V (p-p) − 2.0 − V

(peak-to-peak value)
DC output level top sync − 0.4 − V

output muted − 0.5 − V

CVBS/Y signal

n

d(black)

decimal digital output level

black clamp mode − 240 −

for black

n

d(white)

decimal digital output level

nominal input signal − 652 −

for white

C signal

n

d(black)

decimal digital output level
for black

n

d(p-p)

decimal digital output
amplitude (peak-to-peak

nominal input level; 100%

colour bar

value)

2003 Dec 08 30

480 512 544

− 520 −

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

RGB, YPbPr and YUV inputs

ANALOG INPUTS

General

I

i

RGB mode

V

i(b-w)

YPbPr mode

V

i(Y)(p-p)

V

i(Pb)(p-p)

V

i(Pr)(p-p)

YUV mode

V

i(Y)

V

i(U)(p-p)

V

i(V)(p-p)

DIGITAL OUTPUTS

input current outside clamp pulse − 0 −µA

during clamp pulse −10 − +10 µA

input signal amplitude

− 0.7 1.0 V

(black-to-white value)

Y input signal amplitude

top sync-to-white − 1.0 1.43 V

(peak-to-peak value)
Pb input signal amplitude

100% colour bar − 0.7 1.0 V

(peak-to-peak value)
Pr input signal amplitude

100% colour bar − 0.7 1.0 V

(peak-to-peak value)

Y input signal amplitude top sync-to-white − 1.43 2.04 V
U input signal amplitude

100% colour bar − 1.77 2.53 V

(peak-to-peak value)
V input signal amplitude

100% colour bar − 1.40 2.00 V

(peak-to-peak value)

General

∆t

d

delay difference for the

note 10 − 020ns

three channels

Y signal

n

d(black)

decimal digital output level

black clamp mode − 240 −

for black

n

d(white)

decimal digital output level

nominal input level − 788 −

for white

U and V signals;

n

d(black)

note 23

decimal digital output level

black clamp mode − 512 −

for black

n

d(p-p)

decimal digital output
amplitude (peak-to-peak

nominal input level; 100%

colour bar

value)

Video anti-alias filters

CVBS, YYC,CAND 2ND SIF FILTERS
f

pb(−1dB)

−1.0 dB pass-band
frequency

2003 Dec 08 31

− 716 −

− 8.0 − MHz

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

f

pb(−3dB)

f

sb(−35dB)

t

d(g)

E

∆G

E

∆ϕ

S/N signal-to-noise ratio B = 5 MHz; note 24 60 −− dB
Y

FILTERS

YUV

f

pb(−1dB)

f

pb(−3dB)

f

sb(−35dB)

t

d(g)

S/N signal-to-noise ratio 1fHmode: B = 5 MHz

U AND V FILTERS
f

pb(−1dB)

f

pb(−3dB)

f

sb(−35dB)

t

d(g)

S/N signal-to-noise ratio 1fHmode: B = 5 MHz

FILTER FOR DTV 2ND IF SIGNAL
f

pb(−1dB)

f

pb(−3dB)

−3.0 dB pass-band

− 9.0 − MHz

frequency

−35 dB stop band

− 20 − MHz

frequency
group delay at 1.0 MHz − 36 − ns

at 5.0 MHz − 42 − ns

differential gain error note 9 − 25 %
differential phase error notes 9 and 10 −−5 deg

−1.0 dB pass-band
frequency

−3.0 dB pass-band
frequency

−35 dB stop band
frequency

1fHmode − 8.0 − MHz

2fHmode − 16 − MHz

1fHmode − 9.0 − MHz

2fHmode − 18 − MHz

1fHmode − 20 − MHz

2fHmode − 40 − MHz

group delay at 1 MHz; 1fHmode − 36 − ns

at 1 MHz; 2fHmode − 18 − ns

at 5 MHz; 1fHmode − 42 − ns

at 10 MHz; 2fHmode − 21 − ns

60 −− dB

2fHmode: B = 10 MHz; note 24

−1.0 dB pass-band
frequency

−3.0 dB pass-band
frequency

−35 dB stop band
frequency

1fHmode − 4.0 − MHz

2fHmode − 8.0 − MHz

1fHmode − 4.5 − MHz

2fHmode − 9.0 − MHz

1fHmode − 10 − MHz

2fHmode − 20 − MHz

group delay at 1 MHz; 1fHmode − 72 − ns

at 1 MHz; 2fHmode − 36 − ns

at 2.5 MHz; 1fHmode − 84 − ns

at 5 MHz; 2fHmode − 42 − ns

60 −− dB

2fHmode: B = 10 MHz; note 24

−1.0 dB pass-band

− 10 − MHz

frequency

−3.0 dB pass-band

− 12 − MHz

frequency

2003 Dec 08 32

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

f

sb(−35dB)

t

d(g)

S/N signal-to-noise ratio B = 10 MHz; note 25 60 −− dB

Video analog-to-digital converters

GENERAL; note 26
B

v(−3dB)

f

sample

RES resolution − 10 − bit
STATIC MEASUREMENTS
DNL differential non-linearity f

INL integral non-linearity f
DYNAMIC MEASUREMENTS
THD total harmonic distortion f

S/N signal-to-noise ratio f

ENOB effective number of bits f

Audio selectors

−35 dB stop band

− 44 − MHz

frequency
group delay − 22 − ns

− 32 − ns

−3 dB signal bandwidth 1fHmode − 9 − MHz

sample frequency 1fHmode − 27 − MHz

= 54 MHz; f

clk

= 54 MHz; f

clk

= 27 MHz; f

clk

f

= 54 MHz; f

clk

= 27 MHz; B = 5 MHz − 58 − dB

clk

f

= 54 MHz; B = 10 MHz − 58 − dB

clk

= 54 MHz; f

clk

= 10 MHz − 0.7 − LSB

signal

= 10 MHz − 1 − LSB

signal

= 5 MHz −−63 − dB

signal

= 10 MHz −−63 − dB

signal

= 10 MHz − 9.0 − bits

signal

LR INPUTS
V

i(max)(rms)

R

i

G gain from LR inputs to

maximum input voltage
(RMS value)

5 V audio supply 1.0 −− V

8 V audio supply 2.0 −− V

input resistance 24 32 − kΩ

outputs unloaded −0.4 0 +0.3 dB

analog outputs

α

(LRn)

crosstalk attenuation from

f = 10 kHz 70 80 − dB

non-selected inputs
DSND INPUTS FOR AUDIO SIGNALS COMING FROM DIGITAL VIDEO PROCESSOR
V

i(max)(rms)

maximum input signal

amplitude (RMS value)
R

i

G gain from DSND inputs to

input resistance 24 32 − kΩ

5 V audio supply; DSG = 0;

analog outputs

outputs unloaded
8 V audio supply; DSG = 1;

outputs unloaded

α

(DSNDn)

crosstalk attenuation from

non-selected inputs
MICROPHONE AMPLIFIERS; note 27
R

i

input resistance − 20 − kΩ

1.0 −− V

−0.4 0 +0.3 dB

5.6 6.0 6.3 dB

70 80 − dB

2003 Dec 08 33

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

G

low

G

high

∆f frequency range 50 − 20000 Hz
THD + N total harmonic distortion

S/N signal-to-noise ratio referred to 16 mV (RMS) input

ANALOG OUTPUTS
V

o(max)(rms)

Z

o

THD + N total harmonic distortion

S/N signal-to-noise ratio referred to 0 dBV output level;

∆f frequency range 20 − 20000 Hz
PSRR power supply ripple

Audio analog-to-digital converters

low gain bits M1G = M2G = 0 − 17 − dB

high gain bits M1G = M2G = 1 − 35 − dB

plus noise

1 kHz input signal at

0.9 V (RMS) output level

−74 −80 − dB

70 76 − dB

level; low gain
referred to 16 mV (RMS) input

74 80 − dB

level; high gain

maximum output signal

amplitude (RMS value)

5 V audio supply 1.0 −− V
8 V audio supply 2.0 −− V

output impedance − 500 650 Ω

1 kHz input signal

plus noise

+6 dBV output level −80 −88 − dB

−54 dBV output level;

−36 −40 − dB

A-weighted

90 96 − dB

A-weighted

1 kHz ripple frequency

rejection ratio

ripple on 5 V main supply − 43 − dB
ripple on 8 V audio supply − 45 − dB

DIGITAL AUDIO OUTPUTS; note 28
V

i(max)(rms)

THD + N total harmonic distortion

maximum input voltage

(RMS value)

plus noise

5 V audio supply 1.0 −− V
8 V audio supply 2.0 −− V
1 kHz input signal

+0 dBV output level −−78 − dB

−54 dBV output level;
A-weighted

S/N signal-to-noise ratio referred to 0 dBV input level;

A-weighted

α

cs

V

o

PSRR power supply ripple

channel separation 0 to 20 kHz − 80 − dB

digital output level at 2 V (RMS) input level −−4.3 − dBFS

8 Vaudio supplyvoltage;1 kHz

rejection ratio

ripple frequency

ripple on 5 V main supply − 54 − dB
ripple on 8 V audio supply − 55 − dB

5 Vaudio supplyvoltage;1 kHz
ripple frequency

2003 Dec 08 34

−−30 − dB

− 86 − dB

− 18 − dB

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Timing circuit

HV INPUT SIGNALS: PINS HV_PRIM AND HV_SEC; notes 29 and 30

Timing specification for HV pulses coming from digital video processor;

t

(HV-sync)

t

W(HV)

time between start HV

pulse and start of

horizontal sync pulse on

CVBS/Y signal

1fH TV mode − 0.6 −µs
2fH mode; HDTV = 0 − 0.3 −µs
2fH mode; HDTV = 1 − 0.3 −µs

width of HV pulses 1fH TV mode

normal lines − 72 − ck
clamp disable lines − 128 − ck
vsync lines − 288 − ck

2fHmode HDTV = 0

normal lines − 36 − ck
clamp disable lines − 64 − ck
vsync lines − 144 − ck

2fHmode; HDTV = 1

normal lines − 20 − ck
clamp disable lines − 44 − ck
vsync lines − 144 − ck

Detection of clamp disable lines

t

det(clamp)(dis)

clamp disable detection 1fH TV mode − 80 − ck

2fHmode; HDTV = 0 − 40 − ck
2fHmode; HDTV = 1 − 24 − ck

Detection of vsync lines

t

det(vsync)

vsync detection 1fH TV mode − 255 − ck

2fHmode; HDTV = 0 − 136 − ck
2fHmode; HDTV = 1 − 136 − ck

Internal clamp pulses

t

d(HV-clamp)

t

W(clamp)

delay between start of

HV pulse and start of

clamp pulse

1fH TV mode − 80 − ck
2fHmode; HDTV = 0 − 40 − ck
2fHmode; HDTV = 1 − 24 − ck

width of clamp pulse 1fH TV mode − 44 − ck

2fHmode; HDTV = 0 − 22 − ck

2fHmode; HDTV = 1 − 17 − ck
CRYSTAL REFERENCE FREQUENCY INPUT: PIN XREF
R

C
V

i
i

i(p-p)

input resistance 25 35 45 kΩ
input capacitance − 3 − pF
input signal amplitude

(peak-to-peak value)

see Fig.8

1 − 3.5 V

2003 Dec 08 35

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Data link transmitters

G

ENERAL

f

word(CLK)

WL word length − 44 − bits
f

D

f

bit(CLK)

OUTPUT DRIVERS FOR DATA AND STROBE SIGNALS
∆V

o

V

o(dif)(p-p)

R

o

R

L

East-west drive circuit: pins EWVIN, EWIOUT and REW

R

i

∆V

i

R

ew

∆V

o

∆I

o

2

C-bus control inputs and outputs

I

word clock frequency − 13.5 − MHz

data rate − 594 − Mbit/s
bit clock frequency individual data and strobe

− 297 − MHz

signals

voltage swing
(peak-to-peak value)

differential output voltage

individual pins; output loaded

− 0.3 − V

with 100 Ω

output loaded with 100 Ω− 0.6 − V

(peak-to-peak value)
output resistance −−50 Ω
load resistance connected between positive

− 100 −Ω

terminal and negative terminal

input resistance − 40 − kΩ
input voltage range 0 − 3.5 V
external conversion

note 31 − 750 −Ω

resistor
output voltage range note 31 1.0 − V

cc

V

output current range 0 − 1.2 mA

SDA/SCL INPUTS AND OUTPUT; note 32
V

i

V

IL

V

IH

I

IL

I

IH

V

OL

C

i

input voltage level 0 − 5.5 V
LOW-level input voltage −−0.2 × VCCV
HIGH-level input voltage 0.5 × VCC−− V
LOW-level input current Vi=0V − 0 −µA
HIGH-level input current Vi= 5.5 V − 0 −µA
LOW-level output voltage SDA pin; IL=3mA −−0.4 V

input capacitance − 510pF
IRQ OUTPUT; note 33
V

OL

V

OH

LOW-level output voltage IRQ pin; IL= 1.5 mA −−0.4 V

HIGH-level output voltage open drain −−5.5 V

Notes

1. The supply voltage for the analog audio part may have a value between 5 and 8 V. For a supply voltage of 5 V the
maximum amplitude of in- and output signalsis 1V (RMS). For a supplyvoltage of 8 V the maximum amplitude of in­and output signals is 2V (RMS).

2. The value of the regulated voltage is determined by the external resistive voltage divider. The voltage range
mentioned relates to the voltage at the emitter of the external transistor. The stability of the voltage regulator loop

2003 Dec 08 36

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

depends on the value of thedecoupling capacitorC

I

C

is µF, with I

dec

o

1.5=

×

-----­V

o

in mA.

o

3. This parameter is not tested during production and is just given as application information for the designer of the
television receiver.

4. Loop bandwidth BL= 60 kHz (natural fN= 15 kHz; damping factor d = 2; calculated with top sync level as IF PLL
input signal level).

5. The IF PLL demodulator uses an internal VCO (no external LC-circuit required) which is calibrated by means of a
digital control circuit which uses the clock frequency of the microcontroller/teletext decoder as a reference. The
required IF frequency for the various standards is set via the I2C-bus. When the system is locked the resulting
IF frequency is very accurate with a deviation from the nominal value of less than 25 kHz.

6. Measured at pin CVBSOUTIF with 10 mV (RMS) top sync input signal at VIF input.

7. So called projected zero point, i.e. with switched demodulator.

8. The signal amplitude at the CVBSOUTIF output depends on the setting of bits VA1 and VA0. The recommended
settings for negative modulation (bit PMOD = 0) is VA1 = VA0 = 1. For positive modulation (bit PMOD = 1) the
settings VA1 = 1 and VA0 = 0 is recommended. The V
recommended settings are used.

9. Measured in accordance with the test line given in Figure 3. For the differential phase test the peak white setting is
reduced to 87%:

a) The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and

smallest value relative to the subcarrier amplitude at blanking level.

b) The phase difference is defined as the difference in degrees between the largest and smallest phase angle.

10. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
batches which are made in the pilot production period.

11. This figure is valid for the complete video signal amplitude (peak white-to-black), see Figure 4.

12. The noise inverter is only active in the ‘strong signal mode’ (no noise detected in the incoming signal)

13. The test set-up and input conditions are given in Fig.5. Measurement is done with an input signal of 10 mV (RMS).

14. Measured atan input signal of 10 mV (RMS).The S/N is the ratio of black-to-whiteamplitude to the black levelnoise
voltage (RMS value); B = 5 MHz. Weighted in accordance with CCIR 567.

15. The time-constant of the IF AGC is internal and the speedof the AGC can be set via bus bits AGC1 andAGC0. The
AGC response time is also dependent onthe acquisition time of thePLL demodulator. The values givenare valid for
the ‘norm’ setting (AGC1 = 0 and AGC0 = 1) and when the PLL is in lock.

16. The AFC control voltage is generated by the digital tuning system of the PLL demodulator. This system uses the
external crystal frequency as a reference and is thereforevery accurate. For this reason no maximumand minimum
values are given for the window sensitivity figures. The tuning information is supplied to the tuning system via the
I2C-bus. Two bits are reserved for this function. The AFC value is valid only when bit LOCK = 1.

17. Exceeding this amplitude leads to intermodulation distortion.

18. The intercarrier sound (2nd SIF) signalis not normallyan analog outputsignal of the IC. It can be made available on
the DTV output pins by setting bus bits DSIF = 1 and DFIF = 0.

19. The weighted S/N ratio is measured under the following conditions:
a) The vision IF modulator incidental phase modulation for black-to-white jumps must be less than 0.5 degrees
b) QSS AF performance of the vision IF modulator, measured with the television demodulator AMF2 (audio output

and weighted S/N ratio) better than 60 dB (deviation 27 kHz) for 6 kHz sine wave black-to-white modulation

c) Picture-to-sound carrier ratio of the vision IF modulator: PC/SC1 = 13 dB (transmitter)

on the emitter ofthe externaltransistor. Recommendedvalue

dec

o(dem)(p-p)

and ∆Vo values specified are valid if the

2003 Dec 08 37

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

d) Themeasurements must becarriedout withtheSiemens SAW filtersG3962for vision IFandG9350 for sound IF.

Input level for sound IF 10 mV (RMS) with 27 kHz deviation

e) The PC/SC ratio at the vision IF input is calculated as the addition of the TV transmitter ratio and the SAW filter

PC/SC ratio. This PC/SC ratio is necessary to achieve the S/NW values as indicated.

20. The demodulated AM sound signal can be made available in the analog domain on LINE or SCART audio outputs
by selecting AM internal (bus bit AMX = 0).

21. The frequency range of the2nd SIF channelis limited by the 2nd SIFanti-alias filter.If a10.7 MHz FM radio IF signal
is supplied to the external 2nd SIF input; an external 10.7 MHz bandpass filter must be used; and the internal
anti-alias filter must be bypassed by setting bus bit SLPM = 1.

22. The cascade of sound trap and group delay correction filter compensates for the group delaypre-distortion ofthe BG
standard, curve A (see “Rec. ITU-R BT.470-4”). The indicated values are the difference between the group delay at

4.43 MHz and the group delay at 10 kHz.

23. The digitized U and V signals have the following polarity: U = +(B−Y) and V = +(R−Y).

24. The S/N ratio is defined as the ratio of the full scale black-to-white amplitude to the black level noise voltage
(RMS value).

25. The S/N ratio is defined as the ratio of the full scale peak-to-peak signal amplitude to the zero signal noise voltage
(RMS value).

26. The video ADC is specified as a stand-alone circuit. Distortion and noise of the video switch and anti-alias filters is
not included.

27. The gain of the microphone amplifiers can be switched between low (17 dB) and high (35 dB). The low gain can be
used for microphones witha sensitivity between 5 mV (RMS) and40 mV (RMS) at 94 dB SPL. Thehigh gain can be
used for microphones with a sensitivity of less than 5 mV (RMS) at 94 dB SPL.

28. If the audio supply voltage is 8 V; the 5 V full scale reference voltage for the audio A to D converters at pin 91
(VAADCP) is generated by the IC itself, using the internal bandgap reference. This gives the best power supply
rejectionratio forthe digitalaudio outputs. Ifthe audiosupply voltage is5 V; pin 91must beconnected to theexternal
5 V supply. This results in a reduced power supply rejection ratio for the digital audio outputs.

29. Signals HV_PRIM and HV_SEC must be generated by the digital video processor using a 13.5 MHz clock. Where
pulse widths are specified in clock pulses, a 13.5 MHz clock is assumed (1 clock pulse is 74.1 ns). To enable
detectionof theverticalblanking interval,a larger pulsewidth is usedfor a numberof lines duringthe vertical blanking
period; see Figures 9 and 10.

30. Most timing parameters in this section are expressed in number of clock cycles, abbreviated as ck.

31. The east-west drive circuit is avoltage to current converter circuit, that requires an external conversion resistor. The
opendrain outputtransistor can onlysink current.Therelation betweeninput voltage andoutput currentis as follows:

V

i

=

I

------------------- -

o

4R

equal to V
not be larger than 1.2 mA.

32. The switching levels of pins SDA and SCL are compatible with an external signal amplitude of 3.3 V and 5 V.

33. The IRQ output is an open-drain output; active LOW. The pin IRQ must be loaded with a pull-up resistor.

where R

×

ew

/ 4. The voltage at output pin EWIOUT must not be lower than Vi / 4 + 0.25 V. The output current must

i

is the external conversion resistor. The voltage across the external conversion resistor is

ew

2003 Dec 08 38

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

MBC212

16 %

for negative modulation

100% = 10% rest carrier

PNX3000

100%

92%

30%

handbook, full pagewidth

(%)

Fig.3 Video output signal.

MBC211

100

86
72
58
44
30

646056524844403632221210 26

time (µs)

Fig.4 Test signal waveform.

2003 Dec 08 39

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

handbook, full pagewidth

−13.2 dB

−30 dB

SC CC PC

−3.2 dB

BLUE

−13.2 dB

−30 dB

SC CC PC

YELLOW

PNX3000

−10 dB

MBC213

PC

SC

Input signal conditions:SC = soundcarrier; CC = colour carrier; PC = picture carrier.
All amplitudes with respect to top sync level.

V

Value at 0.92 or 1.1 MHz 20 log

Value at 2.66 or 3.3 MHz 20 log

=

O

-----------------------------------------------------------­V

O

V

O

-----------------------------------------------------------­V

O

Σ

CC

at 3.58 or 4.4 MHz
at 0.92 or 1.1 MHz

at 3.58 or 4.4 MHz
at 2.66 or 3.3 MHz

ATTENUATOR

3.6 dB+=

Fig.5 Test set-up intermodulation.

TEST

CIRCUIT

SPECTRUM

ANALYZER

gain setting
adjusted for blue

MCE436

2003 Dec 08 40

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

225

handbook, full pagewidth

t

d(g)

(ns)

175

125

75

25

−25
01234

PNX3000

MCE431

f (MHz)

5

400

handbook, full pagewidth

t

d(g)

(ns)

300

200

100

0

−100
01234

Fig.6 Group delay characteristic without group delay correction (sound trap: 5.5 MHz).

f (MHz)

MCE432

5

Fig.7 Group delay characteristic with group delay correction (sound trap: 5.5 MHz).

2003 Dec 08 41

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

handbook, halfpage

CVBS_in

0.6 µs

HV pulse

5.33 µs (72 ck)

HGATE

5.92 µs (80 ck)

CLP

3.26 µs (44 ck)

MCE433

handbook, halfpage

normal lines

clamp disable

lines

Vsync lines

clamp pulse

position

clamp disable

detection

PNX3000

vert. sync

detection

MCE434

Fig.8 Timing of some horizontal timing signals

compared to incoming CVBS signal
(1fHmode).

handbook, full pagewidth

video

HV pulse

detected

V pulse

video

HV pulse

det

first field second field

Fig.9 Horizontal timing of HV pulses (1fHmode).

line counter reset
in digital decoder

first fieldsecond field

det

no norm

detected

V pulse

det

Fig.10 Recommended vertical timing of incoming HV pulses (1fHmode).

2003 Dec 08 42

no norm

det

MCE435

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

13 TEST AND APPLICATION INFORMATION

13.1 Power supply decoupling

For optimalTHD and SNRperformance of theanalog and digitalaudio channels, itis important tohave stable 5 and8 V
supply voltages for the audio part of the PNX3000.

The following pins need a stable supply voltage; without disturbances in the baseband audio frequency range:

• Pins V

• Pin VAADCP (pin 91); the 5 V full scale reference for the audio ADCs. The current consumption of this pin is about

• Pin V

CC(1ASW)

to both of these pins is less than 5 mA. Note that this supply voltage may be 5 V or 8 V.

0.25 mA. Thispin must onlybe connected tothe 5 V supplyif an audiosupply voltage (pins V
of 5 V is used. If an audio supply of 8 V is used, this pin must not be connected to the 5 V supply voltage. In this case
the reference voltage is generated by the IC itself, and only a decoupling capacitor should be connected to this pin.

CC(AADC)

and V

CC(2ASW)

(pin 77) is the 5 V supply voltage for the audio ADCs. The supply current for this pin is about 23 mA.

(pins 98 and 88); the supply voltage for the analog audio switches. The supply current

CC(1ASW)

and V

CC(2ASW)

)

2003 Dec 08 43

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

13.2 Application diagram

handbook, full pagewidth

DTV
AGC

control

decoder

V

CC5

100 nF

SAW

SAW

SAW

V

CC5

10 nF

2.2 µF

(2)

100 nF

100 nF

5.6 kΩ

100 nF

(1)

(1)

100 nF

SIFIN

DTVIFINP
DTVIFINN

TUNERAGC

VIFINP
VIFINN

DTVIFPLL

V

(2)

VIFPLL

GND(1IF)

2NDSIFEXT

2NDSIFAGC

GND(2IF)
DTVOUTP
DTVOUTN
V

CC(SUP)

CVBSOUTIF

GND(SUP)

V

CC(1VSW)

CVBS0

TESTPIN1

V

CC(2VSW)

CVBS1

(1)

FUSE

CC(IF)

FUSE

2.2 µF 2.2 µF

SIFAGC

DTVIFAGC

102 101 100 99 98 97 96 909293 9195 94 89 88 87 86 85 84 83 82
103

104
105
106
107

108
109
110

111
112

113
114
115

116
117
118
119
120
121
122
123
124

125
126
127

R5

128

L5

1234567

CVBS2

VAUDO

(1)

100

nF

CVBS2 Y3 C3

1.6
kΩ

68

Ω

CVBS_IF
SCART1

2nd SIFext

180

Ω

180

Ω

TUNERAGC

ATVIFIN

DTVIFIN

1 µF

82 kΩ

100 nF

390 Ω

100 pF

to DTV channel

2.2
kΩ

CVBS0

CVBS1

SIFINN

VAUDS

(1)

100

nF

10 Ω

SIFINP

V

CVBS/Y3

1.2
kΩ

100

(2)

nF

CC(1AASW)

GND(1ASW)

C3

GND(VSW)

(1)

100
nF

2.2
µF

10 µF

MIC1

FUSE

BGDEC

(1)

100

nF

V

CC_audio

470

nF

MIC1P

MIC1N

89

C4

CVBS/Y4

Y4 C4

100

(2)

nF

10
µF

(1)

100
nF

MIC2

MIC2P

FUSE

220 Ω

470

nF

MIC2N

1110

GND(FILT)

(3)

10
µF

PNX3000

12

100 nF

V

CC5

10 Ω

2.2
µF

(2)

100

100

(2)

nF

nF

CC(2ASW)

13

RREF

VCC

V

47
kΩ

14 15

(FILT)

(1)

100

nF

CC5

V

YCOMB

Y

VAADCP VAADCN VAADCREF

CVBS_DTV

(2)

L1

R1

470

nF

L1

AMEXT

470
nF

L2

470

nF

R1

L2

TESTPIN3

CVBSOUTA

470

nF

(2)

100

nF

GND(2ASW)

16 17 18 19 20 21

CCOMB

(1)

100
nF

AMext

C

PNX3000

L3

R2

470

470

nF

nF

L3

R2

VDEFLS

VDEFLO

1.2

1.8
kΩ

kΩ

A

V

= 5 V analog supply

CC5

V

= 5 V or 8 V for audio switch matrix

CC_audio

(1) foil or ceramic capacitor.
(2) ceramic multi-layer capacitor for supply decoupling
(3) This resistor is only used when V

CC_audio

= 5 V, remove if V

CC_audio

=8V

Fig.11 Application diagram (continued in Fig.12).

2003 Dec 08 44

3D-CMB

B

2.2
kΩ

330

Ω

MCE437

68

Ω

CVBS

SCART2

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

handbook, full pagewidth

A

R3

L4

470

470

nF

nF

R3

L4

81 80 747677 7579 78 73 72 71 6870 69 67 66 65

22 23 292726 2824 25 30 31 32 3533 34 36 37

FUSE

CVBSOUTB

R4

470
nF

R4

TESTPIN2

(1)

100

nF

R1 G1

V

CC5

47

Ω

(1)

100

nF

CC(AADC)

V

FUSE

G1/Y1/Y1

R1/PR1/V1

(1)

100

nF

22
µF

GND(AADC)

B1/PB1/U1

(1)

100
nF

B1

470
nF

DSNDL1

CC(RGB)

V

100

V

CC5

470
nF

DSNDR1

PNX3000

GND(RGB)

(2)

100

nF

nF

DSNDL2

R2/PR2/V2

(1)

R2

470
nF

100

(1)

nF

SCART1 SCART2

470
nF

SCART1L

FUSE

DSNDR2

FUSE

G2/Y2/Y2

B2/PB2/U2

(1)

100
nF

G2

B2

LINE

LRL

LINEL

SCART1R

CC(VADC)

V

GND(VADC)

(2)

100

nF

V

CC5

EWVIN LINER

R

LR

SCART2L

SCART2R

64

63
62
61
60
59
58
57
56
55
54
53
52
51
50

49

48

47
46
45
44
43
42
41
40
39

38

REW

EWIOUT

DSND1

DSND2

V

CC(I2D)

DATA1P
DATA1N
STROBE1P
STROBE1N
GND(I2D)
DATA2P
DATA2N
STROBE2P
STROBE2N
FUSE
DATA3P
DATA3N
STROBE3P
STROBE3N
V

CC(DIG)

GND(DIG)

100 nF

VD2V5
HV_PRIM

HV_SEC
SCL
SDA
IRQ
FUSE
XREF
ADR

750

Ω

PNX3000

3.3

3.3

3.3

3.3
nF

nF

V

100 nF

GNDD

V

100 nF

(2)

GNDD

nF

nF

CCD5

(2)

3.3 V

CCD5

(2)

4.7kΩ4.7kΩ10

(13.5 or 27 MHz)

EWVIN

V

deflection

kΩ

ADOC

or

AVIP

data
link 1

data
link 2

data
link 3

HV_PRIM
HV_SEC
SCL
SDA
IRQ

fref

B

2.2
kΩ

330

68

Ω

Ω

CVBS

SCART3

Fig.12 Application diagram (continued from Fig.11).

2003 Dec 08 45

EWIOUT

4.7 µF

V

4.7 µF

audio

V

= 5 V analog supply

CC5

V

= 5 V digital supply

CCD5

MCE438

GNDD = digital ground

(1) foil or ceramic capacitor.
(2) ceramic multi-layer capacitor for

supply decoupling

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

14 PACKAGE OUTLINE

LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm

c

y

102

103

X

A

65

64

Z

E

PNX3000

SOT425-1

pin 1 index

128

1

w

M

p

D

H

D

(1) (1)(1)

D

20.1

0.20

19.9

0.09

0.25

b

0.27

0.17

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

1.6

0.15

0.05

1.45

1.35

UNIT A1A2A3bpcE

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

Z

D

0 5 10 mm

(1)

eHELL

H

0.5

22.15

21.85

14.1

13.9

e

H

E

w

M

b

p

39

38

v

M

A

B

v

M

B

scale

D

16.15

15.85

p

0.75

0.45

A

2

A

E

A

1

detail X

Zywv θ

Z

D

0.81

0.120.2 0.11

0.59

0.81

0.59

(A )

3

L

p

L

E

θ

o

7

o

0

OUTLINE

VERSION

SOT425-1 136E28 MS-026

IEC JEDEC JEITA

REFERENCES

2003 Dec 08 46

EUROPEAN

PROJECTION

ISSUE DATE

00-01-19
03-02-20

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

15 SOLDERING

15.1 Introduction to soldering surface mount packages

Thistext gives averybrief insight toa complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for
certainsurface mount ICs,butit is notsuitablefor fine pitch
SMDs. In these situations reflow soldering is
recommended.

15.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuitboardby screenprinting,stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.

Typical reflow peak temperatures range from
215 to 270 °C depending on solder paste material. The
top-surface temperature of the packages should
preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free

process)
– for all BGA, HTSSON-T and SSOP-T packages
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a

volume ≥ 350 mm3 so called thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free

process) for packages with a thickness < 2.5 mm and a
volume < 350 mm3 so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.

15.3 Wave soldering

Conventional single wave soldering is not recommended
forsurface mount devices(SMDs)or printed-circuit boards

PNX3000

with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wavewith high upwardpressure followed bya
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackages with leadsonfour sides, thefootprintmust
be placedat a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time of the leads in the wave ranges from
3 to 4 seconds at 250 °C or 265 °C, depending on solder
material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

15.4 Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

2003 Dec 08 47

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

15.5 Suitability of surface mount IC packages for wave and reflow soldering methods

(1)

(3)

, TFBGA,

not suitable suitable

BGA, HTSSON..T

PACKAGE

(3)

, LBGA, LFBGA, SQFP, SSOP..T

USON, VFBGA
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,

not suitable

HTQFP, HTSSOP, HVQFN, HVSON, SMS

(5)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO, VSSOP not recommended
CWQCCN..L

(8)

, PMFP

(9)

, WQCCN..L

(8)

not suitable not suitable

Notes

1. Formore detailed informationon the BGApackages refer tothe

“(LF)BGAApplication Note

from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account
be processed through morethan one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature
must be kept as low as possible.

4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.

5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

6. Wave soldering is suitable for LQFP, TQFPand QFP packages with apitch (e) larger than 0.8 mm;it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted
on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar
soldering process. The appropriate soldering profile can be provided on request.

9. Hot bar or manual soldering is suitable for PMFP packages.

SOLDERING METHOD

WAVE REFLOW

(4)

(5)(6)
(7)

suitable

suitable
suitable

”(AN01026); order acopy

(2)

.

2003 Dec 08 48

Philips Semiconductors Preliminary specification

Analog front end for digital video

PNX3000

processors

16 DATA SHEET STATUS

LEVEL

I Objective data Development This data sheet contains data from the objective specification for product

II Preliminary data Qualification This data sheet contains data from the preliminary specification.

III Product data Production This data sheet contains data from the product specification. Philips

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

3. For data sheets describing multiple typenumbers, thehighest-level product status determines the data sheet status.

DATA SHEET

STATUS

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

(1)

PRODUCT

STATUS

(2)(3)

development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.

Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.

Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).

DEFINITION

17 DEFINITIONS Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition Limiting valuesgiven are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
atthese or atany other conditionsabovethose given inthe
Characteristics sectionsof the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentation or warrantythatsuchapplications will be
suitable for the specified use without further testing or
modification.

18 DISCLAIMERS Life support applications  These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expectedto resultin personalinjury. Philips
Semiconductorscustomers using orsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes  Philips Semiconductors
reserves the right to make changes in the products ­including circuits, standard cells, and/or software ­described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.

2003 Dec 08 49

Philips Semiconductors Preliminary specification

Analog front end for digital video
processors

19 PURCHASE OF PHILIPS I2C COMPONENTS

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components inthe I2C systemprovided the system conforms to the I2C specificationdefined by
Philips. This specification can be ordered using the code 9398 393 40011.

PNX3000

2003 Dec 08 50

Philips Semiconductors – a w orldwide compan y

Contact information

For additional information please visit http://www.semiconductors.philips.com. Fax: [phone]
For sales offices addresses send e-mail to: [e-mail].

© Koninklijke Philips Electronics N.V. 2003
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Printed in The Netherlands R24/01/pp51 Date of release: 2003 Dec 08 Document order number: 9397 750 11285

SCA75