Philips PNX2000 Service Manual

PNX2000

Audio video input processor

Rev. 01 – 04 May 2004 Preliminary data

1. General description

2. Features

The PNX2000 is a companion IC for use with the Nexperia™

entertainment engines such as PNX8526 and PNX8550.

The PNX2000 is always used in combination with the PNX3000. PNX2000 is intended for mid to high-end analog and h ybrid TV sets , performing input

decoding of single stream analog audio and single stream analog video signals. In addition, the PNX2000 is used for decoding and presentation of all audio output streams in the system.

■ Detection of PAL, NTSC or SECAM, and various 1fH and 2fH component video

input sources.

■ Full support for 1fH and 2fH video sources; progressive and interlaced.

■ Decoding for global VBI Standards (WST, WSS, VPS, CC, VITC).

■ ITU-656 output interface.

■ Global multi-standard audio demodulation and decoding.

■ Dolby Pro Logic II™ 2 multi-channel audio decoding and post-processing.

■ Advanced fully programmable audio post-processing functions, including

psychoacoustic spatial algorithms for optimal loudspeaker matching.

Figure 1 shows a block diagram of the device.

digital video home

3. Applications

■ Analog TV receivers.

■ Hybrid TV receivers.

■ DVD recorders.

■ VCRs.

1. Nexperia is a trademark of Koninklijke Philips Electronics N.V.

2. Dolby is a trademark of Dolby Laboratories

Philips Semiconductors



PNX2000

Audio video input processor

4. Ordering information

Table 1: Ordering information

Type numb er Package

Description Version

name

PNX2000HL LQFP144 plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm SOT486-1

5. Block diagram

DLINK2

DLINK1 DLINK3

C-bus

INT

13.5 MHz or 27 MHz

Xtal

6× I

S-bus

outputs

6× I

S-bus inputs

PNX2000

audio data SIF or L/R

I2C-BUS

GTU

CLOCKS

DEMDEC DSP

AUDIO DSP

×4

PNX3000

interface (2 stereo

or 4 mono)

video data CVBS, Y/C, YUV 54 MHz clock

I2D

×2×6

BCU

27 Msps or 54 Msps

PI-bus

VIDDEC

DCU

ITU-656

ITU-656

or 2f

10-bit data

HSYNC HSYNC/

VSYNC

mce559

H

Fig 1. Block diagram

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6. Pinning information

6.1 Pinning

PNX2000

Audio video input processor

Fig 2. Pin configuration

6.1.1 Pin description

Table 2 describes acronyms used in the pin tables:

Table 2: Acronym description

Acronym Description

3V 3.3 V LVCMOS 5VT 5 V tolerant inputs Z 3-state TTL TTL logic TTL-H TTL with hysteresis CMOS CMOS logic IA Input Analog ID Input Digital OD Output Digital OA Output Analog IOA I/O Analog IOD I/O Digital GA Ground Analog SA Supply Analog SD Supply Digital OSCIN Crystal Oscillator Input OSCOUT Cr ystal Oscillator Output OSCGND Crystal Oscillator Ground

144

PNX2000HL

109

108

001aaa28

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Table 3: I2D pins

Symbol Pin Type Description

DLINK1DP 2 IA analog differential data link 1 positive termination DLINK1DN 3 IA analog differential data link 1 negative termination DLINK1SP 4 IA analog differential strobe link 1 positive termination DLINK1SN 5 IA analog differential strobe link 1 negative termination DLINK2DP 7 IA analog differential data link 2 positive termination DLINK2DN 8 IA analog differential data link 2 negative termination DLINK2SP 9 IA analog differential strobe link 2 positive termination DLINK2SN 10 IA analog differential strobe link 2 negative termination DLINK3DP 12 IA analog differential data link 3 positive termination DLINK3DN 13 IA analog differential data link 3 negative termination DLINK3SP 14 IA analog differential strobe link 3 positive termination DLINK3SN 15 IA analog differential strobe link 3 negative termination

Table 4: Audio pins

Symbol Pin Type Description

ADAC1 104 OA digital audio output 1 ADAC2 107 OA digital audio output 2 ADAC3 110 OA digital audio output 3 ADAC4 113 OA digital audio output 4 ADAC5 116 OA digital audio output 5 ADAC6 119 OA digital audio output 6 ADAC7 122 OA digital audio output 7 ADAC8 125 OA digital audio output 8 ADAC9 128 OA digital audio output 9 ADAC10 131 OA digital audio output 10 ADAC11 134 OA digital audio output 11 ADAC12 137 OA digital audio output 12 ADAC1_P 103 SA Positiv e analog ref e rence derived via emitter f ollower from

ADAC1_N 105 GA Negative analog reference star connected at PNX3000. ADAC2_P 108 SA Positiv e analog ref e rence derived via emitter f ollower from

ADAC2_N 106 GA Negative analog reference star connected at PNX3000. ADAC3_P 109 SA Positiv e analog ref e rence derived via emitter f ollower from

ADAC3_N 111 GA Negative analog reference star connected at PNX3000. ADAC4_P 114 SA Positiv e analog ref e rence derived via emitter f ollower from

ADAC4_N 112 GA Negative analog reference star connected at PNX3000. ADAC5_P 115 SA Positiv e analog ref e rence derived via emitter f ollower from

ADAC5_N 117 GA Negative analog reference star connected at PNX3000.

PNX2000

Audio video input processor

PNX3000 V_SND pin.

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Table 4: Audio pins…continued

Symbol Pin Type Description

ADAC6_P 120 SA Positiv e analog ref e rence derived via emitter f ollower from

ADAC6_N 118 GA Negative analog reference star connected at PNX3000. ADAC7_P 121 SA Positiv e analog ref e rence derived via emitter f ollower from

ADAC7_N 123 GA Negative analog reference star connected at PNX3000. ADAC8_P 126 SA Positiv e analog ref e rence derived via emitter f ollower from

ADAC8_N 124 GA Negative analog reference star connected at PNX3000. ADAC9_P 127 SA Positiv e analog ref e rence derived via emitter f ollower from

ADAC9_N 129 GA Negative analog reference star connected at PNX3000. ADAC10_P 132 SA Positiv e analog reference derived via emitter follower from

ADAC10_N 130 GA Negative analog reference star connected at PNX3000. ADAC11_P 133 SA Positiv e analog reference derived via emitter follower from

ADAC11_N 135 GA Negative analog reference star connected at PNX3000. ADAC12_P 138 SA Positiv e analog reference derived via emitter follower from

ADAC12_N 136 GA Negative analog reference star connected at PNX3000.

PNX2000

Audio video input processor

PNX3000 V_SND pin.

Table 5: I2S-bus pins

Symbol Pin Type Description

I2S_IN_SD1 88 ID I2S-bus data in channel 1; TTL; 5VT I2S_IN_SD2 87 ID I2S-bus data in channel 2; TTL; 5VT I2S_IN_SD3 86 ID I2S-bus data in channel 3; TTL; 5VT I2S_IN_SD4 85 ID I2S-bus data in channel 4; TTL; 5VT I2S_IN_SD5 84 ID I2S-bus data in channel 5; TTL; 5VT I2S_IN_SD6 83 ID I2S-bus data in channel 6; TTL; 5VT I2S_OUT_SD1 77 OD I2S-bus data out channel 1; CMOS I2S_OUT_SD2 76 OD I2S-bus data out channel 2; CMOS I2S_OUT_SD4 75 OD I2S-bus data out channel 4; CMOS I2S_OUT_SD5 74 OD I2S-bus data out channel 5; CMOS I2S_OUT_SD6 73 OD I2S-bus data out channel 6; CMOS I2S_OUT_SD3_SCK 71 OD I2S-bus bit clock channel 3; CMOS I2S_OUT_SD3_WS 70 OD I2S-bus word select channel 3; CMOS I2S_OUT_SD3 69 OD I2S-bus data-out channel 3; CMOS I2S_SCK_SYS 79 IOD I2S-bus system bit clock; TTL-H; CMOS I2S_WS_SYS 78 IOD I2S-bus system word select; TTL-H; CMOS ADAC_CLK 89 OD Used for 128 fs or 256 fs clock output to external audio

DAC; CMOS.

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Table 6: VIDDEC pins

Symbol Pin Type Description

HVINFO 20 OD horizontal and vertical sync information to PNX3000; CMOS HSYNCFBL1 18 IA horizontal sync (external); fastblanking signal from SCART HSYNCFBL2 19 IA horizontal sync (external); fastblanking signal from SCART VSYNC1 21 ID vertical sync (external); TTL; 5VT VSYNC2 22 ID vertical sync (external); TTL; 5VT

Table 7: ITU-656 pins

Symbol Pin Type Description

DVO_DATA_0 55 OD digital video output state 0; CMOS; Z; 5VT DVO_DATA_1 56 OD digital video output state 1; CMOS; Z; 5VT DVO_DATA_2 57 OD digital video output state 2; CMOS; Z; 5VT DVO_DATA_3 58 OD digital video output state 3; CMOS; Z; 5VT DVO_DATA_4 60 OD digital video output state 4; CMOS; Z; 5VT DVO_DATA_5 61 OD digital video output state 5; CMOS; Z; 5VT DVO_DATA_6 62 OD digital video output state 6; CMOS; Z; 5VT DVO_DATA_7 63 OD digital video output state 7; CMOS; Z; 5VT DVO_DATA_8 64 OD digital video output state 8; CMOS; Z; 5VT DVO_DATA_9 65 OD digital video output state 9; CMOS; Z; 5VT DVO_VALID 52 OD digital video data valid; CMOS; Z; 5VT DVO_CLK 51 OD digital video output clock; CMOS; Z; 5VT LL_CLK 50 ID reserved; TTL; 5VT

PNX2000

Audio video input processor

[1]

[1] It is recommended to bias this pad with a 10 kΩ resistor

Table 8: JTAG pins

Symbol Pin Type Description

TDO 93 OD JT AG test data out; CMOS TDI 92 ID JTAG test data in; TTL-H; 5VT TCK 94 ID JTAG test clock; TTL-H; 5VT TRST_N TMS 95 ID JTAG test mode select; TTL-H; 5VT

[1] It is recommended to pull-down TRST_N with a 10 kΩ resistor. This ensures correct reset state of

Table 9: I2C-bus pins

Symbol Pin Type Description

I2C_SDA 27 IOD I2C-bus data; TTL; Z; 5VT I2C_SCL 26 IOD I2C-bus clock; TTL; Z; 5VT I2C_ADR 17 ID I2C-bus address select (internal pull-down); TTL; 5VT

[1]

96 ID JTAG reset (active low); TTL-H; 5VT

internal TAP circuitry and correct POR of the device within defined state machine.

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Table 10: Clock pins

Symbol Pin Type Description

MPIFCLK 31 OD 13.5 MHz or 27 MHz to PNX3000; CMOS DCLK 47 OD reserved; CMOS XIN 38 OSCIN crystal oscillator input XOUT 39 OSCOUT crystal oscillator output XGND 40 OSCGND crystal oscillator ground

Table 11: GTU pins

Symbol Pin Type Description

INTOUT 48 OD interrupt line output; Z; 5VT

Table 12: Reset pins

Symbol Pin Type Description

RESET_N 45 IA external reset input RESET_SEL 46 ID selects between using an external reset input or using

PNX2000

Audio video input processor

internal POR; TTL; 5VT HIGH = internal reset LOW = external reset

Table 13: Digital supply pins

Symbol Pin Type Description

DDE

32,49,66, 82,91,

- 3.3 V supply voltage

141,143

SSE

28,41,59, 72,99,

- 3.3 V ground

144

[1]

DDI

30,35,42, 53,67,

- 1.8 V supply voltage

80,97

29,36,43, 54,68,81,

- 1.8 V ground

98,139

[1]

DDM

SSD(I2D)

DDD(I2D)

SS(ADAC)

DDD(ADAC)

DD3(DTC)

DDD(DTC)

[1] V

44,140 - 1.8 V supply voltage for KSFRAMs and KROMs 1 GA I2D digital ground 16 SA I2D digital 1.8 V supply voltage 100 GD audio DAC 1.8 V digital ground 101 SD audio DAC 1.8 V digital supply voltage 23 SA DTC 3.3 V supply voltage 24 SA DTC 1.8 V supply voltage

DDI

and V

can be connected to same 1.8 V supply voltage.

DDM

Table 14: Analog supply pins

Symbol Pin Type Description

SSA(I2D)

DDA(I2D)

DDA(PLL)

6 GA I2D analog ground 11 SA I2D analog 1.8 V supply voltage 33 - phase locked loop 1.8 V supply voltage

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Table 14: Analog supply pins…continued

Symbol Pin Type Description

DDA(ADAC)

SS(DTC)

DDA(XTAL)

7. Functional description

7.1 Overview

Table 15 describes the functions of the hardware blocks (see also PNX2000 Block

Diagram Figure 1). For more detailed functional description refer to the PNX2000 User Manual.

Table 15: Block function

Function Block Description

High speed data link I2D Receives data in three streams from PNX3000. Video decoder

processor Serial interface I2C-bus To access all the internal registers. Global Task Unit GTU Generates all the internal clocks, reset and power

TV sound decoder DEMDEC

Audio processor AUDIO DSP Processing analog and digital audio sources. Data Capture Unit DCU Acquires VBI data (Telete xt; CC; VPS) and f ormats in a

Formatter unit ITU-656 Formats YUV, VBI data and CVBS data in ITU-656. Bus Control Unit BCU Bus arbitration among all the internal blocks.

Audio video input processor

102 SA audio DAC 3.3 V supply voltage 25 GA DTC analog ground 37 OSCVDD 1.8 V crystal oscillator supply voltage

VIDDEC Decodes and processes CVBS, YUV or Y/C in YUV

stream.

management. Demodulation, decoding of terrestrial TV aud io

DSP

standards .

stream.

PNX2000

7.2 Interfaces

Table 16: Interfaces

Interface Description

I2C-bus The PNX2000 IC is controlled using an I2C-bus. It performs like an I2C-bus to

PI-bus bridge, i.e. translates I commands.

I2D Receives data in three streams from PNX3000. I2S-bus Seria l digital audio interface (6 stereo inputs, 6 stereo outputs) for connection to

other devices that support the I2S-bus standard. Can be used to receive decoded sound from a multi-channel digital audio decoder, provide additional ADCs and DACs, or loop audio signals through an external processor or delay line.

ITU-656 Mainly intended to transfer output data stream externally to the PNX8550, but the

output data stream could also be readable by other ITU-656 input devices that implement data val id signalling.

DACS Digital-analog converters used to generate analog outputs from Sound Core.

Preliminary data Rev. 01 – 04 May 2004 8 of 26

C-bus slave received commands to PI-bus master

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