PNX2000
Audio video input processor
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Rev. 01 – 04 May 2004 |
Preliminary data |
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The PNX2000 is a companion IC for use with the Nexperia™ 1 digital video home entertainment engines such as PNX8526 and PNX8550.
The PNX2000 is always used in combination with the PNX3000.
PNX2000 is intended for mid to high-end analog and hybrid TV sets, performing input decoding of single stream analog audio and single stream analog video signals. In addition, the PNX2000 is used for decoding and presentation of all audio output streams in the system. Figure 1 shows a block diagram of the device.
■Detection of PAL, NTSC or SECAM, and various 1fH and 2fH component video input sources.
■Full support for 1fH and 2fH video sources; progressive and interlaced.
■Decoding for global VBI Standards (WST, WSS, VPS, CC, VITC).
■ITU-656 output interface.
■Global multi-standard audio demodulation and decoding.
■Dolby Pro Logic II™ 2 multi-channel audio decoding and post-processing.
■Advanced fully programmable audio post-processing functions, including psychoacoustic spatial algorithms for optimal loudspeaker matching.
■Analog TV receivers.
■Hybrid TV receivers.
■DVD recorders.
■VCRs.
1.Nexperia is a trademark of Koninklijke Philips Electronics N.V.
2.Dolby is a trademark of Dolby Laboratories
Philips Semiconductors |
PNX2000 |
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Audio video input processor |
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4. Ordering information |
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Table 1: Ordering information |
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Type number |
Package |
Description |
Version |
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name |
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PNX2000HL |
LQFP144 |
plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm |
SOT486-1 |
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DLINK2
DLINK1 DLINK3
PNX2000
audio data SIF or L/R
I2C-bus I2C-BUS
INT GTU
13.5 MHz or
27 MHz CLOCKS Xtal
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DEMDEC DSP |
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6× I2S-bus |
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outputs |
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AUDIO DSP |
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6× I2S-bus |
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×4 |
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×6 |
×2 |
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inputs |
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PNX3000 |
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interface |
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(2 stereo |
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or 4 mono) |
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video data CVBS, Y/C, YUV 54 MHz clock
27 Msps or 54 Msps
I2D
HSYNC
VIDDEC
HSYNC/
VSYNC
DCU
ITU-656
PI-bus
BCU
mce559
ITU-656
1fH or 2fH
10-bit data
Fig 1. Block diagram
9397 750 12066 |
© Koninklijke Philips Electronics N.V. 2004. All rights reserved. |
Preliminary data |
Rev. 01 – 04 May 2004 |
2 of 26 |
Philips Semiconductors |
PNX2000 |
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Audio video input processor |
144 |
109 |
1 |
108 |
PNX2000HL
36
37
72
73
001aaa287
Fig 2. Pin configuration
Table 2 describes acronyms used in the pin tables:
Table 2: |
Acronym description |
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Acronym |
Description |
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3V |
3.3 V LVCMOS |
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5VT |
5 V tolerant inputs |
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Z |
3-state |
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TTL |
TTL logic |
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TTL-H |
TTL with hysteresis |
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CMOS |
CMOS logic |
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IA |
Input Analog |
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ID |
Input Digital |
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OD |
Output Digital |
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OA |
Output Analog |
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IOA |
I/O Analog |
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IOD |
I/O Digital |
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GA |
Ground Analog |
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SA |
Supply Analog |
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SD |
Supply Digital |
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OSCIN |
Crystal Oscillator Input |
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OSCOUT |
Crystal Oscillator Output |
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OSCGND |
Crystal Oscillator Ground |
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9397 750 12066 |
© Koninklijke Philips Electronics N.V. 2004. All rights reserved. |
Preliminary data |
Rev. 01 – 04 May 2004 |
3 of 26 |
Philips Semiconductors |
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PNX2000 |
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Audio video input processor |
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Table 3: |
I2D pins |
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Symbol |
Pin |
Type |
Description |
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DLINK1DP |
2 |
IA |
analog differential data link 1 positive termination |
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DLINK1DN |
3 |
IA |
analog differential data link 1 negative termination |
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DLINK1SP |
4 |
IA |
analog differential strobe link 1 positive termination |
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DLINK1SN |
5 |
IA |
analog differential strobe link 1 negative termination |
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DLINK2DP |
7 |
IA |
analog differential data link 2 positive termination |
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DLINK2DN |
8 |
IA |
analog differential data link 2 negative termination |
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DLINK2SP |
9 |
IA |
analog differential strobe link 2 positive termination |
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DLINK2SN |
10 |
IA |
analog differential strobe link 2 negative termination |
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DLINK3DP |
12 |
IA |
analog differential data link 3 positive termination |
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DLINK3DN |
13 |
IA |
analog differential data link 3 negative termination |
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DLINK3SP |
14 |
IA |
analog differential strobe link 3 positive termination |
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DLINK3SN |
15 |
IA |
analog differential strobe link 3 negative termination |
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Table 4: |
Audio pins |
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Symbol |
Pin |
Type |
Description |
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ADAC1 |
104 |
OA |
digital audio output 1 |
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ADAC2 |
107 |
OA |
digital audio output 2 |
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ADAC3 |
110 |
OA |
digital audio output 3 |
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ADAC4 |
113 |
OA |
digital audio output 4 |
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ADAC5 |
116 |
OA |
digital audio output 5 |
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ADAC6 |
119 |
OA |
digital audio output 6 |
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ADAC7 |
122 |
OA |
digital audio output 7 |
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ADAC8 |
125 |
OA |
digital audio output 8 |
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ADAC9 |
128 |
OA |
digital audio output 9 |
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ADAC10 |
131 |
OA |
digital audio output 10 |
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ADAC11 |
134 |
OA |
digital audio output 11 |
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ADAC12 |
137 |
OA |
digital audio output 12 |
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ADAC1_P |
103 |
SA |
Positive analog reference derived via emitter follower from |
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PNX3000 V_SND pin. |
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ADAC1_N |
105 |
GA |
Negative analog reference star connected at PNX3000. |
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ADAC2_P |
108 |
SA |
Positive analog reference derived via emitter follower from |
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PNX3000 V_SND pin. |
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ADAC2_N |
106 |
GA |
Negative analog reference star connected at PNX3000. |
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ADAC3_P |
109 |
SA |
Positive analog reference derived via emitter follower from |
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PNX3000 V_SND pin. |
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ADAC3_N |
111 |
GA |
Negative analog reference star connected at PNX3000. |
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ADAC4_P |
114 |
SA |
Positive analog reference derived via emitter follower from |
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PNX3000 V_SND pin. |
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ADAC4_N |
112 |
GA |
Negative analog reference star connected at PNX3000. |
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ADAC5_P |
115 |
SA |
Positive analog reference derived via emitter follower from |
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PNX3000 V_SND pin. |
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ADAC5_N |
117 |
GA |
Negative analog reference star connected at PNX3000. |
9397 750 12066 |
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved. |
Preliminary data |
Rev. 01 – 04 May 2004 |
4 of 26 |
Philips Semiconductors |
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PNX2000 |
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Audio video input processor |
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Table 4: |
Audio pins…continued |
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Symbol |
Pin |
Type |
Description |
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ADAC6_P |
120 |
SA |
Positive analog reference derived via emitter follower from |
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PNX3000 V_SND pin. |
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ADAC6_N |
118 |
GA |
Negative analog reference star connected at PNX3000. |
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ADAC7_P |
121 |
SA |
Positive analog reference derived via emitter follower from |
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PNX3000 V_SND pin. |
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ADAC7_N |
123 |
GA |
Negative analog reference star connected at PNX3000. |
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ADAC8_P |
126 |
SA |
Positive analog reference derived via emitter follower from |
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PNX3000 V_SND pin. |
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ADAC8_N |
124 |
GA |
Negative analog reference star connected at PNX3000. |
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ADAC9_P |
127 |
SA |
Positive analog reference derived via emitter follower from |
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PNX3000 V_SND pin. |
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ADAC9_N |
129 |
GA |
Negative analog reference star connected at PNX3000. |
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ADAC10_P |
132 |
SA |
Positive analog reference derived via emitter follower from |
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PNX3000 V_SND pin. |
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ADAC10_N |
130 |
GA |
Negative analog reference star connected at PNX3000. |
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ADAC11_P |
133 |
SA |
Positive analog reference derived via emitter follower from |
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PNX3000 V_SND pin. |
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ADAC11_N |
135 |
GA |
Negative analog reference star connected at PNX3000. |
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ADAC12_P |
138 |
SA |
Positive analog reference derived via emitter follower from |
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PNX3000 V_SND pin. |
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ADAC12_N |
136 |
GA |
Negative analog reference star connected at PNX3000. |
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Table 5: |
I2S-bus pins |
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Symbol |
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Pin |
Type |
Description |
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I2S_IN_SD1 |
88 |
ID |
I2S-bus data in channel 1; TTL; 5VT |
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I2S_IN_SD2 |
87 |
ID |
I2S-bus data in channel 2; TTL; 5VT |
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I2S_IN_SD3 |
86 |
ID |
I2S-bus data in channel 3; TTL; 5VT |
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I2S_IN_SD4 |
85 |
ID |
I2S-bus data in channel 4; TTL; 5VT |
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I2S_IN_SD5 |
84 |
ID |
I2S-bus data in channel 5; TTL; 5VT |
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I2S_IN_SD6 |
83 |
ID |
I2S-bus data in channel 6; TTL; 5VT |
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I2S_OUT_SD1 |
77 |
OD |
I2S-bus data out channel 1; CMOS |
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I2S_OUT_SD2 |
76 |
OD |
I2S-bus data out channel 2; CMOS |
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I2S_OUT_SD4 |
75 |
OD |
I2S-bus data out channel 4; CMOS |
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I2S_OUT_SD5 |
74 |
OD |
I2S-bus data out channel 5; CMOS |
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I2S_OUT_SD6 |
73 |
OD |
I2S-bus data out channel 6; CMOS |
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I2S_OUT_SD3_SCK |
71 |
OD |
I2S-bus bit clock channel 3; CMOS |
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I2S_OUT_SD3_WS |
70 |
OD |
I2S-bus word select channel 3; CMOS |
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I2S_OUT_SD3 |
69 |
OD |
I2S-bus data-out channel 3; CMOS |
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I2S_SCK_SYS |
79 |
IOD |
I2S-bus system bit clock; TTL-H; CMOS |
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I2S_WS_SYS |
78 |
IOD |
I2S-bus system word select; TTL-H; CMOS |
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ADAC_CLK |
89 |
OD |
Used for 128 fs or 256 fs clock output to external audio |
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DAC; CMOS. |
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9397 750 12066 |
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved. |
Preliminary data |
Rev. 01 – 04 May 2004 |
5 of 26 |
Philips Semiconductors |
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PNX2000 |
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Audio video input processor |
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Table 6: |
VIDDEC pins |
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Symbol |
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Pin |
Type |
Description |
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HVINFO |
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20 |
OD |
horizontal and vertical sync information to PNX3000; CMOS |
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HSYNCFBL1 |
18 |
IA |
horizontal sync (external); fastblanking signal from SCART |
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HSYNCFBL2 |
19 |
IA |
horizontal sync (external); fastblanking signal from SCART |
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VSYNC1 |
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21 |
ID |
vertical sync (external); TTL; 5VT |
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VSYNC2 |
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22 |
ID |
vertical sync (external); TTL; 5VT |
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Table 7: |
ITU-656 pins |
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Symbol |
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Pin |
Type |
Description |
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DVO_DATA_0 |
55 |
OD |
digital video output state 0; CMOS; Z; 5VT |
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DVO_DATA_1 |
56 |
OD |
digital video output state 1; CMOS; Z; 5VT |
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DVO_DATA_2 |
57 |
OD |
digital video output state 2; CMOS; Z; 5VT |
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DVO_DATA_3 |
58 |
OD |
digital video output state 3; CMOS; Z; 5VT |
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DVO_DATA_4 |
60 |
OD |
digital video output state 4; CMOS; Z; 5VT |
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DVO_DATA_5 |
61 |
OD |
digital video output state 5; CMOS; Z; 5VT |
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DVO_DATA_6 |
62 |
OD |
digital video output state 6; CMOS; Z; 5VT |
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DVO_DATA_7 |
63 |
OD |
digital video output state 7; CMOS; Z; 5VT |
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DVO_DATA_8 |
64 |
OD |
digital video output state 8; CMOS; Z; 5VT |
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DVO_DATA_9 |
65 |
OD |
digital video output state 9; CMOS; Z; 5VT |
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DVO_VALID |
52 |
OD |
digital video data valid; CMOS; Z; 5VT |
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DVO_CLK |
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51 |
OD |
digital video output clock; CMOS; Z; 5VT |
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LL_CLK |
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50 |
ID |
reserved; TTL; 5VT[1] |
[1]It is recommended to bias this pad with a 10 kΩ resistor
Table 8: |
JTAG pins |
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Symbol |
Pin |
Type |
Description |
TDO |
93 |
OD |
JTAG test data out; CMOS |
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TDI |
92 |
ID |
JTAG test data in; TTL-H; 5VT |
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TCK |
94 |
ID |
JTAG test clock; TTL-H; 5VT |
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TRST_N[1] |
96 |
ID |
JTAG reset (active low); TTL-H; 5VT |
TMS |
95 |
ID |
JTAG test mode select; TTL-H; 5VT |
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[1]It is recommended to pull-down TRST_N with a 10 kΩ resistor. This ensures correct reset state of internal TAP circuitry and correct POR of the device within defined state machine.
Table 9: |
I2C-bus pins |
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Symbol |
Pin |
Type |
Description |
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I2C_SDA |
27 |
IOD |
I2C-bus data; TTL; Z; 5VT |
I2C_SCL |
26 |
IOD |
I2C-bus clock; TTL; Z; 5VT |
I2C_ADR |
17 |
ID |
I2C-bus address select (internal pull-down); TTL; 5VT |
9397 750 12066 |
© Koninklijke Philips Electronics N.V. 2004. All rights reserved. |
Preliminary data |
Rev. 01 – 04 May 2004 |
6 of 26 |
Philips Semiconductors |
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|
PNX2000 |
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Audio video input processor |
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Table 10: |
Clock pins |
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Symbol |
Pin |
Type |
Description |
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MPIFCLK |
31 |
OD |
13.5 MHz or 27 MHz to PNX3000; CMOS |
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DCLK |
47 |
OD |
reserved; CMOS |
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XIN |
38 |
OSCIN |
crystal oscillator input |
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XOUT |
39 |
OSCOUT |
crystal oscillator output |
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XGND |
40 |
OSCGND |
crystal oscillator ground |
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Table 11: |
GTU pins |
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Symbol |
Pin |
Type |
Description |
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INTOUT |
48 |
OD |
interrupt line output; Z; 5VT |
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Table 12: |
Reset pins |
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Symbol |
Pin |
Type |
Description |
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RESET_N |
45 |
IA |
external reset input |
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RESET_SEL 46 |
ID |
selects between using an external reset input or using |
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internal POR; TTL; 5VT |
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HIGH = internal reset |
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LOW = external reset |
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Table 13: Digital supply pins |
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Symbol |
Pin |
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Type |
Description |
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VDDE |
32,49,66, 82,91, |
- |
3.3 V supply voltage |
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141,143 |
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VSSE |
28,41,59, 72,99, |
- |
3.3 V ground |
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144 |
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VDDI [1] |
30,35,42, 53,67, |
- |
1.8 V supply voltage |
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80,97 |
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VSS |
29,36,43, 54,68,81, |
- |
1.8 V ground |
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98,139 |
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VDDM [1] |
44,140 |
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- |
1.8 V supply voltage for KSFRAMs and KROMs |
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VSSD(I2D) |
1 |
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GA |
I2D digital ground |
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VDDD(I2D) |
16 |
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SA |
I2D digital 1.8 V supply voltage |
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VSS(ADAC) |
100 |
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GD |
audio DAC 1.8 V digital ground |
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VDDD(ADAC) |
101 |
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SD |
audio DAC 1.8 V digital supply voltage |
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VDD3(DTC) |
23 |
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SA |
DTC 3.3 V supply voltage |
|
VDDD(DTC) |
24 |
|
SA |
DTC 1.8 V supply voltage |
[1]VDDI and VDDM can be connected to same 1.8 V supply voltage.
Table 14: Analog supply pins
|
Symbol |
Pin |
Type |
Description |
|
|
|
|
|
|
VSSA(I2D) |
6 |
GA |
I2D analog ground |
|
VDDA(I2D) |
11 |
SA |
I2D analog 1.8 V supply voltage |
|
VDDA(PLL) |
33 |
- |
phase locked loop 1.8 V supply voltage |
9397 750 12066 |
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved. |
Preliminary data |
Rev. 01 – 04 May 2004 |
7 of 26 |
Philips Semiconductors |
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PNX2000 |
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Audio video input processor |
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Table 14: Analog supply pins…continued |
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|
Symbol |
Pin |
Type |
Description |
|
|
|
|
|
|
VDDA(ADAC) |
102 |
SA |
audio DAC 3.3 V supply voltage |
|
VSS(DTC) |
25 |
GA |
DTC analog ground |
|
VDDA(XTAL) |
37 |
OSCVDD |
1.8 V crystal oscillator supply voltage |
Table 15 describes the functions of the hardware blocks (see also PNX2000 Block
Diagram Figure 1).
For more detailed functional description refer to the PNX2000 User Manual.
Table 15: Block function
Function |
Block |
Description |
High speed data link |
I2D |
Receives data in three streams from PNX3000. |
Video decoder |
VIDDEC |
Decodes and processes CVBS, YUV or Y/C in YUV |
processor |
|
stream. |
|
|
|
Serial interface |
I2C-bus |
To access all the internal registers. |
Global Task Unit |
GTU |
Generates all the internal clocks, reset and power |
|
|
management. |
|
|
|
TV sound decoder |
DEMDEC |
Demodulation, decoding of terrestrial TV audio |
|
DSP |
standards . |
|
|
|
Audio processor |
AUDIO DSP |
Processing analog and digital audio sources. |
|
|
|
Data Capture Unit |
DCU |
Acquires VBI data (Teletext; CC; VPS) and formats in a |
|
|
stream. |
|
|
|
Formatter unit |
ITU-656 |
Formats YUV, VBI data and CVBS data in ITU-656. |
|
|
|
Bus Control Unit |
BCU |
Bus arbitration among all the internal blocks. |
|
|
|
|
Table 16: |
Interfaces |
|
Interface |
Description |
|
I2C-bus |
The PNX2000 IC is controlled using an I2C-bus. It performs like an I2C-bus to |
|
|
PI-bus bridge, i.e. translates I2C-bus slave received commands to PI-bus master |
|
|
commands. |
|
|
|
|
I2D |
Receives data in three streams from PNX3000. |
|
I2S-bus |
Serial digital audio interface (6 stereo inputs, 6 stereo outputs) for connection to |
|
|
other devices that support the I2S-bus standard. Can be used to receive decoded |
|
|
sound from a multi-channel digital audio decoder, provide additional ADCs and |
|
|
DACs, or loop audio signals through an external processor or delay line. |
|
|
|
|
ITU-656 |
Mainly intended to transfer output data stream externally to the PNX8550, but the |
|
|
output data stream could also be readable by other ITU-656 input devices that |
|
|
implement data valid signalling. |
|
|
|
|
DACS |
Digital-analog converters used to generate analog outputs from Sound Core. |
|
|
|
9397 750 12066 |
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved. |
Preliminary data |
Rev. 01 – 04 May 2004 |
8 of 26 |