Philips PMV45EN User Manual

PMV45EN

μTrenchMOS™ enhanced logic level FET

Rev. 01 — 15 January 2003

Product data

M3D088

1.Product profile

1.1Description

N-channel enhancement mode field-effect transistor in a plastic package using

TrenchMOS™ technology.

Product availability:

PMV45EN in SOT23.

1.2	Features
	■ Surface mount package	■ Fast switching.
1.3	Applications
	■ Battery management	■ High speed switch.
1.4	Quick reference data
	■ VDS ≤ 30 V	■ ID ≤ 5.4 A
	■ Ptot ≤ 2 W	■ RDSon ≤ 42 mΩ

2. Pinning information

Table 1:

Pinning - SOT23 simplified outline and symbol

Pin

Description

Simplified outline

Symbol

1

gate (g)

3

d

2

source (s)

3

drain (d)

g

1

2

MBB076

s

Top view

MSB003

SOT23

Philips Semiconductors	PMV45EN
	μTrenchMOS™ enhanced logic level FET

3. Limiting values

Table 2: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol	Parameter	Conditions		Min	Max	Unit
VDS	drain-source voltage (DC)	25 °C ≤ Tj ≤ 150 °C		-	30	V
VDGR	drain-gate voltage (DC)	25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ		-	30	V
VGS	gate-source voltage (DC)			-	±20	V
ID	drain current (DC)	Tsp = 25 °C; VGS = 10 V; Figure 2 and 3		-	5.4	A
		Tsp = 100 °C; VGS = 10 V; Figure 2		-	3.4	A
IDM	peak drain current	Tsp = 25	°C; pulsed; tp ≤ 10 μs; Figure 3	-	21.6	A
Ptot	total power dissipation	Tsp = 25	°C; Figure 1	-	2	W
Tstg	storage temperature			−55	+150	°C
Tj	junction temperature			−55	+150	°C
Source-drain diode
IS	source (diode forward) current (DC)	Tsp = 25	°C	-	1.7	A
ISM	peak source (diode forward) current	Tsp = 25	°C; pulsed; tp ≤ 10 μs	-	6.9	A

9397 750 10894

© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Product data

Rev. 01 — 15 January 2003

2 of 12

Philips Semiconductors	PMV45EN
	μTrenchMOS™ enhanced logic level FET

120							03aa17
Pder
(%)
	80
	40
	0
		0		50	100	150	200
							Tsp (°C)
P		=	Ptot		× 100%
	der		----------------------
			P	°C )
			tot (25

Fig 1. Normalized total power dissipation as a function of solder point temperature.

120					03aa25
Ider
(%)
80
40
0
	0	50	100	150	200
					Tsp (°C)
I der		I D
	= ------------------- × 100%
		I D(25°C )

Fig 2. Normalized continuous drain current as a function of solder point temperature.

102						03al02
ID
(A)	Limit RDSon = VDS/ID
10				tp = 10 μ s
				100 μ s
1				1 ms
		DC		10 ms
10-1				100 ms
10-2
10-1	1		10	VDS	(V)	102

Tsp = 25 °C; IDM is single pulse; VGS = 10 V

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

9397 750 10894

© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Product data

Rev. 01 — 15 January 2003

3 of 12

Philips Semiconductors			PMV45EN
			μTrenchMOS™ enhanced logic level FET
4. Thermal characteristics
Table 3:	Thermal characteristics
Symbol	Parameter	Conditions	Min	Typ	Max	Unit
Rth(j-sp)	thermal resistance from junction to solder point	Figure 4	-	-	60	K/W

4.1 Transient thermal impedance

102							03ak68
Zth(j-sp)
(K/W)	δ = 0.5
	0.2
10
	0.1
	0.05				P		tp
						δ = T
	0.02
	single pulse				tp	T	t
1
10-4		10-3	10-2	10-1	1	tp (s)	10

Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.

9397 750 10894

© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Product data

Rev. 01 — 15 January 2003

4 of 12