Philips PLUS405-55A Datasheet

Philips Semiconductors Programmable Logic Devices Product specification

PLUS405-55

Programmable logic sequencer (16 × 64 × 8)

180

October 22, 1993 853–1546 11164

DESCRIPTION

The PLUS405-55 device is a bipolar, programmable state machine of the Mealy type. Both the AND and the OR array are user-programmable. All 64 AND gates are connected to the 16 external dedicated inputs (I0 - I15) and to the feedback paths of the 8 on-chip State Registers (Q

- QP7). Two complement arrays support complex IF-THEN-ELSE state transitions with a single product term (input variables C

, C

1).

All state transition terms can include True, False and Don’t Care states of the controlling state variables. All AND gates are merged into the programmable OR array to issue the next-state and next-output commands to their respective registers. Because the OR array is programmable, any one or all of the 64 transition terms can be connected to any or all of the State and Output Registers.

All state (Q

- QP7) and output (QF0 - QF7) registers are edge-triggered, clocked J-K flip-flops, with Asynchronous Preset and Reset options. The PLUS405 architecture provides the added flexibility of the J-K toggle function which is indeterminate on S-R flip-flops. Each register may be individually programmed such that a specific Preset-Reset pattern is initialized when the initialization pin is raised to a logic level “1”. This feature allows the state machine to be asynchronously initialized to known internal state and output conditions prior to proceeding through a sequence of state transitions. Upon power-up, all registers are unconditionally preset to “1”. If desired, the initialization input pin (INIT) can be converted to an Output Enable

(OE) function as an

additional user-programmable feature. Availability of two user-programmable clocks

allows the user to design two independently clocked state machine functions consisting of four state and four output bits each.

Order codes are listed in the Ordering Information Table below.

FEATURES

•66.7MHz minimum guaranteed clock rate

•55MHz minimum guaranteed operating

frequency (1/(t

IS1

+ t

CKO1

)

•Functional superset of PLS105/105A

•Field-programmable (Ti-W fusible link)

•16 input variables

•8 output functions

•64 transition terms

•8-bit State Register

•8-bit Output Register

•2 transition Complement Arrays

•Multiple clocks

•Programmable Asynchronous Initialization

or Output Enable

•Power-on preset of all registers to “1”

•“On-chip” diagnostic test mode features for

access to state and output registers

•950mW power dissipation (typ.)

•TTL compatible

•J-K or S-R flip-flop functions

•Automatic “Hold” states

•3-State outputs

APPLICATIONS

•Interface protocols

•Sequence detectors

•Peripheral controllers

•Timing generators

•Sequential circuits

•Elevator contollers

•Security locking systems

•Counters

•Shift registers

PIN CONFIGURATIONS

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15

N Package

4 5 6 7 8 9

10 11

12 13 14 15 16 17

2627

CLK

I7 I6

I5/CLK

I4 I3 I2 I1

I0 F7 F6 F5 F4

GND F3

INIT/OE

I15

I14

I13

I12

I11

I10

CLKI6 I7

I5/CLK

I8 I9

I4 I3 I2 I1

I0 F7 F6

F5 F4 GND F3 F2 F1 F0

INIT/OE

I15

I14

I13

I12

I11

I10

N = Plastic DIP (600mil-wide)

A = Plastic Leaded Chip Carrier

A Package

ORDERING INFORMATION

DESCRIPTION

OPERATING

FREQUENCY

ORDER CODE DRAWING NUMBER

28-Pin Plastic Dual In-Line (600mil-wide) 55MHz (tIS + t

CKO

) PLUS405–55N 0413B

28-Pin Plastic Leaded Chip Carrier 55MHz (tIS + t

CKO

) PLUS405–55A 0401F

Philips Semiconductors Programmable Logic Devices Product specification

PLUS405-55

Programmable logic sequencer (16 × 64 × 8)

October 22, 1993

181

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION POLARITY

1 CLK1 Clock: The Clock input to the State and Output Registers. A Low-to-High transition on this

line is necessary to update the contents of both state and output registers. Pin 1 only clocks P0–3 and F0–3 if Pin 4 is also being used as a clock.

Active-High (H)

2, 3, 5–9,

26–27 20–22

I0 – I4, I7, I6

I8 – I9

I13 – I15

Logic Inputs: The 12 external inputs to the AND array used to program jump conditions between machine states, as determined by a given logic sequence. True and complement signals are generated via use of “H” and “L”.

Active-High/Low

(H/L)

4 CLK2 Logic Input/Clock: A user programmable function:

• Logic Input: A 13th external logic input to the AND array , as above.

Active-High/Low

(H/L)

• Clock: A 2nd clock for the State Registers P4–7 and Output Registers F4–7, as above.

Note that input buffer I5 must be deleted from the AND array (i.e., all fuse locations “Don’t Care”) when using Pin 4 as a Clock.

Active-High (H)

23 I12 Logic/Diagnostic Input: A 14th external logic input to the AND array, as above, when

exercising standard TTL or CMOS levels. When I12 is held at +10V , device outputs F0–F7 reflect the contents of State Register bits P0–P7. The contents of each Output Register remains unaltered.

Active-High/Low

(H/L)

24 I11 Logic/Diagnostic Input: A 15th external logic input to the AND array, as above, when

exercising standard TTL levels. When I11 is held at +10V, device outputs F0–F7 become direct inputs for State Register bits P0–P7; a Low-to-High transition on the appropriate clock line loads the values on pins F0–F7 into the State Register bits P0–P7. The contents of each Output Register remains unaltered.

Active-High/Low

(H/L)

25 I10 Logic/Diagnostic Input: A 16th external logic input to the AND array, as above, when

exercising standard TTL levels. When I10 is held at +10V , device outputs F0–F7 become direct inputs for Output Register bits Q0–Q7; a Low-to-High transition on the appropriate clock line loads the values on pins F0–F7 into the Output Register bits Q0–Q7. The contents of each State Register remains unaltered.

Active-High/Low

(H/L)

10–13 15–18

F0 – F7 Logic Outputs/Diagnostic Outputs/Diagnostic Inputs: Eight device outputs which

normally reflect the contents of Output Register Bits Q0–Q7, when enabled. When I12 is held at +10V, F0–F7 = (P0–P7). When I11 is held at +10V, F0–F7 become inputs to State Register bits P0–P7. When I10 is held at +10V , F0–F7 become inputs to Output Register bits Q0–Q7.

Active-High (H)

19 INIT/OE Initialization or Output Enable Input: A user programmable function:

• Initialization: Provides an asynchronous preset to logic “1” or reset to logic “0” of all

State and Output Register bits, determined individually for each register bit through user programming. INIT overrides Clock, and when held High, clocking is inhibited and F0–F7 and P0–P7 are in their initialization state. Normal clocking resumes with the first full clock pulse following a High-to-Low clock transition, after INIT goes Low. See timing definition for t

NVCK

and t

VCK

Active-High (H)

• Output Enable: Provides an output enable function to buffers F0–F7 from the Output

Registers.

Active-Low (L)

Philips Semiconductors Programmable Logic Devices Product specification

PLUS405-55

Programmable logic sequencer (16 × 64 × 8)

October 22, 1993

182

TRUTH TABLE

1, 2, 3, 4, 5, 6, 7

OPTION

INIT OE I10 I11 I12 CK J K Q

H * * * X X X H/L H/L Q

L +10V X X

↑

X X Q

L L

L +10V X X

↑

X X Q

H H

L X +10V X

↑

X X L Q

L X +10V X

↑

X X H Q

L X X +10V X X X Q

L X X X X X X Q

H X X * X X X Q

Hi-Z

+5V X +10V X X

↑

X X Q

L L

X +10V X X

↑

X X Q

H H

X X +10V X

↑

X X L Q

X X +10V X

↑

X X H Q

L X X +10V X X X Q

L X X X X X X Q

L X X X

↑

L L Q

L X X X

↑

L H L L L

L X X X

↑

H L H H H

L X X X

↑

H H Q

↑

X X X X X X X X H H

NOTES:

1. Positive Logic: S/R (or J/K) = T0 + T1 + T2 + . . . T

Tn = (C0, C1) (I0, I1, I2, . . .) (P0, P1, . . . P7)

2. Either Initialization (Active-High) or Output

Enable (Active-Low) are available, but not both. The desired function is a user-programmable

option.

3. ↑ denotes transition from Low-to-High level.

4. * = H or L or +10V

5. X = Don’t Care (<

5.5V)

6. H/L implies that either a High or a Low can occur, depending upon user-programmed selection (each State and Output Register individually programmable).

7. When using the F

pins as inputs to the State and Output Registers in diagnostic mode, the F buffers are 3-Stated and the indicated levels

on the output pins are forced by the user.

VIRGIN STATE

A factory-shipped virgin device contains all fusible links intact, such that:

1. INIT/OE

is set to INIT. In order to use the INIT function, the user must select either the PRESET or the RESET option for each flip-flop. Note that regardless of the user-programmed initialization, or even if the INIT function is not used, all registers are preset to “1” by the power-up procedure.

2. All transition terms are inactive (0).

3. All S/R (or J/K) flip-flop inputs are disabled (0).

4. The device can be clocked via a Test Array preprogrammed with a standard test pattern.

5. Clock 2 is inactive.

LOGIC FUNCTION

0 1 0

0 0 1

STATE REGISTER

n + 1

PRESENT STATE

⋅ B ⋅ C ⋅ . . .

NEXT STATE

Q2 Q1 Q0

SET Q

: J0 = (Q

⋅ Q1 ⋅ Q0) ⋅ A ⋅ B ⋅ C . . .

= 0

RESET Q

: J1 = 0

= (Q

⋅ Q2 ⋅ Q1 ⋅ Q0) ⋅ A ⋅ B ⋅ C . . .

HOLD Q

: J2 = 0

= 0

RESET Q

: J3 = (Q

⋅ Q2 ⋅ Q1 ⋅ Q0) ⋅ A ⋅ B ⋅ C . . .

= (Q

⋅ Q2 ⋅ Q1 ⋅ Q0) ⋅ A ⋅ B ⋅ C . . .

Philips Semiconductors Programmable Logic Devices Product specification

PLUS405-55

Programmable logic sequencer (16 × 64 × 8)

October 22, 1993

183

FUNCTIONAL DIAGRAM

P63 P0

I/CLK

P R

(4)

P R

(4)

P R

(4)

P R

(4)

INIT/OE

Philips Semiconductors Programmable Logic Devices Product specification

PLUS405-55

Programmable logic sequencer (16 × 64 × 8)

October 22, 1993

184

LOGIC DIAGRAM

DETAIL A

DETAIL B

DETAIL C

DETAIL D

9 8 7 6 5

3 2

27 26 25 24 23 22 21 20

I0 I1 I2 I3 I4

I6 I7 I8

I9 I10 I11 I12 I13 I14 I15

I5/CLK

INIT/OE

CLK

NOTE:

Denotes a programmable fuse location.

+ 11 hidden pages