Philips PCK953BD Datasheet
INTEGRATED CIRCUITS
PCK953
50–125 MHz PECL input/9 CMOS output
3.3 V PLL clock driver
Product specification
Supersedes data of 2000 Oct 25
ICL03 — PC Motherboard ICs; Logic Products
Group
2001 Feb 08
Philips Semiconductors Product specification
50–125 MHz PECL input/CMOS output
3.3 V PLL clock driver
DESCRIPTION
The PCK953 is a 3.3 V compatible, PLL-based clock driver device
targeted for high performance clock tree designs. With output
frequencies of up to 125 MHz, and output skews of 100 ps, the
PCK953 is ideal for the most demanding clock tree designs. The
devices employ a fully differential PLL design to minimize
cycle-to-cycle and phase jitter.
The PCK953 has a differential LVPECL reference input, along with
an external feedback input. These features make the PCK953 ideal
for use as a zero delay, low skew fanout buffer. The device
performance has been tuned and optimized for zero delay
performance. The MR/OE
and 3-State the output buffers when driven HIGH.
The PCK953 is fully 3.3 V compatible and requires no external loop
filter components. All control inputs accept LVCMOS or LVTTL
compatible levels, while the outputs provide LVCMOS levels with the
ability to drive terminated 50 Ω transmission lines. For series
terminated 50 Ω lines, each of the PCK953 outputs can drive two
traces, giving the device an effective fanout of 1:18. The device is
packaged in a 7 × 7 mm 32-lead LQFP package to provide the
optimum combination of board density and performance.
FEA TURES
•Fully integrated PLL
•Output frequency up to 125 MHz in PLL mode
•Outputs disable in high impedance
•LQFP packaging
•55 ps cycle-to-cycle jitter typical
•9 mA quiescent current, I
•60 ps static phase offset typical
•Less than 10 µA quiescent current, l
input pin will reset the internal counters
, typical
CCA
, typical
CCO
PIN CONFIGURATION
VCO_SEL
BYPASS
32
31
1
V
CCA
FB_CLK
NC
NC
NC
NC
GNDI
2
3
4
5
6
7
8PECL_CLK
9
10
MR/OE
PECL_CLK
PLL_EN
30
11
CCO
V
GNDO
29
12
Q7
QFB
28
13
GNDO
CCO
V
27
14
Q6
PCK953
Q0
GNDO
26
25
24
23
22
21
20
19
18
17 GNDO
15
16
Q5
CCO
V
SW00625
Q1
V
CCO
Q2
GNDO
Q3
V
CCO
Q4
ORDERING INFORMA TION
PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER
plastic low profile quad flat
package; 32 leads
0 to +70°C PCK953BD SOT358-1
LOGIC DIAGRAM
QFB
PECL_CLK
PECL_CLK
FB_CLK
VCO_SEL
BYPASS
MR/OE
PLL_EN
2001 Feb 08 853–2222 25600
PHASE
DETECTOR
LPF
VCO
200–500 MHz
2
B2
B4
7
Q0:6
Q7
SW00624
Philips Semiconductors Product specification
50–125 MHz PECL input/CMOS output
3.3 V PLL clock driver
FUNCTION TABLE
BYPASS Function
1
0
MR/OE Function
1
0
VCO_SEL Function
1
0
PLL_EN Function
1
0
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
V
I
IN
T
stg
NOTE:
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability . Functional operation under absolute-maximum-rated co nditions is
not implied.
Supply voltage –0.3 4.6 V
Input voltage –0.3 VDD+0.3 V
I
Input current — ±20 mA
Storage temperature range –40 +125 °C
PLL Enabled
PLL Bypass
Outputs Disabled
Outputs Enabled
B2
B1
Select VCO
Select PECL_CLK
1
PARAMETER MIN MAX UNIT
PCK953
2001 Feb 08
3
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