Philips pck857 DATASHEETS

INTEGRATED CIRCUITS

PCK857

50–150MHz differential 1:10 SDRAM clock driver

Product specification Supersedes data of 1998 Dec 10

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2000 June 15

Philips Semiconductors Product specification

50–150 MHz differential 1:10 SDRAM clock driver

FEA TURES

•Optimized for clock distribution in DDR (Double Data Rate)

SDRAM applications

•1-to-10 differential clock distribution

•Very low skew (< 100 ps) and jitter (< 100 ps)

•3 V AV

and 2.5 V V

•SSTL_2 interface clock inputs and outputs

•CMOS control signal input

•Test mode enables buffers while disabling PLL

•Low current power-down mode

•Tolerant of Spread Spectrum input clock

•Full DDR solution provided when used with SSTL16857 and

CBT3857

DESCRIPTION

Zero delay buffer to distribute an SSTL differential clock input pair to 10 SSTL_2 differential output pairs. Outputs are slope controlled. External feedback pin for synchronization of the outputs to the input. A CMOS style Enable/Disable pin is provided for low power disable.

PIN CONFIGURATION

GND

GND GND

V V

CLK CLK

AGND

GND

PCK857

8 9

13 14

15 16

17 18

23 24

48 47 46

45 44

43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

GND Y

GND GND

G FBIN FBIN

FBOUT FBOUT GND

GND

SW00358

ORDERING INFORMA TION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DRAWING NUMBER

48-Pin Plastic TSSOP 0°C to +85°C PCK857 DGG PCK857 DGG SOT362-1

2000 June 15 853-2199 23880

Philips Semiconductors Product specification

50–150 MHz differential 1:10 SDRAM clock driver

PIN DESCRIPTION

PINS SYMBOL I/O DESCRIPTION

17 AGND Ground Analog ground. AGND provides the ground reference for the analog

13, 14 CLK, CLK I Clock input. CLK provides the clock signal to be distributed by the

36, 35 FBIN, FB

32, 33 FB

37 G I Output bank enable. G is the output enable for outputs Y and Y. When

1, 7, 8, 18, 24, 25, 31, 41,

42, 48

4, 11, 12, 15, 21, 28, 34,

38, 45

3, 5, 10, 20, 22, 46, 44, 39,

29, 27

2, 6, 9, 19, 23, 47, 43, 40,

30, 26

, FB

OUT

GND Ground Ground

Y0, Y1, Y2, Y3, Y4, Y5,

Y6, Y7, Y8, Y9

Y0, Y1, Y2, Y3, Y4, Y5,

Y6, Y7, Y8, Y9

Power

Power Power supply

circuitry. Analog power supply. AVCC provides the power reference for the analog

circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. During disable (G = 0), the PLL is powered down.

PCK857 clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal.

I Feedback input. FBIN provides the feedback signal to the internal PLL.

FBIN must be hard-wired to FB PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN.

O Feedback output. FB

at the same frequency as CLK. When externally wired to FBIN, FB completes the feedback loop of the PLL.

G is low outputs Y are disabled to a high-impedance state. When G is high, all outputs Y are enabled and switch at the same frequency as CLK.

O Clock outputs. These outputs provide low-skew copies of CLK.

PCK857

to complete the PLL. The integrated

OUT

is dedicated for external feedback. It switches

OUT

FUNCTION TABLE

INPUTS OUTPUTS PLL ON/OFF

G CLK CLK Y Y FBOUT FBOUT

L L H Z Z Z L H L Z Z Z

1 1

H L H L H L H ON H H L H L H L ON

< 20 MHz < 20 MHz Z Z Z

NOTES:

H = HIGH voltage level L = LOW voltage level Z = high impedance OFF-state X = don’t care

1. Subject to change. May cause conflict with FBIN pins.

2. Additional feature that senses when the clock input is less than 20 MHz and places the part in sleep mode.

2000 June 15

OFF OFF

OFF

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