Philips PCK857 Datasheet
INTEGRATED CIRCUITS
PCK857
66–150MHz Phase Locked Loop
Differential 1:10 SDRAM Clock Driver
Preliminary specification 1998 Dec 10
Philips Semiconductors Preliminary specification
66–150MHz Phase Locked Loop Differential 1:10
SDRAM Clock Driver
FEATURES
•Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications
•1-to-10 differential clock distribution
•Very low skew (< 100ps) and jitter (< 100ps)
•3V AV
and 2.5V V
CC
ddq
•SSTL_2 interface clock inputs and outputs
•CMOS control signal input
•Test mode enables buffers while disabling PLL
•Low current power-down mode
•Tolerant of Spread Spectrum input clock
•Full DDR solution provided when used with SSTL16857 and
CBT3857
DESCRIPTION
Zero delay buffer to distribute an SSTL differential clock input pair to
10 SSTL_2 differential output pairs. Outputs are slope controlled.
External feedback pin for synchronization of the outputs to the input.
A CMOS style Enable/Disable pin is provided for low power disable.
PIN CONFIGURATION
GND
V
DDQ
GND
GND
V
DDQ
V
DDQ
CLK
CLK
V
DDQ
AV
CC
AGND
GND
V
DDQ
GND
PCK857
1
Y
2
0
Y
3
0
4
Y
5
1
Y
6
1
7
8
9
Y
2
Y
10
2
11
12
13
14
15
16
17
18
Y
19
3
Y
20
3
21
Y
22
4
Y
4
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
Y
5
Y
5
V
DDQ
Y
6
Y
6
GND
GND
Y
7
Y
7
V
DDQ
G
FBIN
FBIN
V
DDQ
FBOUT
FBOUT
GND
Y
8
Y
8
V
DDQ
Y
9
Y
9
GND
SW00358
ORDERING INFORMA TION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DRAWING NUMBER
48-Pin Plastic TSSOP 0°C to +70°C PCK857 DGG PCK857 DGG SOT362-1
PINS SYMBOL DESCRIPTION
1, 7, 8, 18, 24, 25, 31, 41, 42, 48 GND SSTL_2 ground pins
2, 3, 5, 6, 9, 10, 19, 20, 22, 23, 26, 27, 29,
30, 32, 33, 39, 40, 43, 44, 46, 47
4, 11, 12, 15, 21, 28, 34 V
13, 14, 35, 36 CLKIN, CLK
16 AV
17 AGND Analog ground
37 G Power-down control input
Yn, Ynb, FB
OUT
DDQ
, FBIN, FB
INb
CC
, FB
OUTb
INb
SSTL_2 differential outputs
SSTL_2 power pins
SSTL_2 differential inputs
Analog power
1998 Dec 10
2
Philips Semiconductors Preliminary specification
66–150MHz Phase Locked Loop Differential 1:10
SDRAM Clock Driver
FUNCTION TABLE
INPUTS OUTPUTS PLL ON/OFF
G CLK CLK Y Y FBOUT FBOUT
L L H Z Z Z
L H L Z Z Z
1
1
H L H L H L H ON
H H L H L H L ON
2
X
< 20MHz < 20MHz Z Z Z
1
NOTES:
H = HIGH voltage level
L = LOW voltage level
Z = high impedance OFF-state
X = don’t care
1. Subject to change. May cause conflict with FBIN pins.
2. Additional feature that senses when the clock input is less than 20MHz and places the part in sleep mode.
BLOCK DIAGRAM
CLK
CLK/
FB
FBIN/
AV
G/
PLL
IN
CC
Y
0
Y0/
Y
1
Y1/
Y
2
Y2/
Y
3
Y3/
Y
4
Y4/
Y
5
Y5/
Y
6
Y6/
Y
7
Y7/
Y
8
Y8/
Y
9
Y9/
FB
OUT
FB
OUT
SW00395
/
1
Z
1
Z
1
Z
PCK857
OFF
OFF
OFF
1998 Dec 10
3
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