Philips PCK2510SLDH Datasheet
INTEGRATED CIRCUITS
PCK2510SL
50–150 MHz 1:10 SDRAM clock driver
Product specification
ICL03 — PC Motherboard ICs; Logic Products Group
2000 Dec 01
Philips Semiconductors Product specification
PCK2510SL50–150 MHz 1:10 SDRAM clock driver
FEA TURES
•Phase-Locked Loop Clock distribution for
PC100/PC133 SDRAM applications
•When outputs are disabled, the PLL and feedback output are
disabled, dropping AI
clock signal is present.
to 100 µA in stand-by mode when input
CC
•See PCK2510SA for JEDEC compliant option where PLL remains
locked when outputs are disabled.
•Spread Spectrum clock compatible
•Operating frequency 50 to 150 MHz
•(t
phase error
– jitter) at 100 to133 MHz = ±50 ps
•Jitter (peak-peak) at 100 to 133 MHz = ± 80 ps
•Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps
•Pin-to-pin skew < 200 ps
•Available in plastic 24-Pin TSSOP
•Distributes one clock input to one bank of ten outputs
•External Feedback (FBIN) terminal Is used to synchronize the
outputs to the clock input
•On-Chip series damping resistors
•No external RC network required
•Operates at 3.3 V
•See page 7 for Characteristic curves.
independent of the duty cycle at CLK. All outputs can be enabled or
disabled via a single output enable input. When the G input is high,
the outputs switch in phase and frequency with CLK; when the G
input is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the PCK2510SL does not
require external RC networks. The loop filter for the PLL is included
on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the PCK2510SL requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power
up and application of a fixed-frequency, fixed-phase signal at CLK,
and following any changes to the PLL reference. The PLL can be
bypassed for test purposes by strapping AV
to ground.
CC
The PCK2510SL is characterized for operation from 0 °C to +70 °C.
PIN CONFIGURATION
1
AGND
2
V
CC
3
1Y0
4
1Y1
5
1Y2
6
GND
7
GND
8
1Y3
9
1Y4
10
V
CC
11
G
12 13
FBOUT
CLK
24
23
AV
CC
22
V
CC
21
1Y9
20
1Y8
19
GND
18
GND
17
1Y7
16
1Y6
15
1Y5
14
V
CC
FBIN
DESCRIPTION
SW00382
The PCK2510SL is a high-performance, low-skew, low-jitter,
phase-locked loop (PLL) clock driver. It uses a PLL to precisely
align, in both frequency and phase, the feedback (FBOUT) output to
the clock (CLK) input signal. It is specifically designed for use with
synchronous DRAMs. The PCK2510SL operates at 3.3 V V
CC
and
is input compatible with both 2.5 V and 3.3 V input voltage ranges. It
also provides integrated series damping resistors that make it ideal
for driving point-to-point loads.
One bank of ten outputs provides ten low-skew, low-jitter copies of
CLK. Output signal duty cycles are adjusted to 50 percent,
ORDERING INFORMA TION
PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER
24-Pin Plastic TSSOP 0 °C to +70 °C PCK2510SLDH SOT355-1
2000 Dec 01 853–2231 25137
2
Philips Semiconductors Product specification
PCK2510SL50–150 MHz 1:10 SDRAM clock driver
PIN DESCRIPTIONS
PIN NUMBER SYMBOL TYPE NAME, FUNCTION, and DIRECTION
1 AGND GND Analog ground. AGND provides the ground reference for the analog circuitry.
2, 10, 14, 22 V
3, 4, 5, 8, 9,
15, 16, 17, 20, 21
6, 7, 18, 19 GND GND Ground
11 G IN
12 FBOUT OUT
13 FBIN IN
23 AV
24 CLK IN
CC
1Y (0–9) OUT
CC
PWR Power supply
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y (0–9) is enabled
via the G input. These outputs can be disabled to a logic-low state by de-asserting the G control
input. Each output has an integrated 25 Ω series-damping resistor.
Output bank enable. G is the output enable for outputs 1Y (0–9). When G is LOW, outputs 1Y
(0–9) are disabled to a logic LOW state. When G is HIGH, all outputs 1Y (0–9) are enabled and
switch at the same frequency as CLK.
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency
as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL.
FBOUT has an integrated 25 Ω series-damping resistor.
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be
hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so
that there is nominally zero phase error between CLK and FBIN.
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition,
PWR
AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL
is bypassed and CLK is buffered directly to the device outputs.
Clock input. CLK provides the clock signal to be distributed by the PCK2510SL clock driver.
CLK is used to provide the reference signal to the integrated PLL that generates the clock
output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase
lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is
required for the PLL to phase lock the feedback signal to its reference signal.
FUNCTION TABLE
INPUTS OUTPUTS
G CLK 1Y (0–9) FBOUT
X L L L
L H L H
H H H H
2000 Dec 01
3
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