12.3.3Repairing soldered joints
13DEFINITIONS
14LIFE SUPPORT APPLICATIONS
15PURCHASE OF PHILIPS I2C COMPONENTS
PCF84C00
1996 Nov 252
Philips SemiconductorsProduct specification
8-bit microcontroller with I2C-bus interface
1FEATURES
• Manufactured in silicon gate CMOS process
• 8-bit CPU, RAM, I/O in a single 28-lead or 56-lead
package
• ‘Piggy-back’ and ROM-less versions, external program
memory
• 256 × 8 RAM
• 20 quasi-bidirectional I/O port lines
• Two test inputs, one of which is also the external
interrupt input
• Three single-level vectored interrupts:
– external
– timer/event counter
2
C-bus
–I
• I2C-bus interface for serial data transfer on two lines
(serial I/O data via an existing port line and clock via a
dedicated line)
• 8-bit programmable timer/event counter
• Clock frequency range: 100 kHz to 10 MHz
• Over 80 instructions (similar to those of the MAB8048)
all of 1 or 2 cycles
• Single supply voltage (2.5 to 5.5 V)
• Stop and Idle modes
• Power-on reset circuit
• Operating temperature range: −40 to +85 °C.
PCF84C00
2GENERAL DESCRIPTION
This data sheet details the specific properties of the
PCF84C00. The shared properties of the PCF84CxxxA
family of microcontrollers are described in the
“PCF84CxxxA family”
conjunction with this publication.
The PCF84C00 has 20 quasi-bidirectional I/O lines, an
I2C-bus serial interface, a single-level vectored interrupt
structure, an 8-bit timer/event counter and on-chip clock
oscillator and clock circuits.
This efficient controller also performs well as an arithmetic
processor. It has facilities for both binary and BCD
arithmetic plus bit-handling capabilities.
The instruction set is similar to the MAB8048 and is a
sub-set of that listed in the
sheet.
data sheet, which should be read in
“PCF84CxxxA family”
data
3ORDERING INFORMATION
TYPE
NUMBER
PCF84C00B−Non-standard 28-lead ‘piggy-back’ package with 28-pin EPROM socket
PCF84C00TVSO56Plastic very small outline package; 56 leads.SOT 190-1
1996 Nov 253
NAMEDESCRIPTIONVERSION
on top. Bottom ‘footprint’ and pinning as DIP 28, version SOT117-1.
The SOT117-1 information provided in Chapter “Package Outlines” is
correct in these respects, but not for the physical size of the
PCF84C00B, which is larger than the SOT117-1 package.
P2.21I/O1 bit of Port 2: 4-bit quasi-bidirectional I/O port
2
SDA/P2.32I/Obidirectional data line of the I
C-bus interface; or 1 bit of Port 2: 4-bit
quasi-bidirectional I/O line
2
SCLK3I/Obidirectional clock line of the I
C-bus interface
P0.0 to P0.74 to 11I/O8 bits of Port 0: 8-bit quasi-bidirectional I/O port
INT/T012IInterrupt/Test 0: external interrupt input (negative edge triggered)/test input
pin. When used as a test input, this pin is directly tested by conditional branch
instructions JT0 and JNT0.
T113ITest 1: test input pin, directly tested by conditional branch instructions JT1 and
JNT1. T1 may also be selected as an input to the 8-bit timer/event counter via
the STRT CNT instruction.
V
SS
14Pground: circuit earth potential
XTAL115Ioscillator input: input from a crystal which determines the internal oscillator
frequency or an external clock generator
XTAL216I/Ooscillator output: output of the inverting amplifier
RESET17I/Oreset input: used to initialize the microcontroller (active HIGH); also output of
power-on-reset circuit
P1.0 to P1.718 to 25I/O8 bits of Port 1: 8-bit quasi-bidirectional I/O port
P2.0 to P2.126, 27I/O2 bits of Port 2: 4-bit quasi-bidirectional I/O port
V
DD
28Ppower supply: 2.5 V to 5.5 V
1996 Nov 255
Philips SemiconductorsProduct specification
8-bit microcontroller with I2C-bus interface
Table 2 PCF84C00T (see Fig.5)
SYMBOLPINTYPEDESCRIPTION
P2.21I/O1 bit of Port 2: 4-bit quasi-bidirectional I/O port
2
SDA/P2.32I/Obidirectional data line of the I
quasi-bidirectional I/O port
SCLK3I/O bidirectional clock line of the I
P0.0 to P0.14, 5I/O2 bits of Port 0: 8-bit quasi-bidirectional I/O port
DXALE6OAddress latch enable: on the falling edge of DXALE, the Dx address can be
latched in an external latch. This signal occurs only during execution of the
MOV Dx, A, MOV A, Dx, ANL Dx, A and ORL Dx, A instructions, with
x = 0 to 255. It is active during TS10 of cycle 1 and the first half of TS1 of
cycle 2.
n.c.7−not connected
P0.2 to P0.78 to 13I/O6 bits of Port 0: 8-bit quasi-bidirectional I/O port
INT/T014IInterrupt/Test 0: external interrupt input (negative edge triggered)/test input
pin. When used as a test input, this pin is directly tested by conditional branch
instructions JT0 and JNT0; note 1.
T115IT est 1: test input pin, directly tested by conditional branch instructions JT1 and
JNT1. T1 may also be selected as an input to the 8-bit timer/event counter via
the STRT CNT instruction.
D0 to D216 to 18I/O3 bits of 8-bit data bus: for external memory and peripherals. The specified
Stop mode supply current is valid only if external pull-ups are connected to all
data lines.
A1219O1 bit of 13-bit address bus: for external memory and peripherals
DXWR20OWrite strobe (active LOW): on the rising edge, data on D0-D7 may be written
to external registers. This signal occurs only during MOV Dx, A, ANL Dx, A
and ORL Dx, A instructions, with x = 0 to 255. It is active during TS7 of
cycle 2.
n.c.21−not connected
A11 to A622 to 27O6 bits of 13-bit address bus: for external memory and peripherals
V
SS
A5 to A029 to 34O6 bits of 13-bit address bus: for external memory and peripherals
DXRD35ORead strobe (active LOW): when this signal is active, external registers
D3 to D736 to 40I/O5 bits of 8-bit data bus: for external memory and peripherals. The specified
PSEN41OProgram store enable (active LOW): PSEN is used to enable external
XTAL142Ioscillator input: input from a crystal which determines the internal oscillator
XTAL243I/Ooscillator output: output of the inverting amplifier
28Pground: circuit earth potential
emulating Dx registers can be read by the data bus. This signal occurs only
during execution of MOV A, Dx, ANL Dx, A and ORL Dx, A instructions, with
x=0to255. It is active during TS3 and TS4 of cycle 2.
Stop mode supply current is valid only if external pull-ups are connected to all
data lines.
program memory and is active during TS9 and TS10 of each machine cycle
and TS1 of each following cycle. PSEN is HIGH during the Stop mode.
frequency or an external clock generator
C-bus interface; or 1 bit of Port 2: 4-bit
2
C-bus interface
PCF84C00
1996 Nov 256
Philips SemiconductorsProduct specification
8-bit microcontroller with I2C-bus interface
SYMBOLPINTYPEDESCRIPTION
RESET44I/Oreset input: used to initialize the microcontroller (active HIGH); also output of
power-on-reset circuit
P1.0 to P1.345 to 48I/O4 bits of Port 1: 8-bit quasi-bidirectional I/O port
EXDI49IExternal derivative interrupt (active LOW): EXDI is ‘OR-ed’ with the internal
serial interrupt and can be used to initiate an interrupt from external hardware
emulating derivative functions. EXDI is pulled HIGH internally. The derivative
interrupt is polled during time slot TS6 (note 1), and is only accepted if an EN
SI instruction has been executed and the device is not already executing an
interrupt routine. Derivative interrupts are not latched in the PCF84C00.
P1.4 to P1.750 to 53I/O4 bits of Port 1: 8-bit quasi-bidirectional I/O port
P2.0 to P2.154, 55I/O2 bits of Port 2: 4-bit quasi-bidirectional I/O port
V
DD
Note
1. The interrupt signal must remain active until the vector address (05 H) is present on the address bus.