Philips pcf84c00 DATASHEETS

INTEGRATED CIRCUITS
DATA SH EET
PCF84C00
8-bit microcontroller with I interface
Product specification Supersedes data of May 1996 File under Integrated Circuits, IC14
C-bus
1996 Nov 25
Philips Semiconductors Product specification
8-bit microcontroller with I2C-bus interface

CONTENTS

1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING 6 FUNCTIONAL DESCRIPTION
6.1 ‘Piggy-back’ version PCF84C00B
6.2 ROM-less version PCF84C00T
6.3 Data memory
6.4 I/O facilities
6.5 Reset 7 LIMITING VALUES 8 HANDLING 9 DC CHARACTERISTICS 10 AC CHARACTERISTICS 11 PACKAGE OUTLINES 12 SOLDERING
12.1 Introduction
12.2 DIP
12.2.1 Soldering by dipping or by wave
12.2.2 Repairing soldered joints
12.3 SO and VSO
12.3.1 Reflow soldering
12.3.2 Wave soldering
12.3.3 Repairing soldered joints 13 DEFINITIONS 14 LIFE SUPPORT APPLICATIONS 15 PURCHASE OF PHILIPS I2C COMPONENTS
PCF84C00
1996 Nov 25 2
Philips Semiconductors Product specification
8-bit microcontroller with I2C-bus interface

1 FEATURES

Manufactured in silicon gate CMOS process
8-bit CPU, RAM, I/O in a single 28-lead or 56-lead
package
‘Piggy-back’ and ROM-less versions, external program memory
256 × 8 RAM
20 quasi-bidirectional I/O port lines
Two test inputs, one of which is also the external
interrupt input
Three single-level vectored interrupts: – external – timer/event counter
2
C-bus
–I
I2C-bus interface for serial data transfer on two lines (serial I/O data via an existing port line and clock via a dedicated line)
8-bit programmable timer/event counter
Clock frequency range: 100 kHz to 10 MHz
Over 80 instructions (similar to those of the MAB8048)
all of 1 or 2 cycles
Single supply voltage (2.5 to 5.5 V)
Stop and Idle modes
Power-on reset circuit
Operating temperature range: 40 to +85 °C.
PCF84C00

2 GENERAL DESCRIPTION

This data sheet details the specific properties of the PCF84C00. The shared properties of the PCF84CxxxA family of microcontrollers are described in the
“PCF84CxxxA family”
conjunction with this publication. The PCF84C00 has 20 quasi-bidirectional I/O lines, an
I2C-bus serial interface, a single-level vectored interrupt structure, an 8-bit timer/event counter and on-chip clock oscillator and clock circuits.
This efficient controller also performs well as an arithmetic processor. It has facilities for both binary and BCD arithmetic plus bit-handling capabilities.
The instruction set is similar to the MAB8048 and is a sub-set of that listed in the sheet.
data sheet, which should be read in
“PCF84CxxxA family”
data

3 ORDERING INFORMATION

TYPE
NUMBER
PCF84C00B Non-standard 28-lead ‘piggy-back’ package with 28-pin EPROM socket
PCF84C00T VSO56 Plastic very small outline package; 56 leads. SOT 190-1
1996 Nov 25 3
NAME DESCRIPTION VERSION
on top. Bottom ‘footprint’ and pinning as DIP 28, version SOT117-1. The SOT117-1 information provided in Chapter “Package Outlines” is correct in these respects, but not for the physical size of the PCF84C00B, which is larger than the SOT117-1 package.
PACKAGE
Philips Semiconductors Product specification
8-bit microcontroller with I2C-bus interface

4 BLOCK DIAGRAM

handbook, full pagewidth
SCLK
clock
I2C-BUS
INTERFACE
SIO interrupt
data
SERIAL DATA/P2.3
PORT 2
BUFFER
PORT 2
LATCH
INTERNAL
CLOCK
FREQUENCY
4
P2.2 to P2.0
3
30
"SEE
FIGS 2 AND 3"
MEMORY
BANK
FLIP-FLOPS
TIMER/
32
EVENT
COUNTER
TEST 1
885
(8)
timer interrupt
13
HIGHER PROGRAM COUNTER
(5)
PCF84C00
P1.7 to P1.0
88
PORT 1
BUFFER
PORT 1
LATCH
LOWER PROGRAM COUNTER
(8)
88 7 8
PROGRAM
STATUS
WORD
8
PORT 0
LATCH
P0.7 to P0.0
PORT 0
BUFFER
ACCUMULATOR
POWER
ON
RESET
RESET
POWER SUPPLY
V
V
DD
SS
TEMPORARY
REGISTER 1
V
POR
GND
STOP IDLE
(8) (8)(8)
INT/T0
INTERRUPT
TEMPORARY
REGISTER 2
external interrupt
CONTROL & TIMING
INITIALIZE
INTERRUPT
LOGIC
ARITHMETIC
LOGIC UNIT
(8)
DECIMAL
ADJUST
XTAL 2XTAL 1RESET
OSCILLATOR
XTAL
Fig.1 Block diagram.
INSTRUCTION
REGISTER
&
DECODER
PROGRAM COUNTER
CONDITIONAL
BRANCH
LOGIC
RAM
ADDRESS
REGISTER
INT/T0 TEST 1 TIMER FLAG CARRY
ACC ACC BIT
TEST
MULTIPLEXER
REGISTER 0 REGISTER 1 REGISTER 2 REGISTER 3 REGISTER 4 REGISTER 5
D
REGISTER 6
E
REGISTER 7
C
8 LEVEL STACK
O
(VARIABLE LENGTH)
D
OPTIONAL SECOND
E
REGISTER BANK
DATA STORE
RESIDENT RAM ARRAY
MGG401
1996 Nov 25 4
Philips Semiconductors Product specification
8-bit microcontroller with I2C-bus interface
A0-A12
PSEN
Fig.2 Replacement of dotted section in Fig.1, for
the PCF84C00B ‘piggy-back’ version.

5 PINNING Table 1 PCF84C00B (see Fig.4)

D0-D7
8
13
MGG402
PCF84C00
full pagewidth
PSEN
DXALE
DXRD
DXWR
EXDI
Fig.3 Replacement of dotted section in Fig.1, for
the PCF84C00T ROM-less version.
A0-A12
D0-D7
13
8
SYMBOL PIN TYPE DESCRIPTION
P2.2 1 I/O 1 bit of Port 2: 4-bit quasi-bidirectional I/O port
2
SDA/P2.3 2 I/O bidirectional data line of the I
C-bus interface; or 1 bit of Port 2: 4-bit
quasi-bidirectional I/O line
2
SCLK 3 I/O bidirectional clock line of the I
C-bus interface P0.0 to P0.7 4 to 11 I/O 8 bits of Port 0: 8-bit quasi-bidirectional I/O port INT/T0 12 I Interrupt/Test 0: external interrupt input (negative edge triggered)/test input
pin. When used as a test input, this pin is directly tested by conditional branch instructions JT0 and JNT0.
T1 13 I Test 1: test input pin, directly tested by conditional branch instructions JT1 and
JNT1. T1 may also be selected as an input to the 8-bit timer/event counter via the STRT CNT instruction.
V
SS
14 P ground: circuit earth potential
XTAL1 15 I oscillator input: input from a crystal which determines the internal oscillator
frequency or an external clock generator XTAL2 16 I/O oscillator output: output of the inverting amplifier RESET 17 I/O reset input: used to initialize the microcontroller (active HIGH); also output of
power-on-reset circuit P1.0 to P1.7 18 to 25 I/O 8 bits of Port 1: 8-bit quasi-bidirectional I/O port P2.0 to P2.1 26, 27 I/O 2 bits of Port 2: 4-bit quasi-bidirectional I/O port V
DD
28 P power supply: 2.5 V to 5.5 V
1996 Nov 25 5
Philips Semiconductors Product specification
8-bit microcontroller with I2C-bus interface
Table 2 PCF84C00T (see Fig.5)
SYMBOL PIN TYPE DESCRIPTION
P2.2 1 I/O 1 bit of Port 2: 4-bit quasi-bidirectional I/O port
2
SDA/P2.3 2 I/O bidirectional data line of the I
quasi-bidirectional I/O port SCLK 3 I/O bidirectional clock line of the I P0.0 to P0.1 4, 5 I/O 2 bits of Port 0: 8-bit quasi-bidirectional I/O port DXALE 6 O Address latch enable: on the falling edge of DXALE, the Dx address can be
latched in an external latch. This signal occurs only during execution of the
MOV Dx, A, MOV A, Dx, ANL Dx, A and ORL Dx, A instructions, with
x = 0 to 255. It is active during TS10 of cycle 1 and the first half of TS1 of
cycle 2. n.c. 7 not connected P0.2 to P0.7 8 to 13 I/O 6 bits of Port 0: 8-bit quasi-bidirectional I/O port INT/T0 14 I Interrupt/Test 0: external interrupt input (negative edge triggered)/test input
pin. When used as a test input, this pin is directly tested by conditional branch
instructions JT0 and JNT0; note 1. T1 15 I T est 1: test input pin, directly tested by conditional branch instructions JT1 and
JNT1. T1 may also be selected as an input to the 8-bit timer/event counter via
the STRT CNT instruction. D0 to D2 16 to 18 I/O 3 bits of 8-bit data bus: for external memory and peripherals. The specified
Stop mode supply current is valid only if external pull-ups are connected to all
data lines. A12 19 O 1 bit of 13-bit address bus: for external memory and peripherals DXWR 20 O Write strobe (active LOW): on the rising edge, data on D0-D7 may be written
to external registers. This signal occurs only during MOV Dx, A, ANL Dx, A
and ORL Dx, A instructions, with x = 0 to 255. It is active during TS7 of
cycle 2. n.c. 21 not connected A11 to A6 22 to 27 O 6 bits of 13-bit address bus: for external memory and peripherals V
SS
A5 to A0 29 to 34 O 6 bits of 13-bit address bus: for external memory and peripherals DXRD 35 O Read strobe (active LOW): when this signal is active, external registers
D3 to D7 36 to 40 I/O 5 bits of 8-bit data bus: for external memory and peripherals. The specified
PSEN 41 O Program store enable (active LOW): PSEN is used to enable external
XTAL1 42 I oscillator input: input from a crystal which determines the internal oscillator
XTAL2 43 I/O oscillator output: output of the inverting amplifier
28 P ground: circuit earth potential
emulating Dx registers can be read by the data bus. This signal occurs only
during execution of MOV A, Dx, ANL Dx, A and ORL Dx, A instructions, with
x=0to255. It is active during TS3 and TS4 of cycle 2.
Stop mode supply current is valid only if external pull-ups are connected to all
data lines.
program memory and is active during TS9 and TS10 of each machine cycle
and TS1 of each following cycle. PSEN is HIGH during the Stop mode.
frequency or an external clock generator
C-bus interface; or 1 bit of Port 2: 4-bit
2
C-bus interface
PCF84C00
1996 Nov 25 6
Philips Semiconductors Product specification
8-bit microcontroller with I2C-bus interface
SYMBOL PIN TYPE DESCRIPTION
RESET 44 I/O reset input: used to initialize the microcontroller (active HIGH); also output of
power-on-reset circuit P1.0 to P1.3 45 to 48 I/O 4 bits of Port 1: 8-bit quasi-bidirectional I/O port EXDI 49 I External derivative interrupt (active LOW): EXDI is ‘OR-ed’ with the internal
serial interrupt and can be used to initiate an interrupt from external hardware
emulating derivative functions. EXDI is pulled HIGH internally. The derivative
interrupt is polled during time slot TS6 (note 1), and is only accepted if an EN
SI instruction has been executed and the device is not already executing an
interrupt routine. Derivative interrupts are not latched in the PCF84C00. P1.4 to P1.7 50 to 53 I/O 4 bits of Port 1: 8-bit quasi-bidirectional I/O port P2.0 to P2.1 54, 55 I/O 2 bits of Port 2: 4-bit quasi-bidirectional I/O port V
DD
Note
1. The interrupt signal must remain active until the vector address (05 H) is present on the address bus.
56 P power supply: 2.5 V to 5.5 V
PCF84C00
1996 Nov 25 7
Philips Semiconductors Product specification
8-bit microcontroller with I2C-bus interface
handbook, halfpage
P2.2 P2.3
SCLK
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
INT/T0
T1
V
SS
1 2 3 4 5 6 7
PCF84C00B
8
9 10 11 12 13
MGG403
28 27 26 25 24 23 22 21 20 19 18 17 16 1514
V
DD
P2.1 P2.0 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 RESET XTAL2 XTAL1
handbook, halfpage
P2.2 P2.3
SCLK
P0.0 P0.1
DXALE
n.c. P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
INT/T0
T1 D0 D1 D2
A12
DXWR
n.c. A11 A10
A9 A8 A7 A6
V
SS
1 2 3 4 5 6 7 8
9 10 11 12 13 14
PCF84C00T
15 16 17 18 19
20
21 22 23 24 25 26 27 28
MGG404
PCF84C00
V
56
DD
P2.1
55
P2.0
54
P1.7
53
P1.6
52
P1.5
51
P1.4
50
EXDI
49
P1.3
48
P1.2
47
P1.1
46
P1.0
45
RESET
44
XTAL2
43
XTAL1
42
PSEN
41
D7
40
D6
39
D5
38
D4
37
D3
36
DXRD
35
A0
34
A1
33
A2
32
A3
31
A4
30
A5
29
Fig.4 Bottom pinning diagram, ‘piggy-back’
version PCF84C00B.
1996 Nov 25 8
Fig.5 Pinning diagram; ROM-less version
PCF84C00T.
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