Philips PCF5079 User Manual

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INTEGRATED CIRCUITS

DATA SH EET

PCF5079

Dual-band power amplifier
controller for GSM, PCN and DCS

Product specification
File under Integrated Circuits, IC17

2001 Nov 21

Philips Semiconductors Product specification

Dual-band power amplifier controller for
GSM, PCN and DCS

CONTENTS

1 FEATURES
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 QUICK REFERENCE DATA
5 BLOCK DIAGRAM
6 PINNING

6.1 Pin description

6.2 Pin configurations
7 FUNCTIONAL DESCRIPTION

7.1 General

7.2 Power-up mode

7.3 OP4 (integrator)

7.4 Start-up and initial conditions

7.5 Home position voltage

7.6 End of burst

7.7 Considerations for ramp-down

7.8 Configurations

7.9 Summary of current and voltage definitions

7.10 Timing
8 LIMITING VALUES
9 ELECTROSTATIC DISCHARGE (ESD)
10 DC CHARACTERISTICS
11 OPERATING CHARACTERISTICS
12 APPLICATION INFORMATION

12.1 Ramp control

12.2 PA protection against mismatch

12.3 Detected voltage measurement

12.4 Application examples

PCF5079

13 PACKAGE OUTLINES
14 SOLDERING (TSSOP10)

14.1 Introduction to soldering surface mount
packages

14.2 Reflow soldering

14.3 Wave soldering

14.4 Manual soldering

14.5 Suitability of surface mount IC packages for
wave and reflow soldering methods

15 SOLDERING (HVSON10)

15.1 Soldering information

15.2 PCB design guidelines

15.2.1 Perimeter pad design

15.2.2 Thermal pad and via design

15.2.3 Stencil design for perimeter pads

15.2.4 Stencil design for thermal pads

15.2.5 Stencil thickness

16 DATA SHEET STATUS
17 DEFINITIONS
18 DISCLAIMERS

2001 Nov 21 2

Philips Semiconductors Product specification

Dual-band power amplifier controller for
GSM, PCN and DCS

1 FEATURES

• Compatible with baseband interface family PCF5073x

• Two power sensor inputs

• Temperature compensation of sensor signal

• Active filter for Digital-to-Analog Converter (DAC) input

• Power Amplifier (PA) protection against mismatching

• Bias current source for detector diodes

• Generation of pre-bias level for PA at start of burst

(home position)

• Compatible with a wide range of silicon PAs

• Compatible with multislot class 12

• Dual output with internal switch

• Two different transfer functions

• Possibility to adapt dynamic transfer functions

• Very small outline package (3 × 3 mm).

PCF5079

2 APPLICATIONS

• Global System for Mobile communication (GSM)

• Personal Communications Network (PCN) systems.

3 GENERAL DESCRIPTION

This CMOSdevice integrates an amplifier for the detected
RF voltage from the sensor, an integrator and an active
filter to build a PA control loop for cellular systems with a
small number of passive components.

4 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DD

I

DD(tot)

T

amb

ORDERING INFORMATION

TYPE NUMBER

PCF5079T/C/1 TSSOP10 plastic thin shrink small outline package; 10 leads; body width 3 mm SOT552-1
PCF5079HK/C/1 HVSON10 plastic, heatsink very thin small outline package; no leads;

supply voltage 2.5 3.6 5.0 V
total supply current −−10 mA
ambient temperature −40 − +85 °C

PACKAGE

NAME DESCRIPTION VERSION

SOT650-1

10 terminals; body 3 × 3 × 0.90 mm

2001 Nov 21 3

Philips Semiconductors Product specification

Dual-band power amplifier controller for
GSM, PCN and DCS

5 BLOCK DIAGRAM

handbook, full pagewidth

S1

C4

OP1

OP1

RF

V

DD

RF

in

I

30 µA

C1

6 pF

C2

6 pF

C3

16.6 pF

10 µA

RF

V

out

10 pF

PU

6

SS

PA

D2

VS2 VS1 VCD1VCG

4523

bias2Ibias1

30 µA

V

V

AUXDAC3

PCF5073x

DD

PU

G = 0.3

V

home

7
VDAC

filter

DD

V

V

DD

SS

PA

in

S5

20 kΩ

BAND GAP

AND CURRENT

REFERENCE

S3S4

R4

10

R1

V

V

DD

SS

D1

10 µA

V

prebias

6 kΩ

VINT(N)

PU

OP4

OP4

OP4

IN

VDAC

CINT1

CINT2

PU

V

DD

RF

out

SF
SF

PU

PU

ref

PCF5079

phases

D
G

D

OP4

D

G

OP4

G

CONTROL

LOGIC

8 9

PU BS

PU/PD

commands

MGT325

PCF5079

Fig.1 Block diagram.

2001 Nov 21 4

Philips Semiconductors Product specification

Dual-band power amplifier controller for
GSM, PCN and DCS

6 PINNING

6.1 Pin description
SYMBOL PIN TYPE

VCG 1 O and A PA control voltage output (GSM)
VINT(N) 2 I and A negative integrator input
VCD 3 O and A PA control voltage (DCS)
VS1 4 I/O and A sensor signal input 1
VS2 5 I/O and A sensor signal input 2
V

SS

6 G reference ground
VDAC 7 I and A DAC input voltage
PU 8 I and D power-up input
BS 9 I and D band selection input
V

DD

10 P positive supply voltage

Note

1. O = output, I = input, I/O = input/output, A = analog, D = digital, P = power supply and G = ground

(1)

DESCRIPTION

PCF5079

6.2 Pin configurations

handbook, halfpage

VCG

VINT(N)

VCD

VS1
VS2

1
2
3

PCF5079T

4
5

MGT326

V

10

DD

9

BS

8

PU

7

VDAC
V

6

SS

Fig.2 Pin configuration (top view) for PCF5079T,

pins are numbered counter-clockwise.

handbook, halfpage

VS2
VS1

VCD

VINT(N)

VCG

5
4
3

PCF5079HK

2
1

6
7
8
9

10

MGU268

Fig.3 Pin configuration (bottom view) for

PCF5079HK, pins are numbered clockwise.

V

SS

VDAC
PU

BS
V

DD

2001 Nov 21 5

Philips Semiconductors Product specification

Dual-band power amplifier controller for
GSM, PCN and DCS

7 FUNCTIONAL DESCRIPTION

7.1 General

The PCF5079 contains an integrated amplifier for the
detected RF voltage from the sensor, an integrator and an
active filter to build up a PA control loop for cellular
systems with a small number of passive components
suitable for dual-band applications. The active band can
be selected by means of the dedicated input BS.

The sensor amplifier can amplify signals from an
RF powerdetector in a range oflessthan−20 to +15 dBm.
This can comply to the PA output power range of
GSM900/1800/1900 systems when, for example, a
directional coupler with 20 dB attenuation is used for
GSM900 and a directional coupler with 18 dB attenuation
is used for GSM1800.

The external Schottky diodes for power detection (sensor)
are biased by an integrated current source of 30 µA.
Variationsof the forwardvoltagewith temperature haveno
influence on the measured signal because they are
cancelled by the switched capacitor amplifier OP1.

An external DAC with at least 10-bit resolution (for
example, AUXDAC3 of baseband interface family
PCF5073x) is necessary to control the loop.

PCF5079

7.4 Start-up and initial conditions

ThePCF5079 is designedto operate in bursts,as required
in TDMA systems. Referring to Fig.4, for each time slot to
be transmitted the PCF5079 must be enabled by setting
signal PU to logic 1. Once pin PU is active, BS is taken
into account to allow correct initialisation of switches S1,
SFD,SFG, S3, S4 and S5, and of the configuration signals
PUG and PUD.

Thefeedback switch across theunuseddriver is kept open
andthe output voltagefromthe unused driveristied to V
to maintain the off state of the unused PA.

When pin PU is set to logic 1, at least 5 µs after VDD has
reacheditsfinal value, switches S1, theappropriateswitch
SFD or SFGand S3 are closed, and switches S4 and S5
are opened. Because switch S1 is closed, the forward
voltage of Schottky diodes D1 and D2 is sampled on
capacitors C1 and C2 respectively.

Moreover, the control voltage on pin VCD or VCG is
initially forced to be at the pre-bias voltage because the
appropriate switch SFDor SFGand S3 are closed, and S4
is opened.

After a fixed time, defined on-chip, switch S1 is opened
and the circuit is ready.

SS

An integrated active filter smooths thevoltage steps of the
DAC during ramp-up and ramp-down.

The operation principle is the same, independently of the
selected standard. The DAC signal and the sensor signal
areadded by amplifierOP1. The voltage differenceof both
signals is integrated by operational amplifier OP4
dedicated to the selected standard, which delivers the
PA control voltage on an external capacitance, CINT1 or
or CINT2, between pins VINT(N) and VCD or VCG,
respectively. The shape of the rising and falling power
burst edges can be determined by means of the DAC
voltage.

7.2 Power-up mode

The device includes a power-up input (pin PU) to switch
the ICon during time slotsthatareused in TDMA systems,
and to switch the IC off during the unused slots to reduce
current consumption.

7.3 OP4 (integrator)

The operational amplifier OP4 (integrator) consists of a
shared input stage, OP4IN and a dedicated output driver
for each standard, OP4G and OP4D. Depending on the
status of input BS, one driveris active andthe other iskept
in power-down mode during active time slots.

Once switch S1 is open, a ramp signal applied at
pin VDAC(at least 20 µsafter the transitionof pin PU from
logic 0 to logic 1)with an amplitude of atleast 70 mV,from
CODE
switch S3 and closing of switch S4 on the home voltage,
with a delay of 3 µs maximum with respect to the ramp.
After switch S3 opens (in a fixed amount of time), the
control voltage on pin VCD or pin VCG rises to the home
position to bias the PA to the beginning of the activerange
of its control curve. During this time (typically 2 µs), the
appropriate switch SFDor SFGremains closed. When the
appropriate switch SFD or SFG is opened, switch S5 is
closed, allowing the transfer of any signal coming from
amplifier OP1. After this preset, the control voltage is free
to increase according to the control loop if the RF input is
enabled (see Fig.12).

For higher DAC ramp steps, the delay of switch S3
opening (S4 closing) is reduced while the delay between
switch SFD(SFG) opening with respect to S3 opening
(S4 closing) remains unchanged.

START

to CODE

, determines the opening of

KICK

2001 Nov 21 6

Philips Semiconductors Product specification

Dual-band power amplifier controller for
GSM, PCN and DCS

handbook, full pagewidth

CODE

CODE

V

V

VDAC

KICK

START

DD

PU

S1

t

>5 µs

d1

>70 mV

t

d2

>20 µs

0

462

8 . . .

time

time

time (QB)

time

PCF5079

closed

open

SFD, SF

V

VCD, VVCG

V

V

prebias

S3

S4

S5

home

closed

open

t

d3
<3 µs
(max)

G

t

d4

2 µs (typ)

time

time

time

time

time

MGT327

closed

open

closed

open

closed

open

The maximum value of CODE
CODE
have to be chosen to get the best ramp shape and spectrum performance.

applied for two quarter-bits ensures a start-up ofthecontrolvoltagewithverylowjitter and high repetitivity. The codes following CODE

START

is limited by the isolation requirement of the PA used in the application. The pulse determined byCODE

START

Fig.4 Start-up and initialization timing diagram.

2001 Nov 21 7

KICK

minus

KICK

Philips Semiconductors Product specification

Dual-band power amplifier controller for
GSM, PCN and DCS

7.5 Home position voltage

Internally, a forward voltage of an on-chip silicon diode is
provided as adefault home position.This voltage matches
the requirements at the control input of most PAs and
exhibits the same temperature coefficient.

7.6 End of burst

The ramp-down should drive the PA from conduction to
shut off in a controlled way (see Fig.5). To get this result,
correctDACprogramming is required, sothatthelast code
of the DAC ramp-down (CODE
code of theramp-up (CODE
corresponding to the difference between start and end

handbook, full pagewidth

V

VDAC

) is lower than the initial

END

). In thisway, the energy

START

PU

PCF5079

codes, applied for a certain number of Quarter-Bits (QB),
is used to balance the energy stored in thesumming node
duringthe time intervalbetween the start ofcontrol voltage
on pin VCD or VCG ramping-up and the feedback of a
detected ramp to the sensor input. Also a very slow
ramp-down is avoided when the PA switches off and the
loop gain becomes zero.

The amount of energy required at the end of the
ramp-down depends on the overall loop gain and on the
time needed to reach PA conduction from the home
position. At the end of a burst, when pin PU is set to
logic 0, control voltage on pin VCD or VCG is forced
to VSS.

time

CODE

START

CODE

S1, S3

S4, S5

V

VCD, VVCG

END

. . . i−8i−6i−4i−2i

V

SS

(1)

t

A

time (QB)

closed

open

time

closed

open

time

t

d5

<

1 µs

time

MGT328

(1) The exact duration oftAdepends onbothPCF5079 and the application loopcharacteristics.The contribution of PCF5079 isduemainly to the group

delay of the low-pass filter on the VDAC input (see Fig.11).

Fig.5 End of burst timing diagram.

2001 Nov 21 8

Philips Semiconductors Product specification

Dual-band power amplifier controller for
GSM, PCN and DCS

7.7 Considerations for ramp-down

Referring to Fig.5, the i-th code can be programmed to
have either the CODE
code between, depending on the application preferences.
Thesecodes do not produceanypower at the outputofthe
PA, as CODE

START

isolation. The proper conclusion of the ramp-down is
ensured by choosing CODE
discharge of the integration capacitance is controlled until
the control voltage on pin VCD or VCG goes below the PA
conduction threshold and by applying at this time the PU
transition from logic 1 to logic 0.

At the beginning of a burst, the VDACsignal steps applied
at OP1 are not compensated by any signal at the sensor
input up to when pin VCD or VCG voltage is greater than
the PA conduction threshold voltage. In any case, the
initial DAC voltage steps are stored in the capacitance of
amplifier OP1. CODE
energy inside the shaded zone cancels the energy
accumulated in the summing node (OP1) at the start of a
burst and not balanced by a feedback signal at the sensor
input.

The exact value of the energy required depends on the
specific PA, on the characteristics of the overall loop and
on the values chosen for the settable parameters inside
the loop.

A rough idea can be derived with a simplified analysis of a
ramp-up, ramp-down cycle using the following
simplifications:

• The starting conditions for OP1 and OP4 are biasing at
V

with zero charge on capacitances

home

• The initial rising of pin VCD or VCG voltage from V
is caused only by the integration of the constant
CODE

KICK

• VDAC is treated as applied directly at the summing
node, initially neglecting the transmission delay through
the internal low-pass filter.

or CODE

END

value or any

START

has been chosen to keep the PA

< CODE

END

has to be chosen so that the

END

START

so that the

home

PCF5079

Timet
Now, to define the quantity

∆V

the current/voltage equations around the integrator OP4
can be solved by forcing the current through R1 to be
equal to the current through the integration capacitance
and calculating the ∆V generated on C

∆V

where

iτ()

Substituting equation (4) into equation (3)

∆ V

Under the hypothesis the voltage is constant:

∆V

Equation (6) can be used to calculate time t
conduction of the PA is reached, considering that

tt

t

Time t
the PA and by ∆V
the energy contained in the shaded zone (Fig.5)is at least
equal to the energy accumulated at the beginning:

∫

where k is the number of quarter-bits during which
CODE

canbe calculated with theprecedingsimplification.

1

KICK

CINT

CINT

CINT

1

t

1

V

0

CODE

1

--------------­C

CINT

×

g

d∆VKICK

=

------------------------------ ­R1

1

----------------------------­C

CINT

1

----------------------------­C

CINT

V

1

home

R1 C

×

CINT

depends on the time constant of the integrator, by

1

2

(t) dt = k QB CODE

out

OP1

is applied.

END

CODE

–=

KICK

t

i τ()τd

×=

∫

0

×∆V

R1×

×∆V

R1×

∆V

CINTVconduction

V

conductionVhome

×=

----------------------------------------------­g

d

. The condition to be fulfilled is that

KICK

START

, then

INT

t

× dτ=

g

∫

0

g

d

KICK

d

× t×=

KICK

=+⇒=

–

∆V

×

KICK

CODE

××

–()

END

at which the

1

START

(2)

(3)

(4)

(5)

(6)

(7)

(8)

2

(9)

Generally, the integrator OP4 input can be expressed as

V

in integrator()

where g

and gdare respectively the gains of sensor input

s

×g

s

s

∆V

×–=

d

VDAC

(1)

g

∆V

and DAC input in the summing amplifier OP1.
Equation (1) holds for closed loop operation. In the time

interval between therising of pin VCD orVCG voltage due
to CODE

(t = 0) and when V

KICK

conduction

for the PA is
reached(t = t1),∆Vsis 0and operation isopen loop. Inthis
time interval, a charge accumulates in the summing node,
which remains uncompensated.

2001 Nov 21 9