Philips PCF5079 User Manual

PCF5079

INTEGRATED CIRCUITS

DATA SHEET

PCF5079

Dual-band power amplifier controller for GSM, PCN and DCS

Product specification			2001 Nov 21
File under Integrated Circuits, IC17

Philips Semiconductors	Product specification

Dual-band power amplifier controller for

PCF5079

GSM, PCN and DCS

CONTENTS

1FEATURES

2APPLICATIONS

3GENERAL DESCRIPTION

4QUICK REFERENCE DATA

5BLOCK DIAGRAM

6PINNING

6.1Pin description

6.2Pin configurations

7	FUNCTIONAL DESCRIPTION

7.1General

7.2Power-up mode

7.3OP4 (integrator)

7.4Start-up and initial conditions

7.5Home position voltage

7.6End of burst

7.7Considerations for ramp-down

7.8Configurations

7.9Summary of current and voltage definitions

7.10Timing

13PACKAGE OUTLINES

14SOLDERING (TSSOP10)

14.1Introduction to soldering surface mount packages

14.2Reflow soldering

14.3Wave soldering

14.4Manual soldering

14.5Suitability of surface mount IC packages for wave and reflow soldering methods

15 SOLDERING (HVSON10)

15.1Soldering information

15.2PCB design guidelines

15.2.1Perimeter pad design

15.2.2Thermal pad and via design

15.2.3Stencil design for perimeter pads

15.2.4Stencil design for thermal pads

15.2.5Stencil thickness

16DATA SHEET STATUS

17DEFINITIONS

18DISCLAIMERS

8LIMITING VALUES

9ELECTROSTATIC DISCHARGE (ESD)

10DC CHARACTERISTICS

11OPERATING CHARACTERISTICS

12APPLICATION INFORMATION

12.1Ramp control

12.2PA protection against mismatch

12.3Detected voltage measurement

12.4Application examples

2001 Nov 21

2

Philips Semiconductors	Product specification

Dual-band power amplifier controller for

PCF5079

GSM, PCN and DCS

1 FEATURES

∙Compatible with baseband interface family PCF5073x

∙Two power sensor inputs

∙Temperature compensation of sensor signal

∙Active filter for Digital-to-Analog Converter (DAC) input

∙Power Amplifier (PA) protection against mismatching

∙Bias current source for detector diodes

∙Generation of pre-bias level for PA at start of burst (home position)

∙Compatible with a wide range of silicon PAs

∙Compatible with multislot class 12

∙Dual output with internal switch

∙Two different transfer functions

∙Possibility to adapt dynamic transfer functions

∙Very small outline package (3 × 3 mm).

4 QUICK REFERENCE DATA

2 APPLICATIONS

∙Global System for Mobile communication (GSM)

∙Personal Communications Network (PCN) systems.

3 GENERAL DESCRIPTION

This CMOS device integrates an amplifier for the detected RF voltage from the sensor, an integrator and an active filter to build a PA control loop for cellular systems with a small number of passive components.

SYMBOL	PARAMETER		MIN.		TYP.	MAX.	UNIT
VDD	supply voltage	2.5		3.6		5.0	V
IDD(tot)	total supply current	−		−		10	mA
Tamb	ambient temperature	−40		−		+85	°C

ORDERING INFORMATION

	TYPE NUMBER		PACKAGE
		NAME	DESCRIPTION	VERSION
	PCF5079T/C/1	TSSOP10	plastic thin shrink small outline package; 10 leads; body width 3 mm	SOT552-1
	PCF5079HK/C/1	HVSON10	plastic, heatsink very thin small outline package; no leads;	SOT650-1
			10 terminals; body 3 × 3 × 0.90 mm

2001 Nov 21

3

Philips Semiconductors	Product specification

Dual-band power amplifier controller for

PCF5079

GSM, PCN and DCS

5 BLOCK DIAGRAM

RFin

PA

RFout

RFin

PA

RFout

D2

D1

CINT1

CINT2

VS2

VS1

VINT(N)

VCD

VCG

5

4

S1

2

SFD

3

1

C1

SFG

6 pF

C4

Ibias2

Ibias1

10 pF

PUOP1

PUD

C2

S5

R1

PUOP4

6 pF

20 kΩ

OP4D

OP1

30 µA

30 µA

PUG

VDD

VDD

OP4IN

PUfilter

OP4

OP4G

C3

BAND GAP

16.6 pF

AND CURRENT

PUref

G = 0.3

REFERENCE

VDD

VDD

PCF5079

10 µA

10 µA

PU/PD

S4

S3

phases

commands

Vhome

Vprebias

R4

6 kΩ

VDAC

CONTROL

VSS

VDD

LOGIC

VSS

7

6

10

8

9

VDAC

VSS

VDD

PU

BS

MGT325

AUXDAC3

PCF5073x

Fig.1 Block diagram.

2001 Nov 21

4

Philips Semiconductors	Product specification

Dual-band power amplifier controller for

PCF5079

GSM, PCN and DCS

6 PINNING

6.1Pin description

SYMBOL	PIN	TYPE(1)	DESCRIPTION
VCG	1	O and A	PA control voltage output (GSM)
VINT(N)	2	I and A	negative integrator input
VCD	3	O and A	PA control voltage (DCS)
VS1	4	I/O and A	sensor signal input 1
VS2	5	I/O and A	sensor signal input 2
VSS	6	G	reference ground
VDAC	7	I and A	DAC input voltage
PU	8	I and D	power-up input
BS	9	I and D	band selection input
VDD	10	P	positive supply voltage

Note

1. O = output, I = input, I/O = input/output, A = analog, D = digital, P = power supply and G = ground

6.2Pin configurations

handbook, halfpage				VDD	handbook, halfpage
VCG	1		10		VS2	5	6	VSS
VINT(N)
	2		9	BS	VS1	4	7	VDAC
		PCF5079T					PCF5079HK 8
VCD	3		8	PU	VCD	3		PU
					VINT(N)	2	9	BS
VS1	4		7	VDAC
				VSS	VCG	1	10	VDD
VS2	5		6
		MGT326					MGU268

Fig.2 Pin configuration (top view) for PCF5079T,	Fig.3 Pin configuration (bottom view) for
pins are numbered counter-clockwise.	PCF5079HK, pins are numbered clockwise.

2001 Nov 21

5

Philips Semiconductors	Product specification

Dual-band power amplifier controller for

PCF5079

GSM, PCN and DCS

7 FUNCTIONAL DESCRIPTION

7.1General

The PCF5079 contains an integrated amplifier for the detected RF voltage from the sensor, an integrator and an active filter to build up a PA control loop for cellular systems with a small number of passive components suitable for dual-band applications. The active band can be selected by means of the dedicated input BS.

The sensor amplifier can amplify signals from an

RF power detector in a range of less than −20 to +15 dBm. This can comply to the PA output power range of GSM900/1800/1900 systems when, for example, a directional coupler with 20 dB attenuation is used for GSM900 and a directional coupler with 18 dB attenuation is used for GSM1800.

The external Schottky diodes for power detection (sensor) are biased by an integrated current source of 30 μA. Variations of the forward voltage with temperature have no influence on the measured signal because they are cancelled by the switched capacitor amplifier OP1.

An external DAC with at least 10-bit resolution (for example, AUXDAC3 of baseband interface family PCF5073x) is necessary to control the loop.

An integrated active filter smooths the voltage steps of the DAC during ramp-up and ramp-down.

The operation principle is the same, independently of the selected standard. The DAC signal and the sensor signal are added by amplifier OP1. The voltage difference of both signals is integrated by operational amplifier OP4 dedicated to the selected standard, which delivers the PA control voltage on an external capacitance, CINT1 or or CINT2, between pins VINT(N) and VCD or VCG, respectively. The shape of the rising and falling power burst edges can be determined by means of the DAC voltage.

7.2Power-up mode

The device includes a power-up input (pin PU) to switch the IC on during time slots that are used in TDMA systems, and to switch the IC off during the unused slots to reduce current consumption.

7.3OP4 (integrator)

The operational amplifier OP4 (integrator) consists of a shared input stage, OP4IN and a dedicated output driver for each standard, OP4G and OP4D. Depending on the status of input BS, one driver is active and the other is kept in power-down mode during active time slots.

7.4Start-up and initial conditions

The PCF5079 is designed to operate in bursts, as required in TDMA systems. Referring to Fig.4, for each time slot to be transmitted the PCF5079 must be enabled by setting signal PU to logic 1. Once pin PU is active, BS is taken into account to allow correct initialisation of switches S1, SFD, SFG, S3, S4 and S5, and of the configuration signals PUG and PUD.

The feedback switch across the unused driver is kept open and the output voltage from the unused driver is tied to VSS to maintain the off state of the unused PA.

When pin PU is set to logic 1, at least 5 μs after VDD has reached its final value, switches S1, the appropriate switch SFD or SFG and S3 are closed, and switches S4 and S5 are opened. Because switch S1 is closed, the forward voltage of Schottky diodes D1 and D2 is sampled on capacitors C1 and C2 respectively.

Moreover, the control voltage on pin VCD or VCG is initially forced to be at the pre-bias voltage because the appropriate switch SFD or SFG and S3 are closed, and S4 is opened.

After a fixed time, defined on-chip, switch S1 is opened and the circuit is ready.

Once switch S1 is open, a ramp signal applied at

pin VDAC (at least 20 μs after the transition of pin PU from logic 0 to logic 1) with an amplitude of at least 70 mV, from

CODESTART to CODEKICK, determines the opening of switch S3 and closing of switch S4 on the home voltage,

with a delay of 3 μs maximum with respect to the ramp. After switch S3 opens (in a fixed amount of time), the control voltage on pin VCD or pin VCG rises to the home position to bias the PA to the beginning of the active range of its control curve. During this time (typically 2 μs), the appropriate switch SFD or SFG remains closed. When the appropriate switch SFD or SFG is opened, switch S5 is closed, allowing the transfer of any signal coming from amplifier OP1. After this preset, the control voltage is free to increase according to the control loop if the RF input is enabled (see Fig.12).

For higher DAC ramp steps, the delay of switch S3 opening (S4 closing) is reduced while the delay between switch SFD (SFG) opening with respect to S3 opening (S4 closing) remains unchanged.

2001 Nov 21

6

Philips Semiconductors	Product specification

Dual-band power amplifier controller for

PCF5079

GSM, PCN and DCS

VDD

time

PU
	td1					time
VVDAC	>5 s
CODEKICK	>70 mV
CODESTART
	0	2	4	6	8 . . .	time (QB)
	td2
	>20 s
						closed
S1
						open
						time
						closed
S3
						open
	td3					time
	<3 s
	(max)					closed
S4
						open
						time
						closed
SFD, SFG						open
						time
		td4	s (typ)
		2				closed
S5
						open
						time
VVCD, VVCG
Vhome
Vprebias
						time
						MGT327

The maximum value of CODESTART is limited by the isolation requirement of the PA used in the application. The pulse determined by CODEKICK minus CODESTART applied for two quarter-bits ensures a start-up of the control voltage with very low jitter and high repetitivity. The codes following CODEKICK have to be chosen to get the best ramp shape and spectrum performance.

Fig.4 Start-up and initialization timing diagram.

2001 Nov 21

7

Philips Semiconductors	Product specification

Dual-band power amplifier controller for

PCF5079

GSM, PCN and DCS

7.5Home position voltage

Internally, a forward voltage of an on-chip silicon diode is provided as a default home position. This voltage matches the requirements at the control input of most PAs and exhibits the same temperature coefficient.

7.6End of burst

The ramp-down should drive the PA from conduction to shut off in a controlled way (see Fig.5). To get this result, correct DAC programming is required, so that the last code of the DAC ramp-down (CODEEND) is lower than the initial

code of the ramp-up (CODESTART). In this way, the energy corresponding to the difference between start and end

codes, applied for a certain number of Quarter-Bits (QB), is used to balance the energy stored in the summing node during the time interval between the start of control voltage on pin VCD or VCG ramping-up and the feedback of a detected ramp to the sensor input. Also a very slow ramp-down is avoided when the PA switches off and the loop gain becomes zero.

The amount of energy required at the end of the ramp-down depends on the overall loop gain and on the time needed to reach PA conduction from the home position. At the end of a burst, when pin PU is set to logic 0, control voltage on pin VCD or VCG is forced

to VSS.

PU

VVDAC

CODESTART CODEEND

S1, S3

S4, S5

VVCD, VVCG

VSS

					time
. . . i−8	i−6	i−4	i−2	i	time (QB)
					closed
					open
					time
					closed
					open
					time
				tA(1)	time
				td5
				<1 µs	MGT328

(1)The exact duration of tA depends on both PCF5079 and the application loop characteristics. The contribution of PCF5079 is due mainly to the group delay of the low-pass filter on the VDAC input (see Fig.11).

Fig.5 End of burst timing diagram.

2001 Nov 21

8

Philips Semiconductors	Product specification

Dual-band power amplifier controller for

PCF5079

GSM, PCN and DCS

7.7Considerations for ramp-down

Referring to Fig.5, the i-th code can be programmed to

have either the CODEEND or CODESTART value or any code between, depending on the application preferences.

These codes do not produce any power at the output of the

PA, as CODESTART has been chosen to keep the PA isolation. The proper conclusion of the ramp-down is

ensured by choosing CODEEND < CODESTART so that the discharge of the integration capacitance is controlled until

the control voltage on pin VCD or VCG goes below the PA conduction threshold and by applying at this time the PU transition from logic 1 to logic 0.

At the beginning of a burst, the VDAC signal steps applied at OP1 are not compensated by any signal at the sensor input up to when pin VCD or VCG voltage is greater than the PA conduction threshold voltage. In any case, the initial DAC voltage steps are stored in the capacitance of amplifier OP1. CODEEND has to be chosen so that the energy inside the shaded zone cancels the energy accumulated in the summing node (OP1) at the start of a burst and not balanced by a feedback signal at the sensor input.

The exact value of the energy required depends on the specific PA, on the characteristics of the overall loop and on the values chosen for the settable parameters inside the loop.

A rough idea can be derived with a simplified analysis of a ramp-up, ramp-down cycle using the following simplifications:

·The starting conditions for OP1 and OP4 are biasing at Vhome with zero charge on capacitances

·The initial rising of pin VCD or VCG voltage from Vhome is caused only by the integration of the constant CODEKICK

·VDAC is treated as applied directly at the summing node, initially neglecting the transmission delay through the internal low-pass filter.

Generally, the integrator OP4 input can be expressed as

Vin(integrator) = gs ´ DVs –gd ´ DVVDAC

(1)

Time t1 can be calculated with the preceding simplification. Now, to define the quantity

DVKICK = CODEKICK –CODESTART

(2)

the current/voltage equations around the integrator OP4 can be solved by forcing the current through R1 to be equal to the current through the integration capacitance and calculating the DV generated on CINT, then

		1	t
DVCINT =	C--------------	CINT	´ ò0 i(t)dt			(3)
where
gd ´ DVKICK						(4)
i(t) = ------------------------------	R1
Substituting equation (4) into equation (3)
DVCINT =		1	´	t	´ DVKICKdt	(5)
	C----------------------------CINT			g
			´ R1	ò0	d

Under the hypothesis the voltage is constant:

	DVCINT	=	1	´ gd ´ DVKICK ´ t	(6)
			C----------------------------CINT
				´ R1

Equation (6) can be used to calculate time t1 at which the conduction of the PA is reached, considering that

	t = t1 Þ Vhome + DVCINT = Vconduction				(7)
	t1 =	R1 ´ CCINT	´	Vconduction –Vhome	(8)
				----------------------------------------------gd ´ DVKICK

Time t1 depends on the time constant of the integrator, by

the PA and by DVKICK. The condition to be fulfilled is that the energy contained in the shaded zone (Fig.5) is at least

equal to the energy accumulated at the beginning:

òt01 V2outOP1 (t) dt = k ´ QB ´ (CODEEND –CODESTART)2 (9)

where k is the number of quarter-bits during which CODEEND is applied.

where gs and gd are respectively the gains of sensor input and DAC input in the summing amplifier OP1.

Equation (1) holds for closed loop operation. In the time interval between the rising of pin VCD or VCG voltage due

to CODEKICK (t = 0) and when Vconduction for the PA is reached (t = t1), DVs is 0 and operation is open loop. In this

time interval, a charge accumulates in the summing node, which remains uncompensated.

2001 Nov 21

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