Philips PCF5077T Datasheet

INTEGRATED CIRCUITS

DATA SH EET

PCF5077T

Power amplifier controller for GSM
and PCN systems

Preliminary specification
File under Integrated Circuits, IC17

1997 Nov 19

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and
PCN systems

FEATURES

• CMOS low-voltage, low-power

• Can be used in burst mode with power-down

• 3-wire serial bus interface with the bus available in

Power-down mode

• On-chip ramp generator for 256 different power levels
with two dynamic ranges

• Two programmable regulator start conditions (V
and V

HOME

)

• Programmable analog output voltage limitation

• Ramping speed depending on the 13 MHz system

frequency clock for Global System for Mobile
communications (GSM) and Personal Communications
Network (PCN)

• Low swing input buffer for the 13 MHz master clock

• Compatible to a large number of different RF power

modules

KICK

PCF5077T

• Programmable temperature matching

• Dual supply concept for analog and digital part

• No external filter for suppression of clock pulse feed

through

• Direct power control with ramping function (control loop
can be switched off)

• On-chip Power-on reset for all registers

• Serial bus is compatible to bus systems independent of

additional clock pulse after rising edge of strobe signal

• Low operating current consumption

• TTL compatible interface

• Programmable gain factor for sensor signal at OP1

• Two different voltages for 1 LSB of the burst power

Digital-to-Analog Converter (DAC) are programmable.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DDD

V

DDA1

V

DDA2

I

DD(oper)(tot)

T

amb

digital supply voltage note 1 2.7 3.0 6.0 V
analog supply voltage 1 note 1 2.7 3.0 6.0 V
analog supply voltage 2 (for OP4) 2.7 5.0 6.0 V
total operating current on the VDD pins note 2 − 918mA
operating ambient temperature −40 − +85 °C

Notes

1. The voltages V

2. V

DDA1=VDDD

and V

DDA1

= 3 V and V

must be equal and V

DDD

= 5 V. The VDD pins are: V

DDA2

must be either equal or greater than V

DDA2

DDA1

, V

DDA2

and V

DDD

.

DDA1=VDDD

.

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

PCF5077T SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1

1997 Nov 19 2

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and
PCN systems

BLOCK DIAGRAM

handbook, full pagewidth

RF input
(sensor)

BAND GAP

I

bias

V

8

QRSA

DACA

KICKA

ref

DAC8

V

ref

100
mV

POWER LEVEL REGISTER
V

KICK

V

HOME
LIMITER REGISTER
DF0/1, DC, DR0/1, TEST

SERIAL BUS INTERFACE

C2

V

D1

30 µA

DACA KICKA QRSA

−0.8 −0.33 +0.33

SLOPE GENERATOR

REGISTER

REGISTER

D1

V

DDA1

SC-ADDER

VS BVS
1 4 15 14

8-bit
6-bit

6 + 2-bit

2-bit

R1

R2
1 kΩ

10 pF

C4

4.8 pF

19.2 pF

ANALOG

FILTER

6

RF-ZERO + DC

C6

DR1

C5

OP1

V

ref

R8

2.8 kΩ

V

ref

DAC6

PCF5077T

R10

4.2 kΩ

DR0

R9

2.8 kΩ

HPA + DC

V

INT(N)

R3

3.5 kΩ

HPA

V

INPUT BUFFER

ref

8.4 kΩ

R5

5

kΩ

1/6

C1

HPA + DC

R4

COMPARATOR

PCF5077T

voltage

control for

RF power module

V

OP4

CONTROL

INT(O)

2 9 10 11 1213 3 16 6

V

SSD

V

DDA1

DF STROBE

CLK

DATA

V

SSA

Fig.1 Block diagram.

1997 Nov 19 3

V

DDA2

V

DDD

CLK13

5

8

TRIG

7

MGK910

PD

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and
PCN systems

PINNING

SYMBOL PIN DESCRIPTION

VS 1 sensor signal input
DF 2 programmable 3-state output
V

DDA1

BVS 4 buffered sensor signal output
TRIG 5 trigger signal input
V

DDD

PD 7 power-down input (active LOW)
CLK13 8 13 MHz master clock input

STROBE 9 serial bus strobe signal input
CLK 10 serial bus clock signal input
DATA 11 serial bus data signal input
V

SSD

V

SSA

V

INT(O)

V

INT(N)

V

DDA2

3 analog supply voltage 1

6 digital supply voltage

(low-swing)

12 digital ground
13 analog ground
14 integrator output
15 integrator inverting input
16 analog supply voltage 2 (for OP4)

handbook, halfpage

VS

1

DF

2

V

DDA1

BVS

TRIG

V

DDD

PD

CLK13

3
4

PCF5077T

5
6
7
8

MGK909

Fig.2 Pin configuration.

PCF5077T

V

16

DDA2

V

15

INT(N)

V

14

INT(O)

V

13

SSA

V

12

SSD

11

DATA

10

CLK

9

STROBE

FUNCTIONAL DESCRIPTION
General

This CMOS device integrates operational amplifiers, two
digital-to-analog converters and a serial bus interface to
implement an ‘Integrating-Controller’ (see Fig.1). It is
designed to control both the power level and the up- and
down-ramping of GSM/PCN transmit bursts.

The GSM/PCN power-up and power-down ramping curves
are generated on-chip, using an internal clock frequency of

2.166 MHz , that is generated internally by




1

=

T

------ -

cy

f

clk

dividing the external 13 MHz clock signal by six.
Generally, the power amplifier is ramped-up after a rising

edge on pin TRIG and ramped-down after a falling edge.
The content of the power level register (bits PL7 to PL0)

determines which of the 2 × 256 possible values the top of
the burst will have.

To match the controller to different power modules and
sensors several parameters must be adapted.
The following parameters influence the performance of the
transmission system:

• The external capacitor C1 in Fig.1 determines the
maximum bandwidth of the power control loop,

depending on the highest steepness of the control curve
of the power module and on the sensor attenuation.

• The maximum output voltage at pin V
power module: the limiting value of V

to protect the

INT(O)

can be set to

INT(O)

4, 3.3 or 2.55 V, depending on the contents of the limiter
register (bits Lim1 and Lim0). This limiting results in a
ringing at V

(typ. 200 mV peak-to-peak value) but it

INT(O)

will not be transferred to the antenna because the power
module is in saturation. The limiter register bits Lim1
and Lim0 can be used to switch off the limiter option
(see Table 5).

• The home position at V
voltage at home position (

is programmed by means of the V

: the integrator output

INT(O)

PD = HIGH and TRIG = LOW)

register.

HOME

Bits Vh5 to Vh0 are fed into a 6-bit DAC that generates
a part of V

HOME

.

• The temperature behaviour of the home position:
bits DVh1 and DVh0 can be used to compensate
temperature dependencies (−2or−4 mV/K) of the
control curves of the power module. This completes the
setting of V

• The KICK voltage: the 6 bits of the V

HOME

.

register

KICK

(Vk5 to Vk0) determine the differential integrator input
voltage just after a ramp-up starting signal is detected.

1997 Nov 19 4

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and
PCN systems

The register information is written via a 3-wire serial bus
(see Sections “Serial bus programming” and “Data
format”).

The output of pin DF is for general purpose which can
have three different states (LOW, HIGH and 3-state),
depending on the values of bits DF0 and DF1 in the serial
register.

Dual supply pins are provided for the analog and digital
blocks.

Reset function

After switching on the power supply, the on-chip reset is
active for maximal 50 µs when the rising slope of V
reached 1.5 ±0.4 V. During this reset, all controllers are
set to the home position and the registers are set to their
default values. If the supply voltage drops below the reset
threshold a constant reset will appear.

Operating conditions

DDD

has

PCF5077T

When the chip is used in the burst mode, it is important to
switch on the PCF5077T before the power module or the
RF power. Otherwise it is possible that a positive spike at

will open the power module.

V

INT(O)

A safe value is tON= 200 µs between the switching on of
the PCF5077T and the switching on of the power module
respectively the next TRIG (see Fig.3).

PD = HIGH
The whole chip is active. CLK13 clocks the internal state

machine as well as the SC-adder and slope generator.
Every change at TRIG is recognized if the master clock is
running. The contents of the serial bus registers are
processed. If the master clock is switched off during
power-up, the state machine is stopped and the output of
the SC-adder and slope generator becomes undefined.
Nevertheless, by reactivating the master clock, the output
of the SC-adder and slope generator will settle to the old
values again.

PD = LOW
The serial bus interface is operating, e.g. all registers can

be programmed but no effect will be seen on any pin.
The contents of the registers are passed to the rest of the
circuit only during power-up and with the 13 MHz master
clock applied.

If the low-swing input buffer at pin CLK13 is switched off,
neither the SC-adder nor the slope generator will function.
This means that after the chip is powered-up, the outputs
have to settle again to the programmed register values.
The settling time is dominated by the slow power-up of the
band gap of typically 50 µs.

The analog integrating controller

The analog integrating controller consists of two
operational amplifiers (OP1 and OP4) and a comparator.
OP1 amplifies the sensor signal and OP4 is used to form
a differential integrator. The comparator is used to limit the
integrator output voltage to the value selected by bits Lim1
and Lim0 in the limiter register.

A (Schottky) diode D1 as external rectifier is connected to
pin VS. The SC-adder block generates the voltage for the
ramping of the power module.The differential integrator
integrates the difference of this voltage and the voltage
detected at the diode. The integrator output voltage V
is used to control the power amplifier module.

INT(O)

1997 Nov 19 5

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and
PCN systems

Table 1 Definition of some voltages used in Figs 1 and 3

SYMBOL DESCRIPTION

V

ref

V

D1

V

PL

V

VS

V

BVS

V

KICK

V

HOME

V

QRS

V

RFIN

Ramp generation (see Fig.3) The circuit is activated with the PD signal going HIGH

before time mask AS and deactivated after ramping down,
e.g. at time GS to HS. For this usual ‘power-down burst
mode’ application in GSM/PCN mobile stations, the RF
input power at the power module must be activated
between time AS and BS (when the home position at
V

has already reached its stable value) and

INT(O)

deactivated between time GS and HS. This is necessary
for many types of power modules to meet the −70 dB
margin.

A ramp-up is started by a rising edge of the TRIG signal.
The TRIG signal and all other internal signals are delayed
by two clock periods (2T
pin TRIG.

The timing diagram shows a possible relationship between
the chip timing (time B to G) relative to the GSM-mask
(AS to HS). However, the user is free to choose the rising
and falling edge of TRIG independently so that the mask is
not violated.

ESCRIPTION OF THE SIGNALS STARTING AT A STABLE HOME

D

POSITION OF

The integrator output voltage is regulated to the value
defined in the V
generator is connected to the negative input V
operational amplifier OP4 (V
bits Vk5 to Vk0 in the V
after a rising edge on pin TRIG, the integrator start
condition circuitry is turned off and OP4 is switched into an
integrator configuration (time B). The HPA switches will

reference voltage, typically 1.25 V
voltage over the sensor diode D1
voltage determining the power level; it is generated in the Switched Capacitor (SC)-adder block if

switch DACA is closed (i.e. if the signal DACA is HIGH)
voltage at pin VS when RF is rectified by the sensor diode D1
amplified voltage from pin VS
voltage determining the kick level; it is generated in the SC-adder block if switch KICKA is closed (i.e.

if the signal KICKA is HIGH)
voltage determining the home position voltage; if HPA signal is active, the output of DAC6 plus

temperature compensation is amplified and appears at the output of OP4 (pin V
low voltage at the output of the SC-adder block which causes a ramp-down with a shortened tail if

switch QRSA is closed (i.e. if the signal QRSA is HIGH)
input signal to the power amplifier

open (HPA + DC is either HPA switch or DC bit).
Switch
Due to the negative differential input voltage V
integrator output will start to rise. After 18Tcy (time C) the
output of DAC8 is connected to the SC-adder and slope
generator block. The input of the 8-bit DAC comes from
bits PL7 to PL0 in the power level register. The slope
generator will generate a smooth curve between the
former and the new output value of the SC-adder block.
The power amplifier is ramped-up via the integrator in
approximately 22Tcy.

This condition is stable as long as TRIG remains HIGH.
Two clock periods after a falling edge at TRIG the

) with respect to the signal at

cy

ramp-down is started (time E). The SC-adder output
voltage will change to V
becomes inactive and QRSA active. This causes a
ramp-down with a shortened tail. The slope generator
again generates a smooth curve between the new
SC-adder output voltage and the old SC-adder output
voltage.

The slope generator must have reached its final value at
38Tcy after the recognized falling edge of TRIG because

V

AT TIME B − 2T

INT(O)

cy

the HPA signal is activated again and by that turning the
integrator into its ‘home position’ (time G). The integrator
output voltage will be regulated once more to the value

register. The output of the slope

HOME

is defined by

KICK

register). Two clock periods

KICK

INT(N)

of

defined in the V

PCF5077T

)

INT(O)

HPA is closed when there is no home position.

, the

KICK

(−100 mV), because DACA

QRS

register.

HOME

1997 Nov 19 6

Philips Semiconductors Preliminary specification

,

,

,

,

,

Power amplifier controller for GSM and
PCN systems

handbook, full pagewidth

dB

30

70

t

4
1
1
6

ON

AS BS CS DS ES FS GS HS

2T

22T

cy

18T

cy

B

18T

cy

22T

cy

t

cy

1

C

200 µs

t

,,

,,

,,

,,

,,

E

2T

cy

2

22T

(2Tcy)(8Tcy)

38T

t

OFF

PCF5077T

18T

cy

cy

44T

cy

22T

cy

cy

G

TRIG

PD

KICKA

HPA

QRSA

DACA

RFIN

(7)

RF-ZERO

(1) t
(2) t
(3) V

(1)

RFON=tON
RFOFF

KICK

− 12Tcyto tON+2Tcy.

= 44Tcyto 66Tcy.

(start integrator) applied to integrator.

(3) (4) (5) (6)

(2)

MGK912

(4) VPL applied to integrator.
(5) V
(6) V

applied to integrator.

QRS

at output of OP4.

HOME

(7) This timing of the RF input power (from the power module) ensures that the −70dB margin is met, even if the isolation of the power module is bad.

Fig.3 Timing diagram of a typical ramp-up/ramp-down curve.

1997 Nov 19 7

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and

PCF5077T

PCN systems

Serial bus programming

A simple 3-wire unidirectional serial bus is used to program
the circuit. The 3 wires are DATA, CLK and STROBE.
The data sent to the device is loaded in bursts framed by
STROBE. Programming clock edges and their appropriate
data bits are ignored until STROBE goes active LOW.

The last four address bits are decoded on the active
STROBE edge. This produces an internal load pulse to
store the data in one of the addressed registers. To avoid
erroneous circuit operation, the STROBE pulse is not
allowed during internal data reads by the rest of the circuit.
This condition is guaranteed by respecting a minimum
STROBE pulse width after data transfer.

Only the last 16 bits serially clocked into the device are
retained within the programming register. Additional

Table 2 Programming register format

DATA BITS

MSB LSB

p15 p14 to p8 p7 p6 p5 p4 p3 p2 p1 p0

data9 data8 to data2 data1 data0 Sadd1 Sadd0 add3 add2 add1 add0

leading bits are ignored, and no check is made on the
number of clock pulses. The fully static CMOS design uses
virtually no current when the bus is inactive. The bus is
also programmable during power-down.

Data format

Data is entered with the most significant bit (MSB) first.
The leading 10 bits p15 to p6 are the data field, the
following bits p5 and p4 form the subaddress, while the
last 4 bits p3 to p0 are the device address field.
The PCF5077T uses only one of the available addresses.
The format is given in Table 2.

The correspondence between data and address fields is
given in Table 3 and the description in Table 4.

All three registers in Table 3 are set to 00H during reset.

SUBADDRESS DEVICE ADDRESS

Table 3 Register bit allocation

DATA FIELD (D9 TO D0)

MSB LSB

p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0
Vk5 Vk4 Vk3 Vk2 Vk1 Vk0 Lim1 Lim0 DC Test 0 0 1 0 1 0
Vh5 Vh4 Vh3 Vh2 Vh1 Vh0 DVh1 DVh0 DR1 DR0 0 1 1 0 1 0
PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 DF1 DF0 1 1 1 0 1 0

Table 4 Description of bits used in Table 3

BITS DESCRIPTION

Vk5 to Vk0 6 bits to control the kick voltage in 64 steps
Vh5 to Vh0 6 bits to control the home position voltage in 64 steps
PL7 to PL0 8 bits to control the power level in 256 steps
Lim1 and Lim0 2 bits to control the limiter voltage (see Table 5)
DC direct control with ramping function (control loop is switched off when DC = 1)
Test test mode (Test = 1); must always be set to logic 0 in application
DVh1 and DVh0 2 bits to set the temperature coefficient of V
DR1 gain factor of OP1
DR0 gain factor for slope generator output
DF1 enable of the 3-state output on pin DF (for DF1 = 0, pin DF is in 3-state mode)
DF0 data output on pin DF

HOME

SUBADDRESS DEVICE ADDRESS

(see Table 6)

1997 Nov 19 8