Philips PCF5077T Datasheet

INTEGRATED CIRCUITS

DATA SH EET

PCF5077T

Power amplifier controller for GSM
and PCN systems

Preliminary specification
File under Integrated Circuits, IC17

1997 Nov 19

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and
PCN systems

FEATURES

• CMOS low-voltage, low-power

• Can be used in burst mode with power-down

• 3-wire serial bus interface with the bus available in

Power-down mode

• On-chip ramp generator for 256 different power levels
with two dynamic ranges

• Two programmable regulator start conditions (V
and V

HOME

)

• Programmable analog output voltage limitation

• Ramping speed depending on the 13 MHz system

frequency clock for Global System for Mobile
communications (GSM) and Personal Communications
Network (PCN)

• Low swing input buffer for the 13 MHz master clock

• Compatible to a large number of different RF power

modules

KICK

PCF5077T

• Programmable temperature matching

• Dual supply concept for analog and digital part

• No external filter for suppression of clock pulse feed

through

• Direct power control with ramping function (control loop
can be switched off)

• On-chip Power-on reset for all registers

• Serial bus is compatible to bus systems independent of

additional clock pulse after rising edge of strobe signal

• Low operating current consumption

• TTL compatible interface

• Programmable gain factor for sensor signal at OP1

• Two different voltages for 1 LSB of the burst power

Digital-to-Analog Converter (DAC) are programmable.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DDD

V

DDA1

V

DDA2

I

DD(oper)(tot)

T

amb

digital supply voltage note 1 2.7 3.0 6.0 V
analog supply voltage 1 note 1 2.7 3.0 6.0 V
analog supply voltage 2 (for OP4) 2.7 5.0 6.0 V
total operating current on the VDD pins note 2 − 918mA
operating ambient temperature −40 − +85 °C

Notes

1. The voltages V

2. V

DDA1=VDDD

and V

DDA1

= 3 V and V

must be equal and V

DDD

= 5 V. The VDD pins are: V

DDA2

must be either equal or greater than V

DDA2

DDA1

, V

DDA2

and V

DDD

.

DDA1=VDDD

.

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

PCF5077T SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1

1997 Nov 19 2

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and
PCN systems

BLOCK DIAGRAM

handbook, full pagewidth

RF input
(sensor)

BAND GAP

I

bias

V

8

QRSA

DACA

KICKA

ref

DAC8

V

ref

100
mV

POWER LEVEL REGISTER
V

KICK

V

HOME
LIMITER REGISTER
DF0/1, DC, DR0/1, TEST

SERIAL BUS INTERFACE

C2

V

D1

30 µA

DACA KICKA QRSA

−0.8 −0.33 +0.33

SLOPE GENERATOR

REGISTER

REGISTER

D1

V

DDA1

SC-ADDER

VS BVS
1 4 15 14

8-bit
6-bit

6 + 2-bit

2-bit

R1

R2
1 kΩ

10 pF

C4

4.8 pF

19.2 pF

ANALOG

FILTER

6

RF-ZERO + DC

C6

DR1

C5

OP1

V

ref

R8

2.8 kΩ

V

ref

DAC6

PCF5077T

R10

4.2 kΩ

DR0

R9

2.8 kΩ

HPA + DC

V

INT(N)

R3

3.5 kΩ

HPA

V

INPUT BUFFER

ref

8.4 kΩ

R5

5

kΩ

1/6

C1

HPA + DC

R4

COMPARATOR

PCF5077T

voltage

control for

RF power module

V

OP4

CONTROL

INT(O)

2 9 10 11 1213 3 16 6

V

SSD

V

DDA1

DF STROBE

CLK

DATA

V

SSA

Fig.1 Block diagram.

1997 Nov 19 3

V

DDA2

V

DDD

CLK13

5

8

TRIG

7

MGK910

PD

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and
PCN systems

PINNING

SYMBOL PIN DESCRIPTION

VS 1 sensor signal input
DF 2 programmable 3-state output
V

DDA1

BVS 4 buffered sensor signal output
TRIG 5 trigger signal input
V

DDD

PD 7 power-down input (active LOW)
CLK13 8 13 MHz master clock input

STROBE 9 serial bus strobe signal input
CLK 10 serial bus clock signal input
DATA 11 serial bus data signal input
V

SSD

V

SSA

V

INT(O)

V

INT(N)

V

DDA2

3 analog supply voltage 1

6 digital supply voltage

(low-swing)

12 digital ground
13 analog ground
14 integrator output
15 integrator inverting input
16 analog supply voltage 2 (for OP4)

handbook, halfpage

VS

1

DF

2

V

DDA1

BVS

TRIG

V

DDD

PD

CLK13

3
4

PCF5077T

5
6
7
8

MGK909

Fig.2 Pin configuration.

PCF5077T

V

16

DDA2

V

15

INT(N)

V

14

INT(O)

V

13

SSA

V

12

SSD

11

DATA

10

CLK

9

STROBE

FUNCTIONAL DESCRIPTION
General

This CMOS device integrates operational amplifiers, two
digital-to-analog converters and a serial bus interface to
implement an ‘Integrating-Controller’ (see Fig.1). It is
designed to control both the power level and the up- and
down-ramping of GSM/PCN transmit bursts.

The GSM/PCN power-up and power-down ramping curves
are generated on-chip, using an internal clock frequency of

2.166 MHz , that is generated internally by




1

=

T

------ -

cy

f

clk

dividing the external 13 MHz clock signal by six.
Generally, the power amplifier is ramped-up after a rising

edge on pin TRIG and ramped-down after a falling edge.
The content of the power level register (bits PL7 to PL0)

determines which of the 2 × 256 possible values the top of
the burst will have.

To match the controller to different power modules and
sensors several parameters must be adapted.
The following parameters influence the performance of the
transmission system:

• The external capacitor C1 in Fig.1 determines the
maximum bandwidth of the power control loop,

depending on the highest steepness of the control curve
of the power module and on the sensor attenuation.

• The maximum output voltage at pin V
power module: the limiting value of V

to protect the

INT(O)

can be set to

INT(O)

4, 3.3 or 2.55 V, depending on the contents of the limiter
register (bits Lim1 and Lim0). This limiting results in a
ringing at V

(typ. 200 mV peak-to-peak value) but it

INT(O)

will not be transferred to the antenna because the power
module is in saturation. The limiter register bits Lim1
and Lim0 can be used to switch off the limiter option
(see Table 5).

• The home position at V
voltage at home position (

is programmed by means of the V

: the integrator output

INT(O)

PD = HIGH and TRIG = LOW)

register.

HOME

Bits Vh5 to Vh0 are fed into a 6-bit DAC that generates
a part of V

HOME

.

• The temperature behaviour of the home position:
bits DVh1 and DVh0 can be used to compensate
temperature dependencies (−2or−4 mV/K) of the
control curves of the power module. This completes the
setting of V

• The KICK voltage: the 6 bits of the V

HOME

.

register

KICK

(Vk5 to Vk0) determine the differential integrator input
voltage just after a ramp-up starting signal is detected.

1997 Nov 19 4

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and
PCN systems

The register information is written via a 3-wire serial bus
(see Sections “Serial bus programming” and “Data
format”).

The output of pin DF is for general purpose which can
have three different states (LOW, HIGH and 3-state),
depending on the values of bits DF0 and DF1 in the serial
register.

Dual supply pins are provided for the analog and digital
blocks.

Reset function

After switching on the power supply, the on-chip reset is
active for maximal 50 µs when the rising slope of V
reached 1.5 ±0.4 V. During this reset, all controllers are
set to the home position and the registers are set to their
default values. If the supply voltage drops below the reset
threshold a constant reset will appear.

Operating conditions

DDD

has

PCF5077T

When the chip is used in the burst mode, it is important to
switch on the PCF5077T before the power module or the
RF power. Otherwise it is possible that a positive spike at

will open the power module.

V

INT(O)

A safe value is tON= 200 µs between the switching on of
the PCF5077T and the switching on of the power module
respectively the next TRIG (see Fig.3).

PD = HIGH
The whole chip is active. CLK13 clocks the internal state

machine as well as the SC-adder and slope generator.
Every change at TRIG is recognized if the master clock is
running. The contents of the serial bus registers are
processed. If the master clock is switched off during
power-up, the state machine is stopped and the output of
the SC-adder and slope generator becomes undefined.
Nevertheless, by reactivating the master clock, the output
of the SC-adder and slope generator will settle to the old
values again.

PD = LOW
The serial bus interface is operating, e.g. all registers can

be programmed but no effect will be seen on any pin.
The contents of the registers are passed to the rest of the
circuit only during power-up and with the 13 MHz master
clock applied.

If the low-swing input buffer at pin CLK13 is switched off,
neither the SC-adder nor the slope generator will function.
This means that after the chip is powered-up, the outputs
have to settle again to the programmed register values.
The settling time is dominated by the slow power-up of the
band gap of typically 50 µs.

The analog integrating controller

The analog integrating controller consists of two
operational amplifiers (OP1 and OP4) and a comparator.
OP1 amplifies the sensor signal and OP4 is used to form
a differential integrator. The comparator is used to limit the
integrator output voltage to the value selected by bits Lim1
and Lim0 in the limiter register.

A (Schottky) diode D1 as external rectifier is connected to
pin VS. The SC-adder block generates the voltage for the
ramping of the power module.The differential integrator
integrates the difference of this voltage and the voltage
detected at the diode. The integrator output voltage V
is used to control the power amplifier module.

INT(O)

1997 Nov 19 5

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and
PCN systems

Table 1 Definition of some voltages used in Figs 1 and 3

SYMBOL DESCRIPTION

V

ref

V

D1

V

PL

V

VS

V

BVS

V

KICK

V

HOME

V

QRS

V

RFIN

Ramp generation (see Fig.3) The circuit is activated with the PD signal going HIGH

before time mask AS and deactivated after ramping down,
e.g. at time GS to HS. For this usual ‘power-down burst
mode’ application in GSM/PCN mobile stations, the RF
input power at the power module must be activated
between time AS and BS (when the home position at
V

has already reached its stable value) and

INT(O)

deactivated between time GS and HS. This is necessary
for many types of power modules to meet the −70 dB
margin.

A ramp-up is started by a rising edge of the TRIG signal.
The TRIG signal and all other internal signals are delayed
by two clock periods (2T
pin TRIG.

The timing diagram shows a possible relationship between
the chip timing (time B to G) relative to the GSM-mask
(AS to HS). However, the user is free to choose the rising
and falling edge of TRIG independently so that the mask is
not violated.

ESCRIPTION OF THE SIGNALS STARTING AT A STABLE HOME

D

POSITION OF

The integrator output voltage is regulated to the value
defined in the V
generator is connected to the negative input V
operational amplifier OP4 (V
bits Vk5 to Vk0 in the V
after a rising edge on pin TRIG, the integrator start
condition circuitry is turned off and OP4 is switched into an
integrator configuration (time B). The HPA switches will

reference voltage, typically 1.25 V
voltage over the sensor diode D1
voltage determining the power level; it is generated in the Switched Capacitor (SC)-adder block if

switch DACA is closed (i.e. if the signal DACA is HIGH)
voltage at pin VS when RF is rectified by the sensor diode D1
amplified voltage from pin VS
voltage determining the kick level; it is generated in the SC-adder block if switch KICKA is closed (i.e.

if the signal KICKA is HIGH)
voltage determining the home position voltage; if HPA signal is active, the output of DAC6 plus

temperature compensation is amplified and appears at the output of OP4 (pin V
low voltage at the output of the SC-adder block which causes a ramp-down with a shortened tail if

switch QRSA is closed (i.e. if the signal QRSA is HIGH)
input signal to the power amplifier

open (HPA + DC is either HPA switch or DC bit).
Switch
Due to the negative differential input voltage V
integrator output will start to rise. After 18Tcy (time C) the
output of DAC8 is connected to the SC-adder and slope
generator block. The input of the 8-bit DAC comes from
bits PL7 to PL0 in the power level register. The slope
generator will generate a smooth curve between the
former and the new output value of the SC-adder block.
The power amplifier is ramped-up via the integrator in
approximately 22Tcy.

This condition is stable as long as TRIG remains HIGH.
Two clock periods after a falling edge at TRIG the

) with respect to the signal at

cy

ramp-down is started (time E). The SC-adder output
voltage will change to V
becomes inactive and QRSA active. This causes a
ramp-down with a shortened tail. The slope generator
again generates a smooth curve between the new
SC-adder output voltage and the old SC-adder output
voltage.

The slope generator must have reached its final value at
38Tcy after the recognized falling edge of TRIG because

V

AT TIME B − 2T

INT(O)

cy

the HPA signal is activated again and by that turning the
integrator into its ‘home position’ (time G). The integrator
output voltage will be regulated once more to the value

register. The output of the slope

HOME

is defined by

KICK

register). Two clock periods

KICK

INT(N)

of

defined in the V

PCF5077T

)

INT(O)

HPA is closed when there is no home position.

, the

KICK

(−100 mV), because DACA

QRS

register.

HOME

1997 Nov 19 6

Philips Semiconductors Preliminary specification

,

,

,

,

,

Power amplifier controller for GSM and
PCN systems

handbook, full pagewidth

dB

30

70

t

4
1
1
6

ON

AS BS CS DS ES FS GS HS

2T

22T

cy

18T

cy

B

18T

cy

22T

cy

t

cy

1

C

200 µs

t

,,

,,

,,

,,

,,

E

2T

cy

2

22T

(2Tcy)(8Tcy)

38T

t

OFF

PCF5077T

18T

cy

cy

44T

cy

22T

cy

cy

G

TRIG

PD

KICKA

HPA

QRSA

DACA

RFIN

(7)

RF-ZERO

(1) t
(2) t
(3) V

(1)

RFON=tON
RFOFF

KICK

− 12Tcyto tON+2Tcy.

= 44Tcyto 66Tcy.

(start integrator) applied to integrator.

(3) (4) (5) (6)

(2)

MGK912

(4) VPL applied to integrator.
(5) V
(6) V

applied to integrator.

QRS

at output of OP4.

HOME

(7) This timing of the RF input power (from the power module) ensures that the −70dB margin is met, even if the isolation of the power module is bad.

Fig.3 Timing diagram of a typical ramp-up/ramp-down curve.

1997 Nov 19 7

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and

PCF5077T

PCN systems

Serial bus programming

A simple 3-wire unidirectional serial bus is used to program
the circuit. The 3 wires are DATA, CLK and STROBE.
The data sent to the device is loaded in bursts framed by
STROBE. Programming clock edges and their appropriate
data bits are ignored until STROBE goes active LOW.

The last four address bits are decoded on the active
STROBE edge. This produces an internal load pulse to
store the data in one of the addressed registers. To avoid
erroneous circuit operation, the STROBE pulse is not
allowed during internal data reads by the rest of the circuit.
This condition is guaranteed by respecting a minimum
STROBE pulse width after data transfer.

Only the last 16 bits serially clocked into the device are
retained within the programming register. Additional

Table 2 Programming register format

DATA BITS

MSB LSB

p15 p14 to p8 p7 p6 p5 p4 p3 p2 p1 p0

data9 data8 to data2 data1 data0 Sadd1 Sadd0 add3 add2 add1 add0

leading bits are ignored, and no check is made on the
number of clock pulses. The fully static CMOS design uses
virtually no current when the bus is inactive. The bus is
also programmable during power-down.

Data format

Data is entered with the most significant bit (MSB) first.
The leading 10 bits p15 to p6 are the data field, the
following bits p5 and p4 form the subaddress, while the
last 4 bits p3 to p0 are the device address field.
The PCF5077T uses only one of the available addresses.
The format is given in Table 2.

The correspondence between data and address fields is
given in Table 3 and the description in Table 4.

All three registers in Table 3 are set to 00H during reset.

SUBADDRESS DEVICE ADDRESS

Table 3 Register bit allocation

DATA FIELD (D9 TO D0)

MSB LSB

p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0
Vk5 Vk4 Vk3 Vk2 Vk1 Vk0 Lim1 Lim0 DC Test 0 0 1 0 1 0
Vh5 Vh4 Vh3 Vh2 Vh1 Vh0 DVh1 DVh0 DR1 DR0 0 1 1 0 1 0
PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 DF1 DF0 1 1 1 0 1 0

Table 4 Description of bits used in Table 3

BITS DESCRIPTION

Vk5 to Vk0 6 bits to control the kick voltage in 64 steps
Vh5 to Vh0 6 bits to control the home position voltage in 64 steps
PL7 to PL0 8 bits to control the power level in 256 steps
Lim1 and Lim0 2 bits to control the limiter voltage (see Table 5)
DC direct control with ramping function (control loop is switched off when DC = 1)
Test test mode (Test = 1); must always be set to logic 0 in application
DVh1 and DVh0 2 bits to set the temperature coefficient of V
DR1 gain factor of OP1
DR0 gain factor for slope generator output
DF1 enable of the 3-state output on pin DF (for DF1 = 0, pin DF is in 3-state mode)
DF0 data output on pin DF

HOME

SUBADDRESS DEVICE ADDRESS

(see Table 6)

1997 Nov 19 8

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and

PCF5077T

PCN systems

Table 5 Limiter voltage

Lim1 Lim0

LIMITER VOLTAGE

(V)

0 0 limiter off −−
0 1 4.00 ±250 ±350
1 0 3.30 ±250 ±350
1 1 2.55 ±250 ±350

Table 6 Programmable temperature coefficient of V

DVh1 DVh0 V

00Vh±0.4 mV/K
01Vh−2 mV/K ±20%
10Vh−4 mV/K ±20%
11V

Note

1. Vh = voltage programmed in V

HOME

TOLERANCE AT T

amb

=27°C

TOLERANCE AT T

(mV)

HOME

register bits Vh5 to Vh0 and generated by DAC6.

(mV)

HOME

SS

(1)

amb

=85°C

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V
V
V
V
V
I
P
T
T

I(n)

DDA1
DDA2
DDD
I
I(VS)

tot
stg
amb

analog supply voltage 1 −0.5 +6.0
analog supply voltage 2 −0.5 +6.0
digital supply voltage −0.5 +6.0
DC input voltage on all pins (except pin VS) −0.5 VDD+ 0.5 V
DC input voltage on pin VS −3.0 VDD+ 0.5 V
DC input current on any signal pin −10 +10 mA
total power dissipation − 83 mW
storage temperature −65 +150 °C
operating ambient temperature −40 +85 °C

(1)
(1)
(1)

Note

1. Pulses of 7 V are allowed for less than 100 ms.

V
V
V

1997 Nov 19 9

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and

PCF5077T

PCN systems

OPERATING CHARACTERISTICS

V

DDA1,VDDA2

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Operational amplifier (OP1)

V

DDA1

GB gain bandwidth product V
G

min

G

max

V

offset

Operational amplifier (OP4)

V

DDA2

GB gain bandwidth product C

PSRR power supply rejection ratio V
SR

pos

SR

neg

V

offset

V

o(min)

V

o(max)

I

o

Programmability and accuracy of V

INL integral non-linearity −±1.5 ±10 LSB
DNL differential non-linearity −±0.2 ±1 LSB
V

o(min)

V

o(max)

STS step size DC = 1; DR0 = 1 − 6 − mV

and V

DDD=VDD

= 2.7 to 6.0 V; V

DDD=VDDA1

≤ V

DDA2

; T

= −40 to +85 °C; unless otherwise specified.

amb

analog supply voltage 1 2.7 3.0 6.0 V

= 3.0 V 2.0 −−MHz

DDA1

minimum gain DR1 = 0 −8.1 −7.6 −7.1 dB
maximum gain DR1 = 1 5.9 6.4 6.9 dB
offset voltage no load at output −20 0 +20 mV

analog supply voltage 2 2.7 5.0 6

= 120 pF; V

L

DDA2

=5V;

4 −−MHz

(1)

note 2

(3)

55 − dB
positive slew rate V
negative slew rate V

= 5 V, at 217 Hz 50

DDA2

= 5 V; note 4 3.5 15 − V/µs

DDA2

= 5 V; note 4 3.5 6 − V/µs

DDA2

voltage offset no load at output −20 0 +20 mV
minimum output voltage −−0.3 V
maximum output voltage 0.85V

DDA2

−−V

output current note 5 4.5 −−mA

(DAC8) at V

PL

INT(O)

minimum output voltage DC = 1; DR0 = 1; note 6 −30 − +60 mV
maximum output voltage DC = 1; DR0 = 0; note 6 2.72 − 3.15 V

DC = 1; DR0 = 0 − 11.7 − mV

V

Programmability and accuracy of V

V

o(min)

V

o(max)

minimum output voltage DC = 1; DR0 = 1; note 6 −50 − +50 mV
maximum output voltage DC = 1; DR0 = 0; note 6 270 − 400 mV

(DAC8) at V

KICK

INT(O)

STS step size DC = 1; DR0 = 1 − 2.6 − mV

DC = 1; DR0 = 0 − 5.0 − mV

1997 Nov 19 10

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and

PCF5077T

PCN systems

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Programmability and accuracy of V

INL integral non-linearity note 7 −±1.0 ±3 LSB
DNL differential non-linearity note 7 −±0.2 ±1 LSB
V

o(min)

V

o(max)

minimum output voltage DVh1 = 0; DVh0 = 0 50 − 170 mV
maximum output voltage DVh1 = 0; DVh0 = 0 1.95 − 2.25 V

STS step size − 33 − mV

Notes

1. Pulses of 7 V are allowed for less than 100 ms.

2. Minimum specified frequency at T

3. Not tested. Guaranteed by design.

4. Slew rates are measured between 10% and 90% of output voltage with a load of approximately 40 pF to ground.

5. Measured with RL= 1.2 kΩ, CL= 80 pF and V

6. Referred to V

; nominal operating condition, direct control (DC = 1), V

HOME

7. The parameter is measured starting from code 4, due to a saturation effect for the first four codes.

(DAC6) at V

HOME

=27°C. For T

amb

INT(O)

=85°C a typical value of 4 MHz is specified.

amb

= 5 V. The voltage drop at the output is less than 20 mV.

DDA2

programmed to 40.

HOME

1997 Nov 19 11

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and

PCF5077T

PCN systems

DC CHARACTERISTICS

V

DDA1,VDDA2

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DDD

V

DDA1

V

DDA2

I

DD(oper)(tot)

I

DD(idle)(tot)

Logic inputs (pins TRIG, STROBE, CLK and DATA)

I

LIL

I

LIH

C

i

V

IL

V

IH

3-state output (pin DF)

V

OL

V

OH

I

LO

Low-swing master clock input (pin CLK13)

I

Ll

C

i

Z

 input impedance f

i

V

i(p−p)

Sensor input voltage (pin VS)

V

i(VS)

Band gap

I

bias

V

ref

TC temperature coefficient for V
t

pu

Power-on reset, threshold voltage V

V

th

t

rst

and V

DDD=VDD

= 2.7 to 6.0 V; V

DDD=VDDA1

≤ V

DDA2

; T

= −40 to +85 °C; unless otherwise specified.

amb

digital supply voltage 2.7 3.0 6.0 V
analog supply voltage 1 2.7 3.0 6.0 V
analog supply voltage 2 2.7 5.0 6.0 V
total operating current on the VDD pins f

= 13 MHz; see Fig.5 − 918mA

CLK13

total idle current on the VDD pins PD = LOW − 420µA

LOW-level input leakage current VIL=0V −5 − +5 µA
HIGH-level input leakage current VIH=6V −5 − +5 µA
input capacitance − 10 − pF
LOW-level input voltage 0 − 0.2VDDV
HIGH-level input voltage 0.5VDD− V

DD

V

LOW-state output voltage IOL=IOH=3mA −−0.4 V
HIGH-state output voltage IOL=IOH= 3 mA 0.7VDD−−V
3-state output leakage current VDF=0toV

DD

−5 − +5 µA

input leakage current −5 − +5 µA
input capacitance − 10 − pF

= 13 MHz; note 1 − 5 − kΩ

CLK13

input voltage (peak-to-peak value) note 2 0.35 − V

input voltage at pin VS −3.0 − V

bias current (source for D1) VVS=0V; T

amb

=25°C;

21 28 35 µA

DD

DD

V

V

TC = −0.08 µA/K

reference voltage T

ref

power-up time for V

ref

; see Fig.4

th

threshold voltage T

=25°C 1.18 1.25 1.32 V

amb

−±170 − ppm/K

note 3 − 550µs

amb

=25°C;

1.2 1.5 1.8 V

TC = −4 mV/K

reset time −−50 µs

Notes

1. An AC coupling with 33 pF is recommended.

2. Tested at nominal working condition (V

DDD=VDDA1

= 3 V; V

= 5 V). AC coupling = 33 pF.

DDA2

3. The necessary start-up time tON= 200 µs (see Fig.3) between PD and TRIG is more than tpu.

1997 Nov 19 12

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and
PCN systems

handbook, halfpage

V

DDD

< t

internal

reset

rst

PCF5077T

V

th

t

t

MGK914

Fig.4 Timing diagram for on-chip reset function.

handbook, halfpage

8

I

DD

(mA)

6

4

2

0

3456

(1)

(2)

(3)

VDD (V)

MGK916

(1) I

DDA1

. (2) I

DDA2

. (3) I

DDD

.

Fig.5 Operating current IDD as a function of VDD.

1997 Nov 19 13

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and

PCF5077T

PCN systems

TIMING CHARACTERISTICS

V

DDA1,VDDA2

SYMBOL PARAMETER MIN. TYP. UNIT

Controller timing; see Fig.3

t

d(TRIG-B)

t

d(B-C)

t

d(TRIG-E)

t

d(E-G)

Serial bus timing; see Fig.6
S

ERIAL PROGRAMMING CLOCK (PIN CLK)

t

r

t

f

T

cy

ENABLE PROGRAMMING (PIN STROBE)
t

start

t

end

REGISTER SERIAL INPUT DATA (PIN DATA)
t

su

t

h

and V

delay from positive TRIG edge to time B =13⁄6T
delay from time B to time C = 18T
delay from negative TRIG edge to time E =13⁄6T
delay from time E to time G = 38T

= 2.7 to 6.0 V; V

DDD

DDD=VDDA1

cy

cy

≤ V

DDA2

; T

= −40 to +85 °C; unless otherwise specified.

amb

cy

− 1.0 µs

− 8.31 µs

cy

− 1.0 µs

− 17.54 µs

rise time − 10 ns
fall time − 10 ns
clock period 100 − ns

strobe start time to first clock edge 0 − ns
strobe end time after last clock edge 40 − ns

input data to CLK set-up time 20 − ns
input data to CLK hold time 20 − ns

handbook, full pagewidth

CLK

DATA

STROBE

t

start

t

su

MSB

T

cy

t

h

Fig.6 Serial bus timing diagram.

1997 Nov 19 14

LSB

t

end

MGK913

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and
PCN systems

APPLICATION INFORMATION
Direct power control with ramping function (DC = 1)

The circuit offers a useful feature to control power levels
close to the saturation region of the external power
module.

This flexibility consists in the direct control on the power
level by setting bit DC to logic 1.

In this condition, the external control loop is switched off by
disabling the gain path from OP1. The ramping shape of
the signal to be transmitted as well as its final level are
driven only by the internally generated control signal from
the slope generator. In this way transient effects to recover
active components from deep saturation are avoided.
The relative error on the absolute value of output power is
quite limited, as a power amplifier is less sensitive to
temperature variation in its saturated region. However, this
way of operating may increase the phase error.

Increased dynamic range

The PCF5077T is able to control a dynamic range of
30 dBm by switching the gain factor of the sensor amplifier
and the resolution of DAC8. This range corresponds to a
maximum peak-to-peak voltage of 3 V measured at the
sensor diode. Figure 7 shows the voltage at the sensor
diode (V
Amplifier (PA) with a directional coupler of 20 dB
attenuation. The maximum voltage of 3 V is reached when
the output power is 35 dBm.

The sensor voltage for power level lower than 13 dBm, as
necessary for GSM Phase 2 and DCS1800, is lower than
200 mV. An 8-bit DAC would not be sufficient to cover the
complete dynamic range. Therefore bits DR0 and DR1 are
used to switch the power range that can be controlled with
the controller (see Table 7).

EDUCED VOLTAGE STEPS OF POWER LEVEL DAC8

R
(DR0 = 1)

The DR0 bit is used to switch resistor R9 (switch
closed) at the integrator input (OP4). The ratio of the DAC8
range to the sensor signal voltage is therefore halved and
the power corresponding to one LSB of DAC8 is reduced
by 3 dB. With this setting the power module can be
controlled more accurately for low output power levels.

AIN FACTOR OF OP1 (DR1)

G
Bit DR1 switches (switch DR1 is closed) the ratio of the

capacitances at OP1. The gain factor for the sensor
amplifier is five times higher when DR1 is in high state.

) versus the output power (P) of the Power

S

DR0 is

PCF5077T

When DR1 = 1, the control loop regulates the output
power of the PA to a lower power level. A dynamic range
of about 10 dBm can be switched by this manner.

V

s:Vpeak

output voltage effective at the integrator output (OP4).

Table 7 Gain factors

Additional application information

Evaluation kits with software and demonstration board are
available for the PCF5077T together with Philips power
modules BGY206, CGY2010, CGY2020 and CGY2021 for
GSM and PCN, which will provide help for applications.

Very little bus traffic is required for the PCF5077T because
the ramping curves are generated on-chip. V
V

HOME

VPL determines the power levels. TRIG is the trigger for up
and down-ramping.

The non-linear behaviour of the control curves of the
power modules have a big influence on the loop. Start
conditions in the flat area of the control curve are critical
and need some attention. Initially V
home position. The HPA switches release the regulator.
The integrator is moved into the active part of the control
curve. This is achieved by integrating V
has reached the active region of the control curve the loop
is closed and the circuit is able to follow the ramping
function generated by a voltage step to the slope
generator. The step height VPL determines the power of
the transmit burst. Down-ramping is started at the slope
generator input by a voltage step from VPL back to V
The loop follows the leading function for down-ramping
until the RF sensor measures zero. The reason for V
to shorten the tail of the slope.

Figures 8 and 9 show the results of measurements on the
up and down-ramping where REF is the reference level of
the power in the time slot, ATTEN is the attenuation of the
input instrument for not to destroy the instrument itself,
RES BW is the resolution bandwidth, VBW is the video
bandwidth, CENTER is the carrier frequency for the burst
that has been measured and SWP is the sweep time used
for the measurement.

is the ratio of sensor signal to slope generator

DR1 DR0 V

S:Vpeak

0 0 1:1
0 1 2:1
1 0 5:1
1 1 10:1

KICK

define the start conditions for up-ramping.

will be at the

INT(O)

. When V

KICK

and

INT(O)

QRS

QRS

is

.

1997 Nov 19 15

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and
PCN systems

ADJUSTMENT OF THE HOME POSITION
The 6-bit DAC for V

burst in the time template. Curve 2 in Fig.8 shows what
happens when V

HOME

and the up-ramping of the power is too steep. The steep
up-ramping results in a wide transient spectra. The RF
input power shall be switched off when the TRIG signal is
LOW to keep the −70 dB margin before the burst.

The home position has to be adjusted for each mobile
phone because of DAC tolerances and individual PA
characteristics.

The temperature coefficients for V
are used to compensate the temperature shift of the PA
control curve. Therefore the PA and the controller shall be
placed nearby on the printed-circuit board. Additionally it
has to be considered that the temperature of the PA and
PCF5077T are different because the PA heats up itself.
Software may help to adapt V
temperatures.

A

DJUSTMENT OF V

After the falling edge of HPA the integrator starts to
increase the control voltage up to the position of V
where the PA should have reached its active region.
Increasing V

at high power level makes the up ramping

KICK

of the burst smoother and improves the transient spectra.

determines the start point of the

HOME

is too low. The burst starts too late

(−2 and −4 mV/K)

HOME

to different

HOME

KICK

KICK

PCF5077T

must be reduced for low level of VPL to avoid that

V

KICK

both voltages become equal. Setting V
value for the lowest power level can be sufficient.

At low power level the burst will start later because of the
bend sensor curve (see Fig.7). The trigger pulse has to be
started up to 3 bits earlier for the lowest power level to
avoid that the power is ramped up too late for the first data
bits of the burst.

IMIT FOR CORRECT DOWN-RAMPING

L
The maximum RF power that the power module in

saturation is able to deliver depends on RF input power,
transmit frequency, supply voltage, temperature and load
impedance. The maximum V

must be matched to the

PL

worst case output power and then reduced by 1 dB when
the PCF5077T is used in closed loop mode.

Curve 2 in Fig.9 shows what happens when the PA is
driven into saturation. The down-ramping of the power is
getting too steep and therefore the transient spectra will be
too wide. The 1 dB margin is necessary because of the flat
PA control curve at high power level. The loop needs more
time to reduce the power during the down-ramping and the
control voltage increases. The high control voltage forces
the power quickly down when the steep region of the
control curve is achieved. The steep down-ramping results
in a wide transient spectra.

to minimum

KICK

10

handbook, halfpage

V

S

(V)

1

−1

10

−2

10

Fig.7 Sensor voltage as a function of output power (diode BAT62).

1997 Nov 19 16

25 3010 20

MGK915

35−55015

P (dBm)

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and
PCN systems

handbook, full pagewidth

REF 33.4 dBm

LOG

10

dB/

40

CENTER 902.400 MHz

# RES BW 300 kHz # VBW 300 kHz # SWP 80 µs

70 dB

ATTEN 40 dB

30 dB

28

12

18 10 32

6 dB

+4 dB

0 µs

KICK

+1 dB

1 dB

PCF5077T

MBE718

(1) Highest usable value.
(2) Lowest usable value.

Fig.8 Power as a function of time; rising edge (behaviour at different worst case home positions of V

handbook, full pagewidth

REF 34.8 dBm

LOG

10

dB/

CENTER 902.400 MHz

# RES BW 1.0 MHz # VBW 300 kHz # SWP 80 µs

ATTEN 40 dB

2

1

6 dB

30 dB

70 dB

MBE719

591571561553543 µs

INT(O)

).

(1) Correct behaviour.
(2) Unusable behaviour with wrong VPL value.

Fig.9 Power as a function of time; falling edge.

1997 Nov 19 17

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and
PCN systems

Application in mobile stations

Using a directional coupler with 16.5 dB attenuation
produces a sensor signal between 100 mV and 3 V below
the diode forward voltage at pin VS for the PA output
power range of 8 to 36 dBm.

handbook, full pagewidth

antenna

sensor

D1

C3

33 pF

C2

8.2 to 39 pF

R1
1 kΩ

VS

TRIG

PD

CLK13

1
2
3
4

PCF5077T

5
6
7
8

PCF5077T

The sensor voltage of 3 V at pin VS corresponds to the
maximum DAC output voltage. The power range that can
be controlled is therefore not limited by the sensor voltage
input VS and higher power levels can be controlled with
the control loop switched on.

16
15
14
13
12
11
10

9

V

INT(N)

V

INT(O)

V

SSA

V

SSD

DATA
CLK
STROBE

RF POWER
AMPLIFIER

C1

120 pF

3-wire
serial

bus

MGK911

RF

Fig.10 Application diagram for mobile stations.

1997 Nov 19 18

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and
PCN systems

PACKAGE OUTLINE

SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm

16

D

c

y

Z

9

E

H

E

PCF5077T

SOT369-1

A

X

v M

A

pin 1 index

18

w M

b

b

0.32

0.20

p

p

0 2.5 5 mm

cD

0.25

5.30

0.13

5.10

(1)E(1)

4.5

4.3

scale

eHELLpQZywv θ

0.65

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

1.5

0.15

0.00

1.4

1.2

3

0.25

UNIT A1A2A

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

Q

A

2

6.6

6.2

L

0.65

0.45

(A )

L

p

A

1

detail X

0.75

1.0

0.45

3

A

θ

0.130.2 0.1

0.48

0.18

(1)

o

10

o

0

OUTLINE
VERSION

SOT369-1

IEC JEDEC EIAJ

REFERENCES

1997 Nov 19 19

EUROPEAN

PROJECTION

ISSUE DATE

94-04-20
95-02-04

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and
PCN systems

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

Reflow soldering

Reflow soldering techniques are suitable for all SSOP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

Wave soldering

Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

(order code 9398 652 90011).

PCF5077T

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The longitudinal axis of the package footprint must

be parallel to the solder flow and must incorporate
solder thieves at the downstream end.

Even with these conditions, only consider wave
soldering SSOP packages that have a body width of

4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1997 Nov 19 20

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and

PCF5077T

PCN systems

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1997 Nov 19 21

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and
PCN systems

NOTES

PCF5077T

1997 Nov 19 22

Philips Semiconductors Preliminary specification

Power amplifier controller for GSM and
PCN systems

NOTES

PCF5077T

1997 Nov 19 23

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. [phone],

Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
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India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. [phone], Fax. [phone]
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
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04547-130 SÃO PAULO, SP, Brazil,
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Spain: Balmes 22, 08007 BARCELONA,
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Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1997 SCA56
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 437027/1200/01/pp24 Date of release: 1997 Nov 19 Document order number: 9397 750 02733