Philips pcec882 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

PCE84C882

Microcontroller for monitor OSD and auto-sync applications

Preliminary speciﬁcation File under Integrated Circuits, IC14

1996 Jan 08

Philips Semiconductors Preliminary speciﬁcation

Microcontroller for monitor OSD and auto-sync applications

CONTENTS

1 FEATURES

1.1 General

1.2 Special

1.3 OSD 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING INFORMATION

5.1 Pinning

5.2 Pin description 6 RESET

6.1 Reset trip level

6.2 Reset status 7 ANALOG (DC) CONTROL

7.1 6 and 7-bit PWM outputs

7.2 14-bit PWM output

7.3 A typical PWM output application 8 ANALOG-TO-DIGITAL CONVERTER (ADC)

8.1 Conversion algorithm

8.2 Typical ADC application 9 ON SCREEN DISPLAY (OSD)

9.1 Horizontal starting position control

9.2 Vertical starting position control

9.3 Vertical jumping cancelling

9.4 On-chip clock generator 10 DISPLAY RAM ORGANIZATION

10.1 Description of display RAM codes

10.2 Default values of OSD after Power-on-reset

10.3 Loading character data into display RAM

10.4 Writing character data into display RAM 11 CHARACTER ROM

11.1 Character ROM address map

11.2 Character ROM organization

11.3 Combination of character font cells

PCE84C882

12 OSD CONTROL REGISTERS

12.1 Derivative Register 22

12.2 Derivative Register 23

12.3 Derivative Register 33

12.4 Derivative Register 34

12.5 Derivative Register 35

12.6 Derivative Register 36

12.7 Derivative Register 37 13 TO FORMAT THE OSD

13.1 Number of characters per row

13.2 Number of rows per frame

13.3 Character size selection for different display resolutions

14 I2C-BUS INTERFACE 15 8-BIT COUNTER (T3) 16 OUTPUT PORTS

16.1 Mask options

17 DERIVATIVE REGISTERS 18 LIMITING VALUES 19 DC CHARACTERISTICS 20 AC CHARACTERISTICS 21 DEVELOPMENT SUPPORT 22 PACKAGE OUTLINE 23 SOLDERING

23.1 Introduction

23.2 Soldering by dipping or by wave

23.3 Repairing soldered joints

24 DEFINITIONS 25 LIFE SUPPORT APPLICATIONS 26 PURCHASE OF PHILIPS I2C COMPONENTS

1996 Jan 08 2

Philips Semiconductors Preliminary speciﬁcation

Microcontroller for monitor OSD and auto-sync applications

1 FEATURES

1.1 General

• CMOS 8-bit CPU (enhanced 8048 CPU) with 8 kbytes system ROM and 192 bytes system RAM

• One 8-bit timer/event counter (T1) and one 8-bit counter triggered by external input (T3)

• Four single level vectored interrupt sources: external (INTN), counter/timer, I

• 2 directly testable inputs T0 and T1

• On-chip oscillator clock frequency: 1 to 10 MHz

• On-chip Power-on-reset with low power detector

• Twelve quasi-bidirectional I/O lines, configuration of

each I/O line individually selected by mask option

• Idle and Stop modes for reduced power consumption

• Operating temperature: −25 to +85 °C

• Operating voltage: 4.5 to 5.5 V

• Package: SDIP42.

C-bus and VSYNCN

PCE84C882

• Background colours: 8 on a word-by-word basis

• Background/shadowing modes: 4 modes available, No

background, North shadowing, Box shadowing and Frame shadowing (raster blanking) on a frame basis

• On-chip Phase-Locked Loop (PLL) oscillator (auto-sync with Hsync) with programmable oscillator for On Screen Display (OSD) function

• Character blinking frequency: programmable using f

divisors of 16, 32, 64 and 128; on a frame basis

Vsync

• Character blinking ratios: 1 : 1, 1 : 3 and 3 : 1

• Programmable active level polarities of VSYNCN,

HSYNCN, R, G, B and FB

• Flexible display format by using Carriage Return Code

• Auto display RAM address (DCRAR) incremented after

write operation to the Character Data Register (DCRCR)

• VSYNCN generates an interrupt (enabled by software) when VIEN is active.

2 GENERAL DESCRIPTION

1.2 Special

• Master-slave I

• Three 6-bit Pulse Width Modulated outputs

(PWM4; PWM6 and PWM7)

• Four 7-bit Pulse Width Modulated outputs (PWM0 to PWM3)

• One 14-bit Pulse Width Modulated output (PWM8)

• One 4-bit ADC channel

• 14 derivative I/O ports.

1.3 OSD

• Maximum dot frequency (f for details)

• Display RAM: 64 × 10 bits

• Display character fonts: 62 + 2 special reserved codes

• Character matrix: 12 × 18 (no spacing between

characters)

• 4 character sizes: 1H/1V, 1H/2V, 1H/3V and 1H/4V

• 64 Horizontal starting positions (4 dots for each step)

• 64 Vertical starting positions (4 scan lines for each step)

• Vertical jumping cancelling circuit

• Spacing between character rows: 0, 4, 8 and 12 scan

lines

• Foreground colours: 8 on a character-by-character basis

C-bus interface

OSD

): 20 MHz (see Section 20

The PCE84C882 is the enhanced version of the PCE84C886 having all the features of this device but in addition provides:

• Two dedicated power pins for the PLL oscillator circuit

• A choice of two mask-programmable prescaler values

for the PLL oscillator

• A higher frequency OSD clock - up to 20 MHz

• An improved edge-sensitive counter (T3).

Differences between the PCE84C882 and the PCE84C886 are shown in Table 1 and also highlighted throughout the document.

The PCE84C882 is a member of the 84CXXX CMOS microcontroller family. It is suitable for use with auto-sync monitors handling mode detection, digital and DPMS control and has an enhanced OSD facility for menu driving applications. The device uses the PCE84CXX processor core and has 8 kbytes of ROM and 192 bytes of RAM. I/O requirements are catered for with 12 general purpose bidirectional I/O lines plus 14 derivative I/O lines. 8 PWM analog outputs are available for analog control purposes and one 4-bit ADC. The device has an 8-bit counter, for use in pulse counting applications; an 8-bit timer/counter with programmable clock and an on-chip programmable PLL oscillator that generates the OSD clock. A master-slave I are also available. The block diagram of the PCE84C882 is shown in Fig.1.

C-bus interface and 2 directly testable lines

1996 Jan 08 3

Philips Semiconductors Preliminary speciﬁcation

Microcontroller for monitor OSD

PCE84C882

and auto-sync applications

Table 1 Differences between the PCE84C882 and the PCE84C886

FEATURE PCE84C882 PCE84C886

Maximum dot frequency (f Maximum Hsync frequency 90 kHz 64 kHz PLL prescaler value 2 or 4 2 Digital to Analogue Converter 1channel 3 channels Pulse Width Modulated outputs 8 channels 9 channels Derivative I/O pins 14 16 Counter T3 input edge sensitivity 0.4 µs1µs

Pin assignment

Pin 21 V Pin 22 C DP07/PWM7 Pin 23 V Pin 24 DP05 DP05/PWM5 Pin 30 V Pin 37 DP07/PWM7 DP11/ADC1 Pin 38 DP06/PWM6 DP10/ADC0 Pin 41 TEST/EMU C

) 20 MHz 14 MHz

OSD

SSP

DDP

DP06/PWM6

TEST/EMU

3 ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

PCE84C882 SDIP42 plastic shrink dual in-line package; 42 leads (600 mil) SOT270-1

PACKAGE

1996 Jan 08 4

Philips Semiconductors Preliminary speciﬁcation

Microcontroller for monitor OSD and auto-sync applications

4 BLOCK DIAGRAM

handbook, full pagewidth

INTN / T0 T3

CPU

XTAL1 (IN)

XTAL2 (OUT)

8-BIT

TIMER /

EVENT

COUNTER

8-BIT

COUNTER

ROM

8 kbytes

RAM

192 bytes

SSP

OSCILLATOR

DDP

PLL

ON SCREEN DISPLAY

PCE84C882

VOW0 VOW2

VSYNCN

VOW1

(3)(3)

8-bit internal bus

HSYNCN

RESET

PARALLEL

I / O

TEST / EMU

(1) Alternative function of DP0. (2) Alternative function of DP1. (3) Alternative function of DP2.

PORTS

PCF84CXX core  excluding ROM / RAM

8-BIT

I / O

PORTS

28 4

DP0 DP1 DP2

Fig.1 Block diagram.

3 x 6-BIT PWM 4 x 7-BIT PWM

(1) (2) (2) (3)

PWM0 

to

PWM7

14-BIT

PWM

PWM8 ADC2 SDA SCL

4-BIT ADC

I C-BUS

INTERFACE

MGC708

(3)

1996 Jan 08 5

Philips Semiconductors Preliminary speciﬁcation

Microcontroller for monitor OSD and auto-sync applications

5 PINNING INFORMATION

5.1 Pinning

handbook, halfpage

VOW1/DP22 VOW0/DP23

VSYNCN HSYNCN

DP13/PWM8

VOW2

P10 P11

P12

T3 P14 P00 P01 P02 P03 P04 P05 P06 P07

SSP

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21

PCE84C882

MGC709

TEST/EMU

DP20/SDA

DP21/SCL

DP06/PWM6

DP07/PWM7

DP12/ADC2

INTN/T0

RESET

XTAL2 (OUT)

XTAL1 (IN)

DP00/PWM0

DP01/PWM1

DP02/PWM2

DP03/PWM3

DP04/PWM4

DP05

DDP

PCE84C882

1996 Jan 08 6

Fig.2 Pin configuration.

Philips Semiconductors Preliminary speciﬁcation

Microcontroller for monitor OSD

PCE84C882

and auto-sync applications

5.2 Pin description Table 2 SDIP42 package

SYMBOL PIN DESCRIPTION

FB 1 Video Fast Blanking output. VOW2 2 Video character output VOW2. VOW1/DP22 3 Video character output VOW1 or Derivative Port line DP22. VOW0/DP23 4 Video character output VOW0 or Derivative Port line DP23. VSYNCN 5 Vertical synchronization signal input. HSYNCN 6 Horizontal synchronization signal input. P10 7 Port line 10 or emulation input P11 8 Port line 11 or emulation input DP13/PWM8 9 Derivative I/O port or PWM8 output. P12 10 Port line 12 or emulation input DXALE. T3 11 Secondary 8-bit counter input (Schmitt trigger). P14 12 Port line 14 or emulation output DXINT. P00 to P07 13 to 20 General I/O port lines. V

SSP

C 22 External low-pass ﬁlter for on-chip PLL OSD oscillator. V

DDP

DP00/PWM0 to DP07/PWM7 29, 28, 27, 26,

XTAL1 (IN) 31 Oscillator input pin for system clock. XTAL2 (OUT) 32 Oscillator output pin for system clock. RESET 33 Reset input; active LOW input initializes device. T1 34 Direct testable pin or event counter input. INTN/T0 35 External interrupt or direct testable pin. DP12/ADC2 36 Derivative I/O port or ADC Channel 2 input. DP21/SCL 39 Derivative port line or I DP20/SDA 40 Derivative port line or I TEST/EMU 41 Control input for testing and emulation mode, normally LOW. V

21 Ground pin of PLL circuit.

23 Power supply pin of PLL circuit.

Derivative I/O ports or PWM outputs. Note that DP05 has no

25, 24, 38, 37

30 Ground pin.

42 Power supply.

derivative function.

C-bus clock input.

C-bus data input.

DXWR.

DXRD.

1996 Jan 08 7

Philips Semiconductors Preliminary speciﬁcation

Microcontroller for monitor OSD and auto-sync applications

6 RESET

The RESET pin may be used as an active LOW input to initialize the microcontroller to a defined state.

An active reset can be generated by driving theRESET pin from an external logic device. Such an active reset pulse should not fall off before VDD has reached its f

-dependent minimum operating voltage.

xtal

A Power-on-reset can be generated using an external RC circuit. To avoid overload of the internal diode, an external diode should be added in parallel if C RC circuit is shown in Fig.3.

6.1 Reset trip level

The RESET trip voltage level for the PCE84C882 is in the range 0.7 to 1.9 V.

If any input (for example Hsync) goes HIGH before V applied, latch-up may occur and in this situation the PCE84C882 cannot be reset. The cause and effect of latch-up is shown in Fig.4.

6.2 Reset status

RESET

≥ 2.2 µF. The

handbook, halfpage

RESET

( 100 kΩ)

RESET

PCA84C8XX

Fig.3 External components for RESET pin.

handbook, halfpage

PCE84C882

internal reset

MLC259

internal V

• Derivative Registers reset status; see Table 38 for details

• Program Counter 00H

• Memory Bank 0

• Register Bank 0

• Stack Pointer 00H

• All interrupts disabled

• Timer/event counter 1 stopped and cleared

• Timer pre-scaler modulo-32 (PS = 0)

• Timer flag cleared

• Serial I/O interface disabled (ESO = 0) and in slave

receiver mode

• Idle and Stop mode cleared.

Hsync

RESET

HSYNCN

RESET

PCE84C882

internal reset

MGC710

Fig.4 The influence of an active HIGH signal being

applied before Power-on-reset.

1996 Jan 08 8

Philips Semiconductors Preliminary speciﬁcation

Microcontroller for monitor OSD and auto-sync applications

7 ANALOG (DC) CONTROL

The PCE84C882 has eight Pulse Width Modulated (PWM) outputs for analog control purposes e.g. brightness, contrast, H-shift, V-shift, H-width, V-size, E-W, R (or G or B) gain control etc. Each PWM output generates a pulse pattern with a programmable duty cycle.

The eight PWM outputs are specified below:

• 3 PWM outputs with 6-bit resolution (PWM4, 6 and 7)

• 4 PWM outputs with 7-bit resolution (PWM0 to PWM3)

• 1 PWM output with 14-bit resolution (PWM8).

The 6 and 7-bit PWM outputs are described in Section 7.1; the 14-bit PWM output is described in Section 7.2 and a typical PWM output application is described in Section 7.3.

7.1 6 and 7-bit PWM outputs

PWM outputs PWM0 to PWM4, PWM6 and PWM7, share the same pins as Derivative Port lines DP00 to DP04, DP06 and DP07, respectively. Selection of the pin function as either a PWM output or a Derivative Port line is achieved using the appropriate PWMnE bit in Register 21 (see Table 38).

PCE84C882

The duty cycle of each PWM output is dependent upon the programmable contents of its associated data latch (Registers 10 to 17 respectively, Register 15 is not used as there is no PWM5 output). As the clock frequency of each PWM circuit is generated can be calculated as shown below.

Pulse width

Where (PWMn) is the decimal value held in the data latch. The maximum repetition frequency (f

7-bit PWM outputs is shown below.

For the 6-bit PWM outputs:

For the 7-bit PWM outputs:

The block diagram for the 6 and 7-bit PWM outputs is shown in Fig.5.

⁄3× f

xtal

3 PWMn()×

---------------------------------f

xtal

, the pulse width of the pulse

) of the 6 and

PWM

xtal

PWM

--------- 192

xtal

--------- 384

The polarity of the PWM outputs is programmable and is selected by the P7LVL or the P6LVL bit in Register 23 (see Section 12.2). The state of the P7LVL bit determines the polarity of the 7-bit PWMs; the state of the P6LVL bit determines the polarity of the 6-bit PWMs.

handbook, full pagewidth

xtal

6 or 7-BIT PWM DATA LATCH

6 or 7-BIT DAC PWM

CONTROLLER

internal data bus

P6LVL/P7LVL

DP0x data

I/O

PWMnE

DP0x/PWMx

MLC069

1996 Jan 08 9

Fig.5 Block diagram for 6 and 7-bit PWMs.

Philips Semiconductors Preliminary speciﬁcation

Microcontroller for monitor OSD and auto-sync applications

handbook, full pagewidth

xtal

64

or

128

63

or

127

1 2 3 m m + 1 m + 2

decimal value PWM data latch

PCE84C882

64

or

128

MLC261

Fig.6 Typical non-inverted output pulse patterns for 6 or 7-bit PWM outputs.

1996 Jan 08 10

Philips Semiconductors Preliminary speciﬁcation

Microcontroller for monitor OSD and auto-sync applications

7.2 14-bit PWM output

PWM8 shares the same pin as Derivative Port line DP13. Selection of the pin function as either a PWM output or as a Derivative Port line is achieved using the PWM8E bit in Register 22 (see Section 12.1).

The block diagram for the 14-bit PWM output is shown in Fig.7 and comprises:

• Two 7-bit latches: PWM8L (Register 18) and PWM8H (Register 19)

• 14-bit data latch (PWMREG)

• 14-bit counter

• Coarse pulse controller

• Fine pulse controller

• Mixer.

Data is loaded into the 14-bit data latch (PWMREG) from the two 7-bit data latches (PWM8H and PWM8L) when either of these data latches is written to. The upper seven bits of PWMREG are used by the coarse pulse controller and determine the coarse pulse width; the lower seven bits are used by the fine pulse controller and determine in which subperiods fine pulses will be added. The outputs OUT1 and OUT2 of the coarse and fine pulse controllers are ‘ORED’ in the mixer to give the PWM8 output. The polarity of the PWM8 output is programmable and is selected by the P8LVL bit in Register 23, this is described in Section 12.2.

PCE84C882

7.2.1 C An active HIGH pulse is generated in every subperiod; the

pulse width being determined by the contents of PWM8H. The coarse output (OUT1) is LOW at the start of each subperiod and will remain LOW until the time

⁄ PWM8H 1+()×[]

then go HIGH and remain HIGH until the start of the next subperiod. The coarse pulse width may be calculated as shown below.

Pulse duration 127 PWM8H–()

7.2.2 F Fine adjustment is achieved by generating an additional

pulse in specific subperiods. The pulse is added at the start of the selected subperiod and has a pulse width of 3/f

xtal

subperiods a fine pulse will be added. It is the logic 0 state of the value held in PWM8L that actually selects the subperiods. When more than one bit is a logic 0 then the subperiods selected will be a combination of those subperiods specified in Table 3. For example, if PWM8L = 111 1010 then this is a combination of:

• PWM8L = 111 1110: subperiod 64 and

• PWM8L = 111 1011: subperiods 16, 48, 80 and 112.

Pulses will be added in subperiods 16, 48, 64, 80 and 112. This example is illustrated in Fig.10.

OARSE ADJUSTMENT

xtal

INE ADJUSTMENT

has elapsed. The output will

×=

-------f

xtal

. The contents of PWM8L determine in which

As the 14-bit counter is clocked by1⁄3× f

, the repetition

xtal

times of the coarse and fine pulse controllers may be calculated as shown below.

384

sub

49152

---------------f

xtal

--------- f

xtal

Coarse controller repetition time:

Fine controller repetition time:

Figure 8 shows typical PWM8 outputs, with coarse adjustment only, for different values held in PWM8H. Figure 9 shows typical PWM8 outputs, with coarse and fine adjustment, after the coarse and fine pulse controller outputs have been ‘ORED’ by the mixer.

1996 Jan 08 11

When PWM8L holds 111 1111 fine adjustment is inhibited and the PWM8 output is determined only by the contents of PWM8H.

Table 3 Additional pulse distribution

PWM8L ADDITIONAL PULSE IN SUBPERIOD

111 1110 64 111 1101 32 and 96 111 1011 16, 48, 80 and 112 111 0111 8, 24, 40, 56, 72, 88, 104 and 120 110 1111 4, 12, 20, 28, 36, 44, 52...116 and 124 101 1111 2, 6, 10, 14, 18, 22, 26, 30...122 and 126 011 1111 1, 3, 5, 7, 9, 11, 13, 15, 17...125 and 127

Philips Semiconductors Preliminary speciﬁcation

Microcontroller for monitor OSD and auto-sync applications

handbook, full pagewidth

‘MOVE instruction’

PWM8H

DATA LOAD

TIMING PULSE

LOAD

Internal data bus

7 7

PWMREG

PWM8L

PCE84C882

‘MOV instruction’

polarity control bit

P8LVL

7 7

COARSE 7-BIT

PWM

MIXER

Q14 to 8 Q7 to 1

14-BIT COUNTER

FINE PULSE

GENERATOR

OUT2OUT1

MLC071

PWM8 output

f = f

tdac xtal

1996 Jan 08 12

Fig.7 14-bit PWM Block diagram.

Philips Semiconductors Preliminary speciﬁcation

Microcontroller for monitor OSD and auto-sync applications

handbook, full pagewidth

xtal

127 0 1 2 m m + 1 m + 2

127

decimal value PWM8H data latch

PCE84C882

127 0 1

MLC263

xtal

handbook, full pagewidth

127 0 1 2 m m + 1 m + 2

127

Fig.8 Non-inverted PWM8 output patterns - Coarse adjustment only.

127 0 1

MLC262

decimal value PWM8H data latch

1996 Jan 08 13

Fig.9 Non-inverted PWM8 output patterns - Coarse and Fine adjustment.

Philips Semiconductors Preliminary speciﬁcation

Microcontroller for monitor OSD and auto-sync applications

handbook, full pagewidth

111 1110

111 1011

111 1010

PWM8L

sub0

sub16

sub32

sub48

sub64

PCE84C882

sub80

sub96

sub112

sub127

MLC755

Fig.10 Fine adjustment output (OUT2).

7.3 A typical PWM output application

A typical PWM application is shown in Fig.11. The buffer is used to reduce jitter on the OSD. R1 and C1 form the integration network the time constant of which should be at least 5 times greater than the repetition period of the PWM output pattern. In order to smooth a changing PWM output a high value of C1 should be chosen. The value of C1 will normally be in the range 1 to 10 µF. The potential divider chain formed by R2 and R3 is used only when the output voltage is to be offset. The output voltages for this application are calculated using Equations (1) and (2).

R3 supply voltage×

min

----------------------------------------------------

max

R1 R3×

--------------------- R1 R3+

-------------------------------------------------------------------

R1 R2×

---------------------R1 R2+

supply voltage×

R1 R3×

---------------------R1 R3+

(1)

(2)

The loop from the PWM pin through R1 and C1 to VSS will radiate high frequency energy pulses. In order to limit the effect of this unwanted radiation source, the loop should be kept short and a high value of R1 selected. The value of R1 will normally be in the range 3.3 to 100 kΩ. It is good practice to avoid sharing VSS (pin 30) with the return leads of other sensitive signals.

handbook, halfpage

PCE84C882

Fig.11 Typical PWM output circuit.

PWMn

MGC711

C1 R3

supply voltage

analog output

1996 Jan 08 14

Philips Semiconductors Preliminary speciﬁcation

Microcontroller for monitor OSD and auto-sync applications

8 ANALOG-TO-DIGITAL CONVERTER (ADC)

The single channel ADC comprises a 4-bit Digital-to-Analog Converter (DAC); a comparator; an analog channel selector and control circuitry. As the digital input to the 4-bit DAC is loaded by software (a subroutine in the program), it is known as a software ADC. The block diagram is shown in Fig.12.

The ADC input ADC2, shares the same pin as Derivative Port line DP12. Selection of the pin function as either an ADC input or as a Derivative Port line is achieved using bit ADCE2 in Register 22. When ADCE2 = 1, the ADC function is enabled (see Section 12.1).

The ADC channel selector is controlled by the ADCS1 and ADCS0 bits in Register 20. As the PCE84C882 provides only one ADC channel, ADCS1 bit must be set to a logic 1 and ADCS0 bit must be set to a logic 0. All other settings are invalid.

The 4-bit DAC analog output voltage (V by the decimal value of the data held in bits DAC0 to DAC3 of Register 20. V and Table 4 lists the V

is calculated as shown in Equation (3)

ref

values assuming VDD=5V.

ref

----------

ref

DAC value 1+()×=

When the analog input voltage is higher than V COMP bit in Register 20 will be HIGH.

Table 4 Selection of V

ref

DAC3 DAC2 DAC1 DAC0 V

00000.3125

00010.6250

00100.9375

00111.2500

01001.5625

01011.8750

01102.1875

01112.5000

10002.8125

10013.1250

10103.4375

10113.7500

11004.0625

11014.3750

11104.6875

11115.0000

) is determined

ref

, the

ref

(3)

(V)

PCE84C882

8.1 Conversion algorithm

There are many algorithms available to achieve the ADC conversion. The algorithm described below and shown in Fig.13 uses an iteration process.

1. Enable and then select the ADC2 channel for conversion. Channel selection is achieved using bits ADCS1 and ADCS0 in Register 20.

2. Set the digital input to the DAC to 1000. The digital input to the DAC is selected using bits DAC3 to DAC0 in Register 20.

3. Determine the result of the compare operation. This is achieved by reading the COMP bit in Register 20 using the instruction MOV A, D20. If COMP = 1; the analog input voltage is higher than the reference voltage (V lower than the reference voltage (V

4. If COMP = 1; then the analog input voltage is higher than the reference voltage (V digital input to the DAC needs to be increased. Set the input to the DAC to 1100.

5. If COMP = 0; then the analog input voltage is lower than the reference voltage (V digital input to the DAC needs to be decreased. Set the input to the DAC to 0100.

6. Determine the result of the compare operation by reading the COMP bit in Register 20.

7. For the DAC = 1100 case If COMP = 1; then the analog input voltage is still

greater than V DAC needs to be increased again. Set the input to the DAC to 1110.

If COMP = 0; then the analog input voltage is now less than V needs to be decreased. Set the input to the DAC to 1010

8. For the DAC = 0100 case If COMP = 1; then the analog input voltage is now

greater than V DAC needs to be increased. Set the input to the DAC to 0110.

If COMP = 0; then the analog input voltage is still lower than V needs to be decreased again. Set the input to the DAC to 0010.

). If COMP = 0; the analog input voltage is

ref

) and therefore the

ref

) and therefore the

ref

and therefore the digital input to the

ref

and therefore the digital input to the DAC

ref

and therefore the digital input to the

ref

and therefore the digital input to the DAC

ref

1996 Jan 08 15

Philips Semiconductors Preliminary speciﬁcation

Microcontroller for monitor OSD and auto-sync applications

9. The operations detailed in 6, 7 and 8 above are repeated and each time the digital input to the DAC is changed accordingly; as dictated by the state of the COMP bit. The complete process is shown in Fig.13. Each time the DAC input is changed the number of values which the analog input can take is reduced by half. In this manner the actual analog value is honed into. The value of the analog input (VA) is determined using Equation (4):

As the conversion time of each compare operation is greater than 6 µs but less than 9 µs; a NOP instruction is recommended to be used in between the instructions that change the value of V the COMP bit.

----------

DAC value 1+()×=

; select the ADC channel and read

ref

(4)

PCE84C882

andbook, full pagewidth

DP12/ADC2

Channel selection

ADC

CHANNEL

SELECTOR

ADCS1 ADCS0

ADCE2

ADC enable selection

Fig.12 Block diagram of 1 channel ADC.

ENABLE

SELECTOR

ref

−

DAC3

DERIVATIVE PORT

SELECTOR

EN2

COMPARATOR

4-BIT DAC

DAC2 DAC1 DAC0

DAC value selection

Internal bus

COMP bit

‘MOV A, D20’

instruction

to read COMP bit

MGC712

1996 Jan 08 16

Philips Semiconductors Preliminary speciﬁcation

Microcontroller for monitor OSD and auto-sync applications

Value = 0100

COMP = 1

Value = 0010

COMP = 1

Value = 0001

Value = 0011

Value = 0101

PCE84C882

0000

MLC073

COMP = 1

00010011

0010

COMP = 1

0101 0100

Value = 1000

COMP = 1

Value = 1100

COMP = 1

Value =0110

Value = 1010

Value = 1110

COMP = 1

Value = 0111

Value = 1001

Value = 1011

Value = 1101

COMP = 1

0111 0110

COMP = 1

1001 10001011

1010

COMP = 1

1101 1100

handbook, full pagewidth

Fig.13 Example of converting algorithm for software ADC.

1996 Jan 08 17

Value = 1111

COMP = 1

1111 1110

Philips Semiconductors Preliminary speciﬁcation

Microcontroller for monitor OSD and auto-sync applications

8.2 Typical ADC application

The ADC2 channel of the PCE84C882 can be used in keypad applications to detect and identify the operation of individual keys. The circuit for a 14-key application is shown in Fig.14.

When no key is depressed the input voltage at the DP12/ADC2 pin will be greater than15⁄16× VDD and if the DAC value selected is 1110 then the COMP bit will be HIGH. When any key is depressed the input voltage at the DP12/ADC2 pin will change, and as each key will generate its own unique input voltage, this can be measured by the ADC2 channel and the actual key depressed can then be identified.

PCE84C882

The input voltage generated by the operation of any key (ignoring the effect of the 100 kΩ resistor) can be calculated as follows:

ADCn

n 0.5–()

-----------------------16

Where n is the key number and can take any integer value in the range 1 to 14.

The input voltage at the ADC input will be influenced by the tolerance of the resistors and the length of the cable connecting the keypad to the monitor. In the worse case situation this may reduce the number of keys that can be uniquely detected and identified.

×=

handbook, halfpage

5 kΩ

2 kΩ

1 kΩ

100 kΩ

key 14

key 13

key 2

key 1

14 key matrix

DP12/ADC2

PCE84C882

MGC718

1996 Jan 08 18

Fig.14 A typical ADC application for keypad detection.

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