Philips pce84c486, pce84c487 Service manual

INTEGRATED CIRCUITS

DATA SH EET

PCE84C486; PCE84C487

Microcontrollers for digital
auto-sync and VST TV controller
applications

Objective specification
File under Integrated Circuits, IC14

1996 Feb 21

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync
and VST TV controller applications

CONTENTS

1 FEATURES

1.1 General

1.2 Special
2 GENERAL DESCRIPTION
3 ORDERING INFORMATION
4 BLOCK DIAGRAMS
5 PINNING INFORMATION

5.1 Pinning

5.2 Pin description
6 RESET

6.1 External reset using the RESET pin

6.2 Power-on-reset

6.3 Watchdog Timer reset

6.4 Reset trip level

6.5 Reset status
7 ANALOG (DC) CONTROL

7.1 6 and 7-bit PWM outputs

7.2 8-bit PWM outputs

7.3 14-bit PWM output (PWM8)

7.4 A typical PWM output application
8 ANALOG-TO-DIGITAL CONVERTER (ADC)

8.1 Conversion algorithm

8.2 A typical application for keypad detection
9I
10 8-BIT COUNTER (T3)
11 WATCHDOG TIMER (WDT)
12 OUTPUT PORTS

12.1 Mask options
13 DERIVATIVE REGISTERS

2

C-BUS INTERFACE

PCE84C486;

PCE84C487

14 LIMITING VALUES
15 DC CHARACTERISTICS
16 AC CHARACTERISTICS
17 PACKAGE OUTLINES
18 SOLDERING

18.1 Introduction

18.2 SDIP
19 DEFINITIONS
20 LIFE SUPPORT APPLICATIONS
21 PURCHASE OF PHILIPS I2C COMPONENTS

1996 Feb 21 2

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

1 FEATURES

1.1 General

• CMOS 8-bit CPU (enhanced 8048 CPU) with 4 kbytes
system ROM and 128 bytes system RAM

• One 8-bit timer/event counter (T1) and one 8-bit counter
(T3) triggered by external input

• Three single level vectored interrupt sources: external
(INTN), counter/timer and I

• 2 directly testable inputs T0 and T1

• On-chip oscillator clock frequency: 1 to 10 MHz

• On-chip Power-on-reset with low power detector

• The PCE84C486 has eleven quasi-bidirectional I/O

lines, the PCE84C487 has twelve. The configuration of
each I/O line individually selected by mask option

• Idle and Stop modes for reduced power consumption

• Operating temperature: −25 to +85 °C

• Operating voltage: 4.5 to 5.5 V

• Packages: SDIP32 for the PCE84C486; SDIP42 for the

PCE84C487.

1.2 Special

• Master-slave I

• Four 6-bit Pulse Width Modulated outputs

• Four 7-bit Pulse Width Modulated outputs

• Four 8-bit Pulse Width Modulated outputs (PCE84C487

only)

• One 14-bit Pulse Width Modulated output

• Two 4-bit Analog-to-Digital Converter (ADC) channels

• 14 derivative I/O ports

• Watchdog Timer.

2

C-bus interface

2

C-bus

PCE84C486; PCE84C487

2 GENERAL DESCRIPTION

The PCE84C486 and PCE84C487 are low-cost
microcontrollers and have been designed for use with
auto-sync monitors, handling mode detection, digital
control and Voltage Synthesized Tuning (VST). These
microcontrollers have no on-chip OSD function.

The term PCE84C48X is used throughout this data sheet
to refer to both devices. Differences between the
PCE84C486 and the PCE84C487 are highlighted
throughout the document.

The PCE84C48X is a member of the 84CXXX CMOS
microcontroller family. The device uses the PCE84CXX
processor core and has 4 kbytes of ROM and 128 bytes of
RAM. I/O requirements are catered for with 11 general
purpose bidirectional I/O lines (the PCE84C487 has 12)
plus 12 function combined I/O lines (the PCE84C487 has

16). Nine PWM analog outputs (the PCE84C487 has 13)
are available for analog control purposes and also a two
channel 4-bit ADC. The device has an 8-bit counter (T3),
for use in pulse counting applications and also an 8-bit
timer/counter (T1) with programmable clock. A Watchdog
timer, a master-slave I2C-bus interface and 2 directly
testable lines are also available on-chip.

The block diagram of the PCE84C486 is shown in Fig.1;
the block diagram of the PCE84C487 is shown in Fig.2.

3 ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

PCE84C486 SDIP32 plastic shrink dual in-line package; 32 leads (400 mil) SOT232-1
PCE84C487 SDIP42 plastic shrink dual in-line package; 42 leads (600 mil) SOT270-1

1996 Feb 21 3

PACKAGE

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

4 BLOCK DIAGRAMS

RESET

8-bit internal bus

WATCHDOG TIMER

2

I C-BUS

INTERFACE

2 x 4-BIT ADC

PCE84C486; PCE84C487

MGC912

SDA SCL

and

ADC1

ADC2

INTN / T0 T3

T1

RAM

128 bytes

ROM

4 kbytes

8-BIT

COUNTER

CPU

8-BIT

TIMER /

EVENT

COUNTER

4 x 6-BIT PWM

4 x 7-BIT PWM

1 x 14-BIT PWM

I / O PORTS

PCF84CXX

core

excluding

ROM / RAM

I / O

PORTS

PARALLEL

EMU

(1) (1) (2) (3)

to

PWM8

PWM0

38

DP1 DP2

DP0

4

P1

8

P0

handbook, full pagewidth

Fig.1 PCE84C486 block diagram.

DD

V

XTAL1 (IN)

XTAL2 (OUT)

1996 Feb 21 4

SS

V

(1) Alternative functions of DP0 and DP1.

(2) Alternative functions of DP2.

(3) Alternative function of P1.

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

RESET

8-bit internal bus

WATCHDOG TIMER

RAM

128 bytes

2

I C-BUS

INTERFACE

2 x 4-BIT ADC

PWM

4 x 8-BIT

PCE84C486; PCE84C487

MGC913

SDA SCL

and

ADC1

ADC2

to

PWM13

PWM10

INTN / T0 T3 RSTO

T1

DD

V

ROM

4 kbytes

8-BIT

COUNTER

CPU

8-BIT

EVENT

TIMER /

XTAL1 (IN)

COUNTER

XTAL2 (OUT)

4 x 6-BIT PWM

4 x 7-BIT PWM

1 x 14-BIT PWM

I / O PORTS

PCF84CXX

core

excluding

I / O

PORTS

PARALLEL

EMU

ROM / RAM

SS

V

(1) (2) (1) (2) (3)

to

PWM8

PWM0

38 5

DP0 DP1 DP2

4

P1

8

P0

handbook, full pagewidth

Fig.2 PCE84C487 block diagram.

1996 Feb 21 5

(1) Alternative functions of DP0 and DP1.

(2) Alternative function of DP2.

(3) Alternative function of P1.

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

5 PINNING INFORMATION

5.1 Pinning

handbook, halfpage

DP13/PWM8

DP20/SDA

P10/SCL

P11

P12

P14
P00
P01
P02
P03
P04
P05
P06
P07

V

T3

SS

1
2
3
4
5
6
7
8

PCE84C486

9
10
11
12
13
14
15
16

MGC904

32

DP07/PWM7

31

DP12/ADC2

30

INTN/T0

29

T1

28

RESET

27

XTAL2(OUT)

26

XTAL1(IN)

25

V

DD

24

DP00/PWM0

23

DP01/PWM1

22

DP02/PWM2

21

DP03/PWM3

20

DP04/PWM4

19

DP05/PWM5

18

DP06/PWM6

17

DP11/ADC1

handbook, halfpage

DP20/SDA

DP13/PWM8

DP24/PWM10

DP25/PWM11

PCE84C486; PCE84C487

P10/SCL

P11

P12

n.c.

T3

P14
P00

RSTO

P01
P02

P03

n.c.
P04
P05
P06
P07

V

SS

1
2
3
4
5
6
7
8

9
10
11

PCE84C487

12
13
14
15
16
17
18
19
20

MGC905

42

DP07/PWM7

41

DP12/ADC2

40

INTN/T0

39

T1

38

RESET

37

n.c.

36

XTAL2(OUT)

35

XTAL1(IN)

34

DP27/PWM13

33

V

DD

32

EMU

31

DP00/PWM0

30

DP01/PWM1

29

DP26/PWM12

28

DP02/PWM2

27

n.c.

26

DP03/PWM3

25

DP04/PWM4

24

DP05/PWM5

23

DP06/PWM6

2221

DP11/ADC1

Fig.3 Pin configuration - PCE84C486.

1996 Feb 21 6

Fig.4 Pin configuration - PCE84C487.

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and

PCE84C486; PCE84C487

VST TV controller applications

5.2 Pin description Table 1 SDIP32 package

SYMBOL PIN DESCRIPTION

DP20/SDA 1 Derivative port line 20 or I
P10/SCL 2 Port line 10 or I
P11 3 Port line 11 or emulation input
DP13/PWM8 4 Derivative I/O port 13 or PWM8 output.
P12 5 Port line 12 or emulation input DXALE.
T3 6 8-bit counter input (Schmitt trigger).
P14 7 Port line 14 or emulation output DXINT.
P00 to P07 8 to 15 General I/O port lines.
V

SS

DP11/ADC1 17 Derivative I/O port 11 or ADC Channel 1input.
DP00/PWM0 to DP07/PWM7 24 to 18, 32 Derivative I/O ports or 6 and 7-bit PWM outputs.
V

DD

XTAL1 (IN) 26 Oscillator input pin for system clock.
XTAL2 (OUT) 27 Oscillator output pin for system clock.
RESET 28 Reset input; active LOW input initializes device.
T1 29 Direct testable pin or event counter input.
INTN/T0 30 External interrupt or direct testable pin.
DP12/ADC2 31 Derivative I/O port 12 or ADC Channel 2 input.

16 Ground pin.

25 Power supply.

2

C-bus clock line or emulation input DXWR.

2

C-bus data line.

DXRD.

1996 Feb 21 7

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and

PCE84C486; PCE84C487

VST TV controller applications

Table 2 SDIP42 package

SYMBOL PIN DESCRIPTION

2

DP20/SDA 1 Derivative port line 20 or I

2

P10/SCL 2 Port line 10 or I
P11 3 Port line 11 or emulation input
DP13/PWM8 4 Derivative I/O port 13 or PWM8 output.
P12 5 Port line 12 or emulation input DXALE.
n.c. 6 Not connected.
T3 7 8-bit counter input (Schmitt trigger).
DP24/PWM10 to DP27/PWM13 8, 14, 29, 34 Derivative I/O ports or 8-bit PWM outputs.
P14 9 Port line 14 or emulation output DXINT.

P00 to P07
RSTO 11 Used for emulation purposes only. This active HIGH output is the

n.c. 16 Not connected.
V

SS

DP11/ADC1 22 Derivative I/O port 11 or ADC channel 1 input.
DP04/PWM4 to DP07/PWM7 25, 24, 23, 42 Derivative I/O ports or 6-bit PWM outputs.
n.c. 27 Not connected.
DP00/PWM0 to DP03/PWM3 31, 30, 28, 26 Derivative I/O ports or 7-bit PWM outputs.
EMU 32 Emulation mode control input, normally LOW.
V

DD

XTAL1 (IN) 35 Oscillator input pin for system clock.
XTAL2 (OUT) 36 Oscillator output pin for system clock.
n.c. 37 Not connected.
RESET 38 Reset input; active LOW input initializes device.
T1 39 Direct testable pin or event counter input.
INTN/T0 40 External interrupt or direct testable pin.
DP12/ADC2 41 Derivative I/O port 12 or ADC Channel 2 input.

10, 12, 13, 15,

17, 18, 19, 20

21 Ground pin.

33 Power supply.

General I/O port lines.

result of the OR operation carried out internally on the
input and the Watchdog Timer reset line.

C-bus clock line or emulation input DXWR.

C-bus data line.

DXRD.

RESET

1996 Feb 21 8

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

6 RESET

To initialize the microcontroller to a defined state a reset
operation is performed. A reset can be generated in three
ways:

• applying an external signal to the RESET pin

• via Power-on-reset circuitry

• by the Watchdog Timer.

6.1 External reset using the

An active LOW signal from an external logic device will
reset the device. The signal must be maintained long
enough to allow VDD to reach its f
operating voltage.

6.2 Power-on-reset

A Power-on-reset can be generated using an external RC
circuit. To avoid overload of the internal diode, an external
diode should be added in parallel if C
The RC circuit is shown in Fig.5.

RESET pin

-dependent minimum

xtal

≥ 2.2 µF.

RESET

PCE84C486; PCE84C487

6.4 Reset trip level

The RESET trip voltage level for both the PCE84C486 and
PCE84C487 is masked to 1.3 V.

6.5 Reset status

• Derivative Registers reset status; see Table 8 for details

• Program Counter 00H

• Memory Bank 0

• Register Bank 0

• Stack Pointer 00H

• All interrupts disabled

• Timer/event counter 1 stopped and cleared

• Timer pre-scaler modulo-32 (PS = 0)

• Timer flag cleared

• Serial I/O interface disabled (ESO = 0) and in slave

receiver mode

• Idle and Stop mode cleared.

6.3 Watchdog Timer reset

An overflow of the Watchdog Timer will cause the device
to be reset. The operation of the Watchdog Timer is
described in Chapter 12.

handbook, halfpage

V

DD

R

RESET

( 100 kΩ)

RESET

C

RESET

V

SS

internal reset

PCA84C8XX

MLC259

Fig.5 External components for RESET pin.

1996 Feb 21 9

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

7 ANALOG (DC) CONTROL

The PCE84C486 has nine Pulse Width Modulated outputs
(PWM0 to PWM8) and the PCE84C487 has thirteen Pulse
Width Modulated outputs (PWM0 to PWM8 and
PWM10 to PWM13). These outputs are used for analog
control purposes e.g. brightness, contrast, H-shift, V-shift,
H-width, V-size, pin-cushion, trapezium, R (or G or B) gain
control, sound volume etc. Each PWM output generates a
pulse pattern with a programmable duty cycle.

The PWM outputs are specified below:

• PWM0 to PWM3: 4 PWM outputs with 7-bit resolution

• PWM4 to PWM7: 4 PWM outputs with 6-bit resolution

• PWM8: 1 PWM output with 14-bit resolution

• PWM10 to PWM13: 4 PWM outputs with 8-bit

resolution.

The 6 and 7-bit PWM outputs are described in Section 7.1;
the 8-bit PWM outputs are described in Section 7.2 and
the 14-bit PWM output is described in Section 7.3. A
typical PWM output application is described in Section 7.4.

7.1 6 and 7-bit PWM outputs

The block diagram for the 6 and 7-bit PWM outputs is
shown in Fig.6.

Pulse Width Modulated outputs PWM0 to PWM7 share
the same pins as Derivative Port lines DP00 to DP07,
respectively. Selection of the pin function as either a PWM
output or a Derivative Port line is achieved using the
appropriate PWMnE bit in the PWME1 Register (see
Table 8).

The polarity of the 6 and 7-bit PWM outputs is
programmable and is selected by the P7LVL or the P6LVL
bit in the CON2 Register (see Table 8). The state of the
P7LVL bit determines the polarity of the 7-bit PWMs; the
state of the P6LVL bit determines the polarity of the 6-bit
PWMs.

The duty cycle of each PWM output is dependent upon the
programmable contents of its associated data latch
(PWM0 to PWM7 Registers respectively). As the clock
frequency of each PWM circuit is
of the pulse generated can be calculated as shown below.

1

⁄3× f

, the pulse width

xtal

PCE84C486; PCE84C487

The maximum repetition frequency (f
7-bit PWM outputs is shown below.

For the 6-bit PWM outputs:

For the 7-bit PWM outputs:

f

PWM

f

PWM

7.2 8-bit PWM outputs

The block diagram for the 8-bit PWM outputs is shown in
Fig.8.

The 8-bit PWM outputs PWM10 to PWM13 (only available
with the PCE84C487) share the same pins as Derivative
Port lines DP24 to DP27, respectively. Selection of the pin
function as either a PWM output or a Derivative Port line is
achieved using the appropriate PWMnE bit in the
PWME2 Register (see Table 8). In the PCE84C486 the
contents of the PWME2 register should be set so that
these PWM outputs are disabled (i.e 00H).

The polarity of the 8-bit PWM outputs is programmable
and is selected by the P8LVL bit in the CON2 Register.

The duty cycle of each 8-bit PWM output is dependent
upon the programmable contents of its associated data
latch (PWM10 to PWM13 Registers respectively). As the
clock frequency of each PWM circuit is f
width of the pulse generated can be calculated as shown
below.

Pulse width

PWMn()

=

-----------------------­f

xtal

Where (PWMn) is the decimal value held in the data latch.
The maximum repetition frequency (f

PWM outputs is shown below.

f

PWM

--------- ­256

f

xtal

=

An 8-bit PWM output is driven HIGH when the value held
in its data latch is 00H. This is different to the 6 and 7-bit
PWM outputs which are driven LOW when their data
latches contain 00H.

=

=

PWM

f

xtal

--------- ­192

f

xtal

--------- ­384

PWM

) of the 6 and

, the pulse

xtal

) of the 8-bit

Pulse width

3 PWMn()×

=

---------------------------------­f

xtal

Where (PWMn) is the decimal value held in the data latch.

1996 Feb 21 10

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

handbook, full pagewidth

f

xtal

3

6 or 7-BIT PWM DATA LATCH

6 or 7-BIT DAC PWM

CONTROLLER

internal data bus

P6LVL/P7LVL

Q

Q

PCE84C486; PCE84C487

DP0x data

I/O

PWMnE

DP0x/PWMx

MLC069

f

handbook, full pagewidth

xtal

3

64
or

128

00

01

m

63

or

127

Fig.6 Block diagram for 6 and 7-bit PWMs.

1 2 3 m m + 1 m + 2

decimal value PWM data latch

64

or

128

1

MLC261

Fig.7 Typical non-inverted output pulse patterns for 6 or 7-bit PWM outputs.

1996 Feb 21 11

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

handbook, full pagewidth

f

osc

8-BIT PWM DATA LATCH

8-BIT DAC PWM

CONTROLLER

Q

Q

P8LVL

PCE84C486; PCE84C487

DP2x data

I/O

PWMnE

DP2x/PWMx

MGC907

f

handbook, full pagewidth

osc

256 1 2 3 m m + 1 m + 2

00

01

m

256

Fig.8 Block diagram for 8-bit PWMs.

256 1

MGC908

decimal value PWM data latch

Fig.9 Typical non-inverted output pulse patterns for 8-bit PWM outputs.

1996 Feb 21 12

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

7.3 14-bit PWM output (PWM8)

The 14-bit PWM output can be used to generate the
Automatic Frequency Control (AFC) signal used in VST
applications.

PWM8 shares the same pin as Derivative Port line DP13.
Selection of the pin function as either a PWM output or as
a Derivative Port line is achieved using the PWM8E bit in
Register 22.

The Block diagram for the 14-bit PWM output is shown in
Fig.10 and comprises:

• Two 7-bit latches: PWM8L (Register 18) and PWM8H
(Register 19)

• 14-bit data latch (PWMREG)

• 14-bit counter

• Coarse pulse controller

• Fine pulse controller

• Mixer.

Data is loaded into the 14-bit data latch (PWMREG) from
the two 7-bit data latches (PWM8H and PWM8L) when
PWM8L is written to. The contents of PWMREG determine
the active time of the PWM8 output. The upper seven bits
of PWMREG are used by the coarse pulse controller and
determine the coarse pulse width; the lower seven bits are
used by the fine pulse controller and determine in which
subperiods fine pulses will be added. The outputs OUT1
and OUT2 of the coarse and fine pulse controllers are
‘ORED’ in the mixer to give the PWM8 output. The polarity
of the PWM8 output is programmable and is selected by
the P8LVL bit in Register 23.

1

⁄3× f

As the 14-bit counter is clocked by
times of the coarse and fine pulse controllers may be
calculated as shown below.

Coarse controller repetition time:

Fine controller repetition time:

t

sub

49152

t

=

----------------

r

Figure 11 shows typical PWM8 outputs, with coarse
adjustment only, for different values held in PWM8H. Note
that the PWM8 coarse controller output is the same as the
7-bit PWM outputs except the polarity is reversed.
Figure 12 shows typical PWM8 outputs, with coarse and
fine adjustment, after the coarse and fine pulse controller
outputs have been ‘ORED’ by the mixer.

, the repetition

xtal

384

=

--------- ­f

xtal

f

xtal

PCE84C486; PCE84C487

7.3.1 C
An active HIGH pulse is generated in every subperiod; the

pulse width being determined by the contents of PWM8H.
The coarse output (OUT1) is LOW at the start of each
subperiod and will remain LOW until the time

3f

⁄ PWM8H 1+()×[]

then go HIGH and remain HIGH until the start of the next
subperiod. The coarse pulse width may be calculated as
shown below.

Pulse duration 127 PWM8H–()

7.3.2 F
Fine adjustment is achieved by generating an additional

pulse in specific subperiods. The pulse is added at the
start of the selected subperiod and has a pulse width of
3/f

xtal

subperiods a fine pulse will be added. It is the logic 0 state
of the value held in PWM8L that actually selects the
subperiods. When more than one bit is a logic 0 then the
subperiods selected will be a combination of those
subperiods specified in Table 3. For example, if
PWM8L = 111 1010 then this is a combination of:

• PWM8L = 111 1110: subperiod 64 and

• PWM8L = 111 1011: subperiods 16, 48, 80 and 112.

Pulses will be added in subperiods 16, 48, 64, 80 and 112.
This example is illustrated in Fig.13.

When PWM8L holds 111 1111 fine adjustment is inhibited
and the PWM8 output is determined only by the contents
of PWM8H.

Table 3 Additional pulse distribution

PWM8L ADDITIONAL PULSE IN SUBPERIOD

111 1110 64
111 1101 32 and 96
111 1011 16, 48, 80 and 112
111 0111 8, 24, 40, 56, 72, 88, 104 and 120
110 1111 4, 12, 20, 28, 36, 44, 52...116 and 124
101 1111 2, 6, 10, 14, 18, 22, 26, 30...122 and 126
011 1111 1, 3, 5, 7, 9, 11, 13, 15, 17...125 and 127

OARSE ADJUSTMENT

xtal

INE ADJUSTMENT

has elapsed. The output will

3

×=

-------­f

xtal

. The contents of PWM8L determine in which

1996 Feb 21 13

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

handbook, full pagewidth

Internal data bus

PWM8H

7 7

PWM8L

PCE84C486; PCE84C487

‘MOV instruction’

DATA LOAD

TIMING PULSE

polarity
control bit

P14LVL

LOAD

COARSE 7-BIT

PWM

Q14 to 8 Q7 to 1

PWMREG

7 7

FINE PULSE

GENERATOR

OUT2OUT1

MIXER

Q

14-BIT COUNTER

Q

MGC909

PWM8 output

f = f

tdac xtal

3

Fig.10 14-bit PWM Block diagram.

1996 Feb 21 14

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

f

handbook, full pagewidth

xtal

3

127 0 1 2 m m + 1 m + 2

00

01

m

127

decimal value PWM8H data latch

PCE84C486; PCE84C487

127 0 1

MLC263

f

xtal

handbook, full pagewidth

3

127 0 1 2 m m + 1 m + 2

00

01

m

127

Fig.11 Non-inverted PWM8 output patterns - Coarse adjustment only.

127 0 1

MLC262

decimal value PWM8H data latch

Fig.12 Non-inverted PWM8 output patterns - Coarse and Fine adjustment.

1996 Feb 21 15

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

handbook, full pagewidth

111 1110

111 1011

111 1010

PWM8L

t

sub0

t

sub16

t

sub32

t

sub48

t

t

sub64

PCE84C486; PCE84C487

r

t

sub80

t

sub96

t

sub112

t

sub127

MLC755

Fig.13 Fine adjustment output (OUT2).

7.4 A typical PWM output application

A typical PWM application is shown in Fig.14. R1 and C1
form an integration network the time constant of which
should be at least 5 times greater than the repetition period
of the PWM output pattern. In order to smooth a changing
PWM output a high value of C1 should be chosen. The
value of C1 will normally be in the range 1 to 10 µF. The
potential divider chain formed by R2 and R3 is used only
when the output voltage is to be offset. The output voltages
for this application are calculated using
Equations (1) and (2).

V

V

----------------------------------------------------

max

R1 R3×

--------------------- ­R1 R3+

=

------------------------------------------------------------------ -

min

R3

R1 R2×

+

---------------------­R1 R2+

R2

+

supply voltage×

R1 R3×

---------------------­R1 R3+

The loop from the PWM pin through R1 and C1 to V

SS

(1)

(2)

will

R3 supply voltage×

=

radiate high frequency energy pulses. In order to limit the
effect of this unwanted radiation source, the loop should
be kept short and a high value of R1 selected. The value
of R1 will normally be in the range 3.3 to 100 kΩ. It is good
practice to avoid sharing VSS with the return leads of other
sensitive signals.

handbook, halfpage

PCE84C48X

Fig.14 Typical PWM output circuit.

PWMn

V

SS

MGD136

R1

R2

C1 R3

supply
voltage

analog
output

1996 Feb 21 16

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

8 ANALOG-TO-DIGITAL CONVERTER (ADC)

The two-channel ADC comprises a 4-bit Digital-to-Analog
Converter (DAC); a comparator; an analog channel
selector and control circuitry. As the digital input to the 4-bit
DAC is loaded by software (a subroutine in the program),
it is known as a software ADC. The block diagram is shown
in Fig.15.

The ADC inputs ADC1 and ADC2 share the same pins as
Derivative Port lines DP11 and DP12 respectively.
Selection of the pin function as either an ADC input or as
a Derivative Port line is achieved using bits ADCE1 and
ADCE2 in Register 22. When ADCEn = 1, the ADC
function is enabled.

The 4-bit DAC analog output voltage (V
by the decimal value of the data held in bits DAC0 to DAC3
of Register 20. V
and Table 4 lists the V

V

ref

DD

---------­16

V

is calculated as shown in Equation (3)

ref

values assuming VDD=5V.

ref

DAC value 1+()×=

When the analog input voltage is higher than V
COMP bit in Register 20 will be HIGH.

Table 4 Selection of V

ref

DAC3 DAC2 DAC1 DAC0 V

00000.3125

00010.6250

00100.9375

00111.2500

01001.5625

01011.8750

01102.1875

01112.5000

10002.8125

10013.1250

10103.4375

10113.7500

11004.0625

11014.3750

11104.6875

11115.0000

) is determined

ref

, the

ref

(V)

ref

(3)

PCE84C486; PCE84C487

The ADC channel selector is controlled by the ADCS1 and
ADCS0 bits in Register 20. The channels are selected as
shown in Table 5.

Table 5 Selection of ADC channel

ADCS1 ADCS0 CHANNEL SELECTED

0 0 not allowed
0 1 ADC1
1 0 ADC2
1 1 not allowed

8.1 Conversion algorithm

There are many algorithms available to achieve the ADC
conversion. The algorithm described below and shown in
Fig.16 uses an iteration process.

1. Enable and then select the ADC channel for
conversion. Channel selection is achieved using bits
ADCS1 and ADCS0 in Register 20.

2. Set the digital input to the DAC to 1000. The digital
input to the DAC is selected using bits DAC3 to DAC0
in Register 20.

3. Determine the result of the compare operation. This is
achieved by reading the COMP bit in Register 20
using the instruction MOV A, D20H. If COMP = 1; the
analog input voltage is higher than the reference
voltage (V
lower than the reference voltage (V

4. If COMP = 1; then the analog input voltage is higher
than the reference voltage (V
digital input to the DAC needs to be increased. Set the
input to the DAC to 1100.

5. If COMP = 0; then the analog input voltage is lower
than the reference voltage (V
digital input to the DAC needs to be decreased. Set the
input to the DAC to 0100.

6. Determine the result of the compare operation by
reading the COMP bit in Register 20.

). If COMP = 0; the analog input voltage is

ref

).

ref

) and therefore the

ref

) and therefore the

ref

1996 Feb 21 17

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

7. For the DAC = 1100 case
If COMP = 1; then the analog input voltage is still

greater than V
DAC needs to be increased again. Set the input to the
DAC to 1110.

If COMP = 0; then the analog input voltage is now less
than V

and therefore the digital input to the DAC

ref

needs to be decreased. Set the input to the DAC to
1010

8. For the DAC = 0100 case
If COMP = 1; then the analog input voltage is now

greater than V
DAC needs to be increased. Set the input to the DAC
to 0110.

If COMP = 0; then the analog input voltage is still lower
than V

and therefore the digital input to the DAC

ref

needs to be decreased again. Set the input to the DAC
to 0010.

and therefore the digital input to the

ref

and therefore the digital input to the

ref

PCE84C486; PCE84C487

9. The operations detailed in 6, 7 and 8 above are
repeated and each time the digital input to the DAC is
changed accordingly; as dictated by the state of the
COMP bit. The complete process is shown in Fig.16.
Each time the DAC input is changed the number of
values which the analog input can take is reduced by
half. In this manner the actual analog value is honed
into. The value of the analog input (VA) is determined
using Equation (4):

V

V

As the conversion time of each compare operation is
greater than 6 µs but less than 9 µs; a NOP instruction is
recommended to be used in between the instructions that
change the value of V
the COMP bit.

DD

16

DAC value 1+()×=

; select the ADC channel and read

ref

----------

A

(4)

handbook, full pagewidth

DP11/ADC1

DP12/ADC2

Channel selection

ADC

CHANNEL

SELECTOR

ADCS1 ADCS0

ADCE1 ADCE2

ADC enable selection

Fig.15 Block diagram of 2 channel ADC.

ENABLE

SELECTOR

DERIVATIVE PORT

EN1 EN2

+

V

ref

DAC3

COMPARATOR

−

DAC2 DAC1 DAC0

DAC value selection

SELECTOR

EN

4-BIT DAC

Internal bus

COMP bit

‘MOV A, D20’

instruction

to read COMP bit

MGD263

1996 Feb 21 18

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

Value = 0010

Value = 0100

COMP = 1

TF

PCE84C486; PCE84C487

Value = 0001

COMP = 1

TF

Value = 0011

Value = 0101

COMP = 1

TF

COMP = 1

TF

COMP = 1

TF

0000

00010011

0010

0101 0100

MLC073

Value = 1000

TF

COMP = 1

Value =0110

Value = 1010

Value = 1100

COMP = 1

TF

Value = 1110

COMP = 1

TF

Value = 0111

Value = 1001

COMP = 1

TF

Value = 1011

Value = 1101

COMP = 1

TF

COMP = 1

TF

COMP = 1

TF

COMP = 1

TF

COMP = 1

TF

0111 0110

handbook, full pagewidth

1001 10001011

1010

Fig.16 Example of converting algorithm for software ADC.

1101 1100

1996 Feb 21 19

Value = 1111

COMP = 1

TF

1111 1110

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

8.2 A typical application for keypad detection

The ADC channels of the PCE84C48X can be used in
keypad applications to detect and identify the operation of
individual keys. The circuit for a 14-key application is
shown in Fig.17.

When no key is depressed the input voltage at the ADC
input pin will be greater than15⁄16VDD and if the DAC value
selected is 1110 then the COMP bit will be HIGH. When
any key is depressed the input voltage at the ADC input pin
will change, and as each key will generate its own unique
input voltage, this can be measured by the ADC channel
and the actual key depressed can then be identified.

PCE84C486; PCE84C487

The input voltage generated by the operation of any key
(ignoring the effect of the 100 kΩ resistor) can be
calculated as follows:

V

ADCn

n 0.5–()

-----------------------­16

Where n is the key number and can take any integer value
in the range 1 to 14.

The input voltage at the ADC input will be influenced by the
tolerance of the resistors and the length of the cable
connecting the keypad to the monitor. In the worse case
situation this may reduce the number of keys that can be
uniquely detected and identified.

V

×=

DD

handbook, halfpage

5 kΩ

2 kΩ

2 kΩ

2 kΩ

1 kΩ

100 kΩ

key 14

key 13

key 2

key 1

14 key matrix

1 µF

V

DD

ADCx

PCE84C486
PCE84C487

V

SS

MGC910

Fig.17 A typical ADC application for keypad detection.

1996 Feb 21 20

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

9I2C-BUS INTERFACE

The PCE84C48X has an on-chip I2C-bus interface that
can be used in master or slave mode. Full details of the
I2C-bus are given in the document

to use it”

. This document may be ordered using the code

9398 393 40011.
The I2C-bus interface lines SDA and SCL share the same

pins as port lines DP20 and P10 respectively. Selection of
the pin function as either an I2C-bus line or a port line is
achieved using the SDAE and SCLE bits in Derivative
Register 22. Only port Option 2 is available for both of
these pins.

10 8-BIT COUNTER (T3)

The main application for this counter is in the frequency
measurement of the Hsync signal.

The block diagram of the 8-bit counter is shown in Fig.22.
A Schmitt trigger is used at the input for noise rejection and
also to shape the input signal into a square wave. The T3
input is sampled at a frequency of
clock which synchronizes the internal T3 clock and the
read operation of Derivative Register 24. The rising edge
of the input increments the ripple counter by 1.

“The I2C-bus and how

1

⁄3× f

by the sample

osc

PCE84C486; PCE84C487

If the rising and falling edges of the input pulse are less
than 30 ns then the minimum pulse width that the T3 input
will recognise is 3/f
10 MHz then the minimum pulse width is 400 ns. In some
display modes, the active pulse width of the Hsync signal
can be less than 400 ns; in this situation some external
application circuitry may be required.

handbook, halfpage

0.9 V

0.1 V

0.9 V

0.1 V

+ 100 ns. If the system clock is

osc

t

H

DD
DD

DD
DD

t

r

t

f

t

f

t

r

t

L

MGC719

The contents of T3 may be read using the instruction
MOV A, D24H. As soon as the data is read, the counter is
reset to zero. A counter overflow or Power-on-reset also
resets the counter contents to zero.

handbook, full pagewidth

T3

Power-on-reset

EMU

READ D24H

SYNCHRONISATION

CIRCUIT

sample clock

T3 COUNTER

CONTROL CIRCUIT

Fig.18 T3 input waveform.

CK

8-BIT COUNTER

RESET

Q0 to Q7

Data bus

MGC717

Fig.19 Block diagram of the 8-bit counter (T3).

1996 Feb 21 21

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

11 WATCHDOG TIMER (WDT)

The purpose of the Watchdog Timer is to reset the
microcontroller, within a reasonable period of time, if it
enters an erroneous processor state. Erroneous processor
states can be caused by noise or RFI.

The Watchdog Timer consists of a 23-bit counter which is
clocked at a frequency of f
contents of the counter are cleared. The counter contents
are then incremented by ‘1’ every oscillator clock cycle.
If the maximum count is exceeded, the counter overflows
and the microcontroller is reset. In order to prevent a
counter overflow and its resulting reset operation, the user
program must clear the contents of the Watchdog Timer
before its maximum count is exceeded. During normal
processing, the contents of the Watchdog Timer are
cleared by writing a logic 1 to Derivative Register 45H (this
is a dummy register).

. During a Power-on-reset the

osc

PCE84C486; PCE84C487

The maximum time period (t
and not cause a reset operation, is calculated as shown
below.

-------­f

osc

×=

t

p

22

1

2

In the Idle mode the oscillator is still running and the
Watchdog Timer remains active. In the Stop mode
however, the oscillator is stopped and the operation of the
Watchdog Timer is halted but its contents are retained.
Therefore, it may be advisable for the user to clear the
contents of the Watchdog Timer before the Stop mode is
entered, in order to avoid an unexpected reset operation
after the device is woken-up.

The operational voltage range of the Watchdog Timer is
2 to 5.5 V.

) which the counter may run

p

handbook, full pagewidth

f

osc

WR45H

Power-on-reset

CLK

23-BIT COUNTER

RESET

Q22

Fig.20 The Watchdog Timer.

on-chip RESET

MGC906

1996 Feb 21 22

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

12 OUTPUT PORTS

Each I/O port line may be individually configured using one
of three mask options. The three I/O mask options are
specified below:

Option 1 Standard input/output with switched pull-up

current source; this is shown in Fig.24.

Option 2 Input/output with open-drain output; this is

shown in Fig.25.
Option 3 Push-pull output; this is shown in Fig.26.
The state of each output port after a Power-on-reset can

also be selected using the mask options. All port mask
options are given in Section 13.1.

PCE84C486; PCE84C487

handbook, full pagewidth

WRITE PULSE

OUTL/ORL/ANL/MOV

DATA BUS

TR2

D

MQ

MASTER

ORL/ANL/MOV

D

SLAVE

SQ

SQ

TR1

IN/MOV

TR3

V

SS

Fig.21 Standard I/O with pull-up transistor source (Option 1).

MLA696

constant
current
source
100 µA typ.

V

DD

I/O PORT
LINE

1996 Feb 21 23

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

WRITE PULSE

handbook, full pagewidth

OUTL/ORL/ANL

DATA BUS

D

MQ

MASTER

ORL/ANL

D

SLAVE

SQ

SQ

IN

PCE84C486; PCE84C487

V

DD

I/O PORT

TR1

V

SS

MLA697

LINE

handbook, full pagewidth

WRITE PULSE

OUTL / ORL / ANL

DATA BUS

Fig.22 Open-drain I/O without pull-up transistor (Option 2).

TR2

D

SLAVE

SQ

SQ

TR1

V

SS

IN

D

MQ

MASTER

ORL / ANL

MLB998

constant
current
source
100 µA typ.

OUTPUT
LINE

V

DD

Fig.23 Push-pull output with pull-up transistor (Option 3).

1996 Feb 21 24

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

12.1 Mask options

Table 6 lists the port mask options available for the
PCE84C486; Table 7 lists the port mask options available
for the PCE84C487.

Table 6 Port options - PCE84C486

OPTION

PORT PIN

CONFIGURATION RESET STATE

P00 8 1, 2 or 3 HIGH or LOW
P01 9 1, 2 or 3 HIGH or LOW
P02 10 1, 2 or 3 HIGH or LOW
P03 11 1, 2 or 3 HIGH or LOW
P04 12 1, 2 or 3 HIGH or LOW
P05 13 1, 2 or 3 HIGH or LOW
P06 14 1, 2 or 3 HIGH or LOW
P07 15 1, 2 or 3 HIGH or LOW
P10 2 1, 2 or 3 HIGH or LOW
P11 3 1, 2 or 3 HIGH or LOW
P12 5 1, 2 or 3 HIGH or LOW
P14 7 1, 2 or 3 HIGH or LOW
DP00 24 1, 2 or 3 HIGH or LOW
DP01 23 1, 2 or 3 HIGH or LOW
DP02 22 1, 2 or 3 HIGH or LOW
DP03 21 1, 2 or 3 HIGH or LOW
DP04 20 1, 2 or 3 HIGH or LOW
DP05 19 1, 2 or 3 HIGH or LOW
DP06 18 1, 2 or 3 HIGH or LOW
DP07 32 1, 2 or 3 HIGH or LOW
DP11 17 1, 2 or 3 HIGH or LOW
DP12 31 1, 2 or 3 HIGH or LOW
DP13 4 1, 2 or 3 HIGH or LOW
DP20 1 2 HIGH

PCE84C486; PCE84C487

Table 7 Port options - PCE84C487

OPTION

PORT PIN

CONFIGURATION RESET STATE

P00 10 1, 2 or 3 HIGH or LOW
P01 12 1, 2 or 3 HIGH or LOW
P02 13 1, 2 or 3 HIGH or LOW
P03 15 1, 2 or 3 HIGH or LOW
P04 17 1, 2 or 3 HIGH or LOW
P05 18 1, 2 or 3 HIGH or LOW
P06 19 1, 2 or 3 HIGH or LOW
P07 20 1, 2 or 3 HIGH or LOW
P10 2 1, 2 or 3 HIGH or LOW
P11 3 1, 2 or 3 HIGH or LOW
P12 5 1, 2 or 3 HIGH or LOW
P14 9 1, 2 or 3 HIGH or LOW
DP00 31 1, 2 or 3 HIGH or LOW
DP01 30 1, 2 or 3 HIGH or LOW
DP02 28 1, 2 or 3 HIGH or LOW
DP03 26 1, 2 or 3 HIGH or LOW
DP04 25 1, 2 or 3 HIGH or LOW
DP05 24 1, 2 or 3 HIGH or LOW
DP06 23 1, 2 or 3 HIGH or LOW
DP07 42 1, 2 or 3 HIGH or LOW
DP11 22 1, 2 or 3 HIGH or LOW
DP12 41 1, 2 or 3 HIGH or LOW
DP13 4 1, 2 or 3 HIGH or LOW
DP20 1 2 HIGH
DP24 8 1, 2 or 3 HIGH or LOW
DP25 14 1, 2 or 3 HIGH or LOW
DP26 29 1, 2 or 3 HIGH or LOW
DP27 34 1, 2 or 3 HIGH or LOW

1996 Feb 21 25

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and

PCE84C486; PCE84C487

VST TV controller applications

13 DERIVATIVE REGISTERS

The PCE84C486 has 22 Derivative Registers and the PCE84C487 has 26 Derivative Registers. Both devices have one
dummy register associated with the Watchdog Timer; this resides at address 45H. The Derivative Port I/O registers are
located at addresses 00 to 05H. When DP0TR, DP1TR and DP2TR are read the data is read directly from the pin.
However, when DP0R, DP1R and DP2R are read the data is read from the port latch (see Figs 24 to 26 for the port
configuration).

As the PCE84C486 has no 8-bit PWM outputs the PWME2 Register (address 44H) is not used and its contents must be
set to 00H. Registers PWME2, PWM10 to PWM13 and the 4 MSBs of Registers DP2TR and DP2R are only available in
the PCE84C487.

Table 8 Register map (see note 1)

ADDR

(HEX)

00 DP0TR

01 DP1TR

02 DP2TR

03 DP0R

04 DP1R

05 DP2R

10 PWM0 −

11 PWM1 −

12 PWM2 −

13 PWM3 −

14 PWM4 −

15 PWM5 −

16 PWM6 −

17 PWM7 −

18 PWM8L −

19 PWM8H −

REG 7 6 5 4 3 2 1 0 R/W

DP07

(terminal)

(terminal)−(X)

(terminal)

(latch)

(latch)

(latch)

(X)

DP27
(X)

DP07
(1)

−

(X)
DP27

(1)

(X)

(X)

(X)

(X)

(X)

(X)

(X)

(X)

(X)

(X)

DP06
(X)

−

(X)
DP26

(X)
DP06

(1)

−

(X)
DP26

(1)
PWM06

(0)
PWM16

(0)
PWM26

(0)
PWM36

(0)

−

(X)

−

(X)

−

(X)

−

(X)
PWM86L

(0)
PWM86H

(0)

DP05
(X)

−

(X)
DP25

(X)
DP05

(1)

−

(X)
DP25

(1)
PWM05

(0)
PWM15

(0)
PWM25

(0)
PWM35

(0)
PWM45

(0)
PWM55

(0)
PWM65

(0)
PWM75

(0)
PWM85L

(0)
PWM85H

(0)

DP04
(X)

−

(X)
DP24

(X)
DP04

(1)

−

(X)
DP24

(1)
PWM04

(0)
PWM14

(0)
PWM24

(0)
PWM34

(0)
PWM44

(0)
PWM54

(0)
PWM64

(0)
PWM74

(0)
PWM84L

(0)
PWM84H

(0)

DP03
(X)

DP13
(X)

−

(X)
DP03

(1)
DP13

(1)

−

(X)
PWM03

(0)
PWM13

(0)
PWM23

(0)
PWM33

(0)
PWM43

(0)
PWM53

(0)
PWM63

(0)
PWM73

(0)
PWM83L

(0)
PWM83H

(0)

DP02
(X)

DP12
(X)

−

(X)
DP02

(1)
DP12

(1)

−

(X)
PWM02

(0)
PWM12

(0)
PWM22

(0)
PWM32

(0)
PWM42

(0)
PWM52

(0)
PWM62

(0)
PWM72

(0)
PWM82L

(0)
PWM82H

(0)

DP01
(X)

DP11
(X)

−

(X)
DP01

(1)
DP11

(1)

−

(X)
PWM01

(0)
PWM11

(0)
PWM21

(0)
PWM31

(0)
PWM41

(0)
PWM51

(0)
PWM61

(0)
PWM71

(0)
PWM81L

(0)
PWM81H

(0)

DP00
(X)

− R

DP20
(X)

DP00
(1)

−

(1)
DP20

(1)
PWM00

(0)
PWM10

(0)
PWM20

(0)
PWM30

(0)
PWM40

(0)
PWM50

(0)
PWM60

(0)
PWM70

(0)
PWM80L

(0)
PWM80H

(0)

R

R

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

1996 Feb 21 26

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

ADDR

(HEX)

20 ADCCN −

21 PWME1 PWM7E

22 CON1 PWM8E

23 CON2 −

24 T3CON T3B7

40 PWM10 PWM107

41 PWM11 PWM117

42 PWM12 PWM127

43 PWM13 PWM137

44 PWME2 −

REG 7 6 5 4 3 2 1 0 R/W

(X)

(0)

(0)

(X)

(0)

(0)

(0)

(0)

(0)

(X)

ADCS1
(0)

PWM6E
(0)

SCLE
(0)

−

(X)
T3B6

(0)
PWM106

(0)
PWM116

(0)
PWM126

(0)
PWM136

(0)

−

(X)

ADCS0
(0)

PWM5E
(0)

SDAE
(0)

−

(X)
T3B5

(0)
PWM105

(0)
PWM115

(0)
PWM125

(0)
PWM135

(0)

−

(X)

DAC3
(0)

PWM4E
(0)

ADCE2
(0)

−

(X)
T3B4

(0)
PWM104

(0)
PWM114

(0)
PWM124

(0)
PWM134

(0)

−

(X)

DAC2
(0)

PWM3E
(0)

ADCE1
(0)

P8LVL
(0)

T3B3
(0)

PWM103
(0)

PWM113
(0)

PWM123
(0)

PWM133
(0)

PWM13E
(0)

PCE84C486; PCE84C487

DAC1
(0)

PWM2E
(0)

(3)

0

P14LVL
(0)

T3B2
(0)

PWM102
(0)

PWM112
(0)

PWM122
(0)

PWM132
(0)

PWM12E
(0)

DAC0
(0)

PWM1E
(0)

−

(X)
P7LVL

(0)
T3B1

(0)
PWM101

(0)
PWM111(0)PWM110

PWM121
(0)

PWM131
(0)

PWM11E
(0)

(2)

COMP
(0)

PWM0E
(0)

−

(X)
P6LVL

(0)
T3B0

(0)
PWM100

(0)

(0)
PWM120

(0)
PWM130

(0)
PWM10E

(0)

RW

RW

RW

RW

R

RW

RW

RW

RW

RW

Notes

1. Values within parethesis show the bit state after a reset operation. ‘X’ denotes an undefined state.

2. This bit is Read only.

3. This bit must be set to logic 0.

14 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 34)

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD

V

I

I

OH

I

OL

P

tot

T

amb

T

stg

supply voltage −0.3 +8.0 V
input voltage on any pin with respect to ground (VSS) −0.3 VDD+ 0.3 V
maximum source current for all port lines −−10.0 mA
maximum sink current for all port lines − 30.0 mA
total power dissipation − 1W
operating ambient temperature −25 +85 °C
storage temperature −55 +125 °C

1996 Feb 21 27

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and

PCE84C486; PCE84C487

VST TV controller applications

15 DC CHARACTERISTICS

V

=5V±10%;VSS=0V;T

DD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V
I

I
V

DD

DD

LU

POR

operating supply voltage 4.5 5.0 5.5 V
operating supply current f

latch-up current for all pins 50 −− mA
Power-on-reset voltage level 0.7 1.3 1.9 V

Ports P0; P1; DP0; DP1 and DP2 inputs

V

IL

V

IH

I

LI

LOW level input voltage 0 − 0.3VDDV
HIGH level input voltage 0.7VDD− V
input leakage current VSS< VI< V

Port P0 outputs

V
I

OH1

I

OH2

OL

LOW level output voltage VDD=5V; IOL=10mA −−1.2 V
HIGH level pull-up output source current VDD=5V; VO= 0.7V

HIGH level push-pull output source current VDD=5V; VO=VDD− 0.4 V −3.0 −7.0 − mA

DP00/PWM0 to DP07/PWM7; DP24/PWM10 to DP27/PWM13 as derivative ports

I

OL

I

OH1

I

OH2

LOW level output sink current VDD=5V; VOL= 0.4 V 5.0 12.0 − mA
HIGH level pull-up output source current VDD=5V; VO= 0.7V

HIGH level push-pull output source current VDD=5V; VO=VDD− 0.4 V −3.0 −7.0 − mA

DP00/PWM0 to DP07/PWM7; DP24/PWM10 to DP27/PWM13 as PWM outputs

I

OL

I

OH1

I

OH2

LOW level output sink current VDD=5V; VOL= 0.4 V 0.7 1.5 − mA
HIGH level pull-up output source current VDD=5V; VO= 0.7V

HIGH level push-pull output source current VDD=5V; VO=VDD− 0.4 V −0.7 −1.5 − mA

P10 to P12 and P14 outputs

I

OL

I

OH1

I

OH2

LOW level output sink current VDD=5V; VOL= 0.4 V 5.0 12.0 − mA
HIGH level pull-up output source current VDD=5V; VO= 0.7V

HIGH level push-pull output source current VDD=5V; VO=VDD− 0.4 V −3.0 −7.0 − mA

DP20/SDA and DP21/SCL outputs

I

OL

I

OH1

I

OH2

LOW level output sink current VDD=5V; VOL= 0.4 V 3.0 −− mA
HIGH level pull-up output source current VDD=5V; VO= 0.7V

HIGH level push-pull output source current VDD=5V; VO=VDD− 0.4 V −3.0 −7.0 − mA

= −25 to +85 °C; all voltages with respect to VSS; unless otherwise specified.

amb

= 10 MHz; VDD=5V − 510mA

xtal

f

= 6 MHz; VDD=5V − 3.5 7 mA

xtal

Stop; f
Stop; f

V

DD

V

DD

V

DD

V

DD

V

DD

= 10 MHz − 36 mA

xtal

= 6 MHz − 1.5 4 mA

xtal

DD

=5V; VO=V

=5V; VO=V

=5V; VO=V

=5V; VO=V

=5V; VO=V

DD

SS

DD

SS

DD

SS

DD

SS

DD

SS

−−±10 µA

−40 −100 −µA

−−140 −400 µA

−40 −100 −µA

−−140 −400 µA

−40 −100 −µA

−−140 −400 µA

−40 −100 −µA

−−140 −400 µA

−40 −100 −µA

−−140 −400 µA

DD

V

1996 Feb 21 28

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and

PCE84C486; PCE84C487

VST TV controller applications

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DP13/PWM8 as PWM8 output

I

OL

I

OH1

I

OH2

DP11/ADC1 or DP12/ADC2 as derivative output ports

I

OL

I

OH1

I

OH2

TEST/EMU;

V

IL

V

IH

I

LI

LOW level output sink current VDD=5V; VOL= 0.4 V 1.4 3.0 − mA
HIGH level pull-up output source current VDD=5V; VO= 0.7V

V

=5V; VO=V

DD

SS

DD

−40 −100 −µA

−−140 −400 µA

HIGH level push-pull output source current VDD=5V; VO=VDD− 0.4 V −1.4 −3.0 − mA

LOW level output sink current VDD=5V; VOL= 0.4 V 5.0 12.0 − mA
HIGH level pull-up output source current VDD=5V; VO= 0.7V

=5V; VO=V

V

DD

SS

DD

−40 −100 −µA

−−140 −400 µA

HIGH level push-pull output source current VDD=5V; VO=VDD− 0.4 V −3.0 −7.0 − mA

RESET; INTN/T0; T1 and T3

LOW level input voltage 0 − 0.3VDDV
HIGH level input voltage 0.7VDD− V
input leakage current VSS< VI< V

DD

−1.0 − +1.0 µA

DD

V

16 AC CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

f

xtal

f

PXE

C

xtal1

Crystal oscillator frequency VDD= 5 V; T

Option 1: g
Option 2: g

= 0.4 mS 1 − 6 MHz

m

= 1.2 mS 4 − 10 MHz

m

PXE resonator frequency VDD= 5 V; T

Option 2: g

external capacitance at XTAL1 (IN)

= 1.2 mS 1 − 5 MHz

m

VDD= 5 V; T

= −25 to +85 °C

amb

= −25 to +85 °C

amb

= −25 to +85 °C − 30 100 pF

amb

pin (PXE resonator)

C

xtal2

external capacitance at XTAL2 (OUT)

VDD= 5 V; T

= −25 to +85 °C − 30 100 pF

amb

pin (PXE resonator)

t

T3

minimum pulse width period at T3
input

rising or falling edge of T3
pulse < 30 ns

0.4 −− µs

Analog-to-Digital (software) Converter

V

AI

DP11/ADC1 or DP12/ADC2

V

SS

− V

DD

V

comparator analog input voltage

V

AE

T

AFC

conversion error range −−±
conversion time (from any change in

−−7 µs

1

⁄

2

LSB

ADC input i.e. channel select, voltage
level or enable/disable)

1996 Feb 21 29

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

17 PACKAGE OUTLINES

SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)

D

seating plane

L

Z

32

e

b

PCE84C486; PCE84C487

SOT232-1

M

E

A

2

A

A

1

w M

b

1

17

c

(e )

M

1

H

pin 1 index

1

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

A

A

UNIT b

mm

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

max.

4.7 0.51 3.8

OUTLINE

VERSION

SOT232-1

12

min.

max.

IEC JEDEC EIAJ

1.3

0.8

b

1

0.53

0.40

REFERENCES

cEe M

0.32

0.23

(1) (1)

D

29.4

28.5

9.1

8.7

E

16

(1)

Z

L

3.2

2.8

EUROPEAN

PROJECTION

M

10.7

10.2

E

12.2

10.5

e

1

w

H

0.181.778 10.16

ISSUE DATE

92-11-17
95-02-04

max.

1.6

1996 Feb 21 30

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)

D

seating plane

L

Z

42

e

b

PCE84C486; PCE84C487

M

A

2

A

A

1

w M

b

1

22

c

(e )

M

SOT270-1

E

1

H

pin 1 index

1

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

A

A

UNIT b

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

mm

OUTLINE
VERSION

SOT270-1

max.

5.08 0.51 4.0

12

min.

max.

IEC JEDEC EIAJ

b

1.3

0.8

1

0.53

0.40

REFERENCES

0.32

0.23

cEe M

(1) (1)

D

38.9

38.4

14.0

13.7

E

21

(1)

Z

e

1

L

M

E

3.2

15.80

2.9

15.24

EUROPEAN

PROJECTION

17.15

15.90

w

H

0.181.778 15.24

ISSUE DATE

90-02-13
95-02-04

max.

1.73

1996 Feb 21 31

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

18 SOLDERING

18.1 Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

18.2 SDIP

18.2.1 SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

(order code 9398 652 90011).

PCE84C486; PCE84C487

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

18.2.2 R
Apply a low voltage soldering iron (less than 24 V) to the

lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

EPAIRING SOLDERED JOINTS

stg max

). If the

1996 Feb 21 32

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and

PCE84C486; PCE84C487

VST TV controller applications

19 DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

20 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

21 PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

1996 Feb 21 33

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

NOTES

PCE84C486; PCE84C487

1996 Feb 21 34

Philips Semiconductors Objective specification

Microcontrollers for digital auto-sync and
VST TV controller applications

NOTES

PCE84C486; PCE84C487

1996 Feb 21 35

Philips Semiconductors – a worldwide company

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BUENOS AIRES, Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

th

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Tel. [phone], Fax. [phone]

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]

Norway: Box 1, Manglerud 0612, OSLO,

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Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
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Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,

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SCDS47 © Philips Electronics N.V. 1996

All rights are reserved. Reproduction in whole or in part is prohibited without the
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The information presented in this document does not form part of any quotation
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other industrial or intellectual property rights.

Printed in The Netherlands

457021/1100/01/pp36 Date of release: 1996 Feb 21
Document order number: 9397 750 00676