Philips pce84c486, pce84c487 Service manual

INTEGRATED CIRCUITS

DATA SHEET

PCE84C486; PCE84C487

Microcontrollers for digital auto-sync and VST TV controller applications

Objective specification			1996 Feb 21
File under Integrated Circuits, IC14

Philips Semiconductors	Objective specification
Microcontrollers for digital auto-sync	PCE84C486;
and VST TV controller applications	PCE84C487

CONTENTS

1 FEATURES

1.1General

1.2Special

2GENERAL DESCRIPTION

3ORDERING INFORMATION

4BLOCK DIAGRAMS

5PINNING INFORMATION

5.1Pinning

5.2Pin description

6 RESET

6.1External reset using the RESET pin

6.2Power-on-reset

6.3Watchdog Timer reset

6.4Reset trip level

6.5Reset status

7	ANALOG (DC) CONTROL

7.16 and 7-bit PWM outputs

7.28-bit PWM outputs

7.314-bit PWM output (PWM8)

7.4A typical PWM output application

8	ANALOG-TO-DIGITAL CONVERTER (ADC)

8.1Conversion algorithm

8.2A typical application for keypad detection

9I2C-BUS INTERFACE

108-BIT COUNTER (T3)

11WATCHDOG TIMER (WDT)

12OUTPUT PORTS

12.1Mask options

13DERIVATIVE REGISTERS

14LIMITING VALUES

15DC CHARACTERISTICS

16AC CHARACTERISTICS

17PACKAGE OUTLINES

18SOLDERING

18.1Introduction

18.2SDIP

19DEFINITIONS

20LIFE SUPPORT APPLICATIONS

21PURCHASE OF PHILIPS I2C COMPONENTS

1996 Feb 21	2

Philips Semiconductors	Objective specification

Microcontrollers for digital auto-sync and

PCE84C486; PCE84C487

VST TV controller applications

1 FEATURES

1.1General

∙CMOS 8-bit CPU (enhanced 8048 CPU) with 4 kbytes system ROM and 128 bytes system RAM

∙One 8-bit timer/event counter (T1) and one 8-bit counter (T3) triggered by external input

∙Three single level vectored interrupt sources: external (INTN), counter/timer and I2C-bus

∙2 directly testable inputs T0 and T1

∙On-chip oscillator clock frequency: 1 to 10 MHz

∙On-chip Power-on-reset with low power detector

∙The PCE84C486 has eleven quasi-bidirectional I/O lines, the PCE84C487 has twelve. The configuration of each I/O line individually selected by mask option

∙Idle and Stop modes for reduced power consumption

∙Operating temperature: −25 to +85 °C

∙Operating voltage: 4.5 to 5.5 V

∙Packages: SDIP32 for the PCE84C486; SDIP42 for the PCE84C487.

1.2Special

∙Master-slave I2C-bus interface

∙Four 6-bit Pulse Width Modulated outputs

∙Four 7-bit Pulse Width Modulated outputs

∙Four 8-bit Pulse Width Modulated outputs (PCE84C487 only)

∙One 14-bit Pulse Width Modulated output

∙Two 4-bit Analog-to-Digital Converter (ADC) channels

∙14 derivative I/O ports

∙Watchdog Timer.

3 ORDERING INFORMATION

2 GENERAL DESCRIPTION

The PCE84C486 and PCE84C487 are low-cost microcontrollers and have been designed for use with auto-sync monitors, handling mode detection, digital control and Voltage Synthesized Tuning (VST). These microcontrollers have no on-chip OSD function.

The term PCE84C48X is used throughout this data sheet to refer to both devices. Differences between the PCE84C486 and the PCE84C487 are highlighted throughout the document.

The PCE84C48X is a member of the 84CXXX CMOS microcontroller family. The device uses the PCE84CXX processor core and has 4 kbytes of ROM and 128 bytes of RAM. I/O requirements are catered for with 11 general purpose bidirectional I/O lines (the PCE84C487 has 12) plus 12 function combined I/O lines (the PCE84C487 has 16). Nine PWM analog outputs (the PCE84C487 has 13) are available for analog control purposes and also a two channel 4-bit ADC. The device has an 8-bit counter (T3), for use in pulse counting applications and also an 8-bit timer/counter (T1) with programmable clock. A Watchdog timer, a master-slave I2C-bus interface and 2 directly testable lines are also available on-chip.

The block diagram of the PCE84C486 is shown in Fig.1; the block diagram of the PCE84C487 is shown in Fig.2.

	TYPE NUMBER		PACKAGE
		NAME	DESCRIPTION	VERSION
	PCE84C486	SDIP32	plastic shrink dual in-line package; 32 leads (400 mil)	SOT232-1
	PCE84C487	SDIP42	plastic shrink dual in-line package; 42 leads (600 mil)	SOT270-1

1996 Feb 21

3

21 Feb 1996

T1

INTN / T0

T3

VDD

XTAL1 (IN)

WATCHDOG TIMER

8-BIT

8-BIT

ROM

RAM

TIMER /

CPU

COUNTER

4 kbytes

128 bytes

EVENT

XTAL2 (OUT)

COUNTER

RESET

8-bit internal bus

4

PARALLEL

PCF84CXX

4 x 6-BIT PWM

I / O

I2C-BUS

core

I / O PORTS

2 x 4-BIT ADC

PORTS

4 x 7-BIT PWM

INTERFACE

excluding

1 x 14-BIT PWM

ROM / RAM

VSS

EMU

MGC912

8

4

8

3

(1)

(1)

(2)

(3)

P0

P1

DP0

DP1 DP2

PWM0

ADC1

SDA

SCL

to

and

PWM8

ADC2

(1) Alternative functions of DP0 and DP1.

full pagewidth

handbook,

(3) Alternative function of P1.

(2) Alternative functions of DP2.

Fig.1 PCE84C486 block diagram.

DIAGRAMS BLOCK 4

and sync-auto digital for Microcontrollers

PCE84C487 PCE84C486;

applications controller TV VST

Semiconductors Philips

specification Objective

21 Feb 1996

	T1	INTN / T0	T3		RSTO
VDD
XTAL1 (IN)					WATCHDOG TIMER
	8-BIT
			8-BIT	ROM	RAM
	TIMER /	CPU
			COUNTER	4 kbytes	128 bytes
	EVENT
XTAL2 (OUT)
	COUNTER				RESET
					8-bit internal bus

5

PARALLEL

I / O

PCF84CXX

4 x 6-BIT PWM

4 x 8-BIT

I2C-BUS

core

I / O PORTS

2 x 4-BIT ADC

EMU

PORTS

4 x 7-BIT PWM

PWM

INTERFACE

excluding

1 x 14-BIT PWM

ROM / RAM

VSS

8

4

8

3

5

MGC913

(1)

(2)

(1)

(2)

(3)

P0 P1

DP0

DP1

DP2

PWM0

PWM10

ADC1

SDA

SCL

to

to

and

PWM8

PWM13

ADC2

(1) Alternative functions of DP0 and DP1.

full pagewidth

handbook,

(2) Alternative function of DP2.

(3) Alternative function of P1.

Fig.2 PCE84C487 block diagram.

and sync-auto digital for Microcontrollers

PCE84C487 PCE84C486;

applications controller TV VST

Semiconductors Philips

specification Objective

Philips Semiconductors	Objective specification

Microcontrollers for digital auto-sync and

PCE84C486; PCE84C487

VST TV controller applications

5 PINNING INFORMATION

5.1Pinning

						handbook, halfpage
						DP20/SDA	1		42	DP07/PWM7
						P10/SCL
							2		41	DP12/ADC2
						P11
							3		40	INTN/T0
DP20/SDA	1		32	DP07/PWM7
						DP13/PWM8	4		39	T1
P10/SCL	2		31	DP12/ADC2
						P12	5		38		RESET
P11	3		30	INTN/T0
						n.c.	6		37	n.c.
DP13/PWM8	4		29	T1
						T3	7		36	XTAL2(OUT)
P12	5		28		RESET
						DP24/PWM10	8		35	XTAL1(IN)
T3	6		27	XTAL2(OUT)
						P14	9		34	DP27/PWM13
P14	7		26	XTAL1(IN)
						P00	10		33	VDD
P00	8	PCE84C486	25	VDD
						RSTO	11	PCE84C487	32	EMU
P01	9		24	DP00/PWM0
						P01	12		31	DP00/PWM0
P02	10		23	DP01/PWM1
						P02	13		30	DP01/PWM1
P03	11		22	DP02/PWM2
						DP25/PWM11	14		29	DP26/PWM12
P04	12		21	DP03/PWM3
						P03	15		28	DP02/PWM2
P05	13		20	DP04/PWM4
						n.c.	16		27	n.c.
P06	14		19	DP05/PWM5
						P04	17		26	DP03/PWM3
P07	15		18	DP06/PWM6
						P05	18		25	DP04/PWM4
VSS	16		17	DP11/ADC1
						P06	19		24	DP05/PWM5
		MGC904
						P07	20		23	DP06/PWM6
						VSS	21		22	DP11/ADC1
								MGC905

Fig.3 Pin configuration - PCE84C486.

Fig.4 Pin configuration - PCE84C487.

1996 Feb 21

6

Philips Semiconductors	Objective specification

Microcontrollers for digital auto-sync and

PCE84C486; PCE84C487

VST TV controller applications

5.2 Pin description Table 1 SDIP32 package

		SYMBOL	PIN	DESCRIPTION
	DP20/SDA		1	Derivative port line 20 or I2C-bus data line.
P10/SCL			2	Port line 10 or I2C-bus clock line or emulation input
							DXWR.
	P11		3	Port line 11 or emulation input
					DXRD.
	DP13/PWM8		4	Derivative I/O port 13 or PWM8 output.
	P12		5	Port line 12 or emulation input DXALE.
	T3		6	8-bit counter input (Schmitt trigger).
	P14		7	Port line 14 or emulation output DXINT.
	P00 to P07		8 to 15	General I/O port lines.
	VSS		16	Ground pin.
	DP11/ADC1		17	Derivative I/O port 11 or ADC Channel 1input.
	DP00/PWM0 to DP07/PWM7		24 to 18, 32	Derivative I/O ports or 6 and 7-bit PWM outputs.
	VDD		25	Power supply.
	XTAL1 (IN)		26	Oscillator input pin for system clock.
	XTAL2 (OUT)		27	Oscillator output pin for system clock.
			28	Reset input; active LOW input initializes device.
	RESET
	T1		29	Direct testable pin or event counter input.
	INTN/T0		30	External interrupt or direct testable pin.
	DP12/ADC2		31	Derivative I/O port 12 or ADC Channel 2 input.

1996 Feb 21

7

Philips Semiconductors	Objective specification

Microcontrollers for digital auto-sync and

PCE84C486; PCE84C487

VST TV controller applications

Table 2 SDIP42 package

		SYMBOL	PIN	DESCRIPTION
	DP20/SDA		1	Derivative port line 20 or I2C-bus data line.
P10/SCL			2	Port line 10 or I2C-bus clock line or emulation input
							DXWR.
P11			3	Port line 11 or emulation input
					DXRD.
	DP13/PWM8		4	Derivative I/O port 13 or PWM8 output.
	P12		5	Port line 12 or emulation input DXALE.
	n.c.		6	Not connected.
	T3		7	8-bit counter input (Schmitt trigger).
	DP24/PWM10 to DP27/PWM13		8, 14, 29, 34	Derivative I/O ports or 8-bit PWM outputs.
	P14		9	Port line 14 or emulation output DXINT.
	P00 to P07		10, 12, 13, 15,	General I/O port lines.
			17, 18, 19, 20
	RSTO		11	Used for emulation purposes only. This active HIGH output is the
				result of the OR operation carried out internally on the				RESET
				input and the Watchdog Timer reset line.
	n.c.		16	Not connected.
	VSS		21	Ground pin.
DP11/ADC1			22	Derivative I/O port 11 or ADC channel 1 input.
DP04/PWM4 to DP07/PWM7			25, 24, 23, 42	Derivative I/O ports or 6-bit PWM outputs.
n.c.			27	Not connected.
DP00/PWM0 to DP03/PWM3			31, 30, 28, 26	Derivative I/O ports or 7-bit PWM outputs.
EMU			32	Emulation mode control input, normally LOW.
VDD			33	Power supply.
XTAL1 (IN)			35	Oscillator input pin for system clock.
XTAL2 (OUT)			36	Oscillator output pin for system clock.
n.c.			37	Not connected.
			38	Reset input; active LOW input initializes device.
	RESET
	T1		39	Direct testable pin or event counter input.
	INTN/T0		40	External interrupt or direct testable pin.
	DP12/ADC2		41	Derivative I/O port 12 or ADC Channel 2 input.

1996 Feb 21

8

Philips Semiconductors	Objective specification

Microcontrollers for digital auto-sync and

PCE84C486; PCE84C487

VST TV controller applications

6 RESET

To initialize the microcontroller to a defined state a reset operation is performed. A reset can be generated in three ways:

·applying an external signal to the RESET pin

·via Power-on-reset circuitry

·by the Watchdog Timer.

6.1External reset using the RESET pin

An active LOW signal from an external logic device will reset the device. The signal must be maintained long enough to allow VDD to reach its fxtal-dependent minimum operating voltage.

6.2Power-on-reset

A Power-on-reset can be generated using an external RC circuit. To avoid overload of the internal diode, an external

diode should be added in parallel if CRESET ³ 2.2 mF. The RC circuit is shown in Fig.5.

6.3Watchdog Timer reset

An overflow of the Watchdog Timer will cause the device to be reset. The operation of the Watchdog Timer is described in Chapter 12.

6.4Reset trip level

The RESET trip voltage level for both the PCE84C486 and PCE84C487 is masked to 1.3 V.

6.5Reset status

·Derivative Registers reset status; see Table 8 for details

·Program Counter 00H

·Memory Bank 0

·Register Bank 0

·Stack Pointer 00H

·All interrupts disabled

·Timer/event counter 1 stopped and cleared

·Timer pre-scaler modulo-32 (PS = 0)

·Timer flag cleared

·Serial I/O interface disabled (ESO = 0) and in slave receiver mode

·Idle and Stop mode cleared.

handbook, halfpage

VDD

R RESET

internal reset

( 100 kΩ)

RESET

C RESET

VSS

PCA84C8XX

MLC259

Fig.5 External components for RESET pin.

1996 Feb 21

9

Philips Semiconductors	Objective specification

Microcontrollers for digital auto-sync and

PCE84C486; PCE84C487

VST TV controller applications

7 ANALOG (DC) CONTROL

The PCE84C486 has nine Pulse Width Modulated outputs (PWM0 to PWM8) and the PCE84C487 has thirteen Pulse Width Modulated outputs (PWM0 to PWM8 and

PWM10 to PWM13). These outputs are used for analog control purposes e.g. brightness, contrast, H-shift, V-shift, H-width, V-size, pin-cushion, trapezium, R (or G or B) gain control, sound volume etc. Each PWM output generates a pulse pattern with a programmable duty cycle.

The PWM outputs are specified below:

·PWM0 to PWM3: 4 PWM outputs with 7-bit resolution

·PWM4 to PWM7: 4 PWM outputs with 6-bit resolution

·PWM8: 1 PWM output with 14-bit resolution

·PWM10 to PWM13: 4 PWM outputs with 8-bit resolution.

The 6 and 7-bit PWM outputs are described in Section 7.1; the 8-bit PWM outputs are described in Section 7.2 and the 14-bit PWM output is described in Section 7.3. A typical PWM output application is described in Section 7.4.

7.16 and 7-bit PWM outputs

The block diagram for the 6 and 7-bit PWM outputs is shown in Fig.6.

Pulse Width Modulated outputs PWM0 to PWM7 share the same pins as Derivative Port lines DP00 to DP07, respectively. Selection of the pin function as either a PWM output or a Derivative Port line is achieved using the appropriate PWMnE bit in the PWME1 Register (see Table 8).

The polarity of the 6 and 7-bit PWM outputs is programmable and is selected by the P7LVL or the P6LVL bit in the CON2 Register (see Table 8). The state of the P7LVL bit determines the polarity of the 7-bit PWMs; the state of the P6LVL bit determines the polarity of the 6-bit PWMs.

The duty cycle of each PWM output is dependent upon the programmable contents of its associated data latch (PWM0 to PWM7 Registers respectively). As the clock

frequency of each PWM circuit is 1¤3 ´ fxtal, the pulse width of the pulse generated can be calculated as shown below.

3 ´ (PWMn) Pulse width = ---------------------------------

fxtal

Where (PWMn) is the decimal value held in the data latch.

The maximum repetition frequency (fPWM) of the 6 and 7-bit PWM outputs is shown below.

fxtal

For the 6-bit PWM outputs: fPWM = ---------

192

fxtal

For the 7-bit PWM outputs: fPWM = ---------

384

7.28-bit PWM outputs

The block diagram for the 8-bit PWM outputs is shown in Fig.8.

The 8-bit PWM outputs PWM10 to PWM13 (only available with the PCE84C487) share the same pins as Derivative Port lines DP24 to DP27, respectively. Selection of the pin function as either a PWM output or a Derivative Port line is achieved using the appropriate PWMnE bit in the PWME2 Register (see Table 8). In the PCE84C486 the contents of the PWME2 register should be set so that these PWM outputs are disabled (i.e 00H).

The polarity of the 8-bit PWM outputs is programmable and is selected by the P8LVL bit in the CON2 Register.

The duty cycle of each 8-bit PWM output is dependent upon the programmable contents of its associated data latch (PWM10 to PWM13 Registers respectively). As the

clock frequency of each PWM circuit is fxtal, the pulse width of the pulse generated can be calculated as shown

below.

(PWMn) Pulse width = ------------------------

fxtal

Where (PWMn) is the decimal value held in the data latch.

The maximum repetition frequency (fPWM) of the 8-bit PWM outputs is shown below.

fxtal

fPWM = ---------

256

An 8-bit PWM output is driven HIGH when the value held in its data latch is 00H. This is different to the 6 and 7-bit PWM outputs which are driven LOW when their data latches contain 00H.

1996 Feb 21

10

Philips Semiconductors	Objective specification

Microcontrollers for digital auto-sync and

PCE84C486; PCE84C487

VST TV controller applications

	internal data bus
			DP0x data
fxtal	6 or 7-BIT PWM DATA LATCH	P6LVL/P7LVL	I/O
3
			PWMnE
	Q
	6 or 7-BIT DAC PWM
	CONTROLLER		DP0x/PWMx
	Q
			MLC069

Fig.6 Block diagram for 6 and 7-bit PWMs.

	f
handbook,xtalfull pagewidth
	3
64							1		2		3										m		m + 1		m + 2		64												1
				or																																	or
128																											128
00

01

m

63 or 127

MLC261

decimal value PWM data latch

Fig.7	Typical non-inverted output pulse patterns for 6 or 7-bit PWM outputs.
1996 Feb 21	11