Philips PCD5091H, PCD5091HZ Datasheet
INTEGRATED CIRCUITS
DATA SH EET
PCD5091
DECT baseband controller
Objective specification
Supersedes data of 1996 Oct 30
File under Integrated Circuits, IC17
1997 Jul 21
Philips Semiconductors Objective specification
DECT baseband controller PCD5091
CONTENTS
1 FEATURES
1.1 DSP software features
2 GENERAL DESCRIPTION
3 ORDERING INFORMATION
4 BLOCK DIAGRAM
5 PINNING INFORMATION
5.1 Pinning
5.2 Pin description
6 FUNCTIONAL DESCRIPTION
7 PACKAGE OUTLINES
8 SOLDERING
8.1 Introduction
8.2 Reflow soldering
8.3 Wave soldering
8.4 Repairing soldered joints
9 DEFINITIONS
10 LIFE SUPPORT APPLICATIONS
11 PURCHASE OF PHILIPS I2C COMPONENTS
1997 Jul 21 2
Philips Semiconductors Objective specification
DECT baseband controller PCD5091
1 FEATURES
• 80C51 ports P0, P1, P2 and P3 available for interfacing
to display, keyboard, I2C-bus, interrupt sources and/or
external memory. Integrated 64 kbyte ROM, 3 kbytes of
data memory and 1 kbyte SDR-RAM. External program
memory is addressable up to 128 kbytes
• +2.7 to +5 V port (P0 to P3) interface
• TDMA frame (de)multiplexing. Transmission or
reception can be programmed for any slot
• Ciphering, scrambling, CRC checking/generation and
protected B-fields
• Speech and data buffering space for six handsets
• Local call and B-field loop-back
• Two interrupt lines for BML and DSP to interrupt 80C51
• On-chip, three-channel time-multiplexed 8-bit
Analog-to-Digital Converter (ADC) for RSSI
measurement, one for battery voltage measurement
and one channel available for other purposes
• On-chip 8-bit Digital-to-Analog Converter (DAC) for
electronic potentiometer function
• Phase error measurement and phase error correction by
hardware
• DACs and ADCs for dynamic earpiece and dynamic or
electret microphone
• On-chip reference voltage
• On-chip supply for electret microphone
• Very low ohmic buzzer output
• Serial interface to external ADPCM CODEC (PCD5032)
or 8 kHz u-law samples
• Speech switch for Digital Telephone Answering
Machine (DTAM) connected to SPI interface
• IOM-2 interface (Siemens registered trademark)
• Serial interface to synthesizer for frequency
programming
• Programmable polarity and timing of radio-control
signals
• GMSK pulse shaper
• Easy interfacing with radio circuits, operating at other
supply voltage (RF supply pin with level shifter for RF
signals)
• On-chip comparator for use as data-slicer
• Low power oscillator with integrated frequency
adjustment
• QFP100 and LQFP100 packages
• Power-on-reset
• Programmable power-down modes
• Low supply voltage (2.7 to 3.6 V)
• CMOS technology.
1.1 DSP software features
• ADPCM encoding and decoding complying with G.721
• Volume control
• Speech filters
• Programmable gain in speech paths
• Side tone and soft mute
• Two tone (DTMF) generators
• Automatic gain control
• Hands-free operation
For each DSP software version a separate manual is
available in which detailed information is provided on how
parameters must be set. For further information please
contact Philips Semiconductors.
2 GENERAL DESCRIPTION
The PCD5091 is designed for GAP-compliant handsets
with speaker-phone option. It has an embedded 80C51
microcontroller with twice the performance of the classic
architecture, 64 kbytes of PROM program memory and
3 kbytes of data memory on-chip. In addition there is
1 kbyte of on-chip data memory that is shared with on-chip
Burst Mode Logic (BML) and DSP, the System Data RAM
(SDR).
3 ORDERING INFORMATION
TYPE
NUMBER
PCD5091H QFP100 plastic quad flat package; 100 leads (lead length 1.95 mm);
PCD5091HZ LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1
1997 Jul 21 3
NAME DESCRIPTION VERSION
body 14 × 20 × 2.8 mm
PACKAGE
SOT317-2
Philips Semiconductors Objective specification
DECT baseband controller PCD5091
4 BLOCK DIAGRAM
digital pins
analog pins
TST1
TST2
CLK3
DCK
BZP
BZM
EARP
DI
DO
FS1
EARM
LIFP
LIFM
MICP
MICM
VMIC
ref
V
VANLI
RSSI_AN
VBAT
3 ×
DD5V
V
DDA
V
SSA
V
2 ×
DD3V
V
SS
5 ×
V
DD_RF
V
PORT 3.7
PORT 3.0 to
PORT 2.7
PORT 2.0 to
8 8 8
PORT 1.7
PORT 1.0 to
8
PORT 0.7
PORT 0.0 to
DD
V
PORT 3
PORT 1 PORT 2
PORT 0
PCD5091
IB-BUS
80CL51- CORE
(TCB)
TEST CONTROL BLOCK
DD
V
C-BUS
2
I
(256 BYTES)
MICROCONTROLLER-RAM
AUX-RAM
(3 kBYTES)
ROM
(64 kBYTES)
(SPI)
IOM/ADPCM
SPEECH INTERFACE
(ABB)
BUZZER BUFFER
DD
V
MICROCONTROLLER
DD
V
DD
V
INTERFACE (ABCIF)
AB-MICROCONTROLLER
DD
V
DD_RF
V
ref
PEAK-HOLD
3 : 1
MUX
ANALOG
SOURCE
VOLTAGE
(AVR)
REFERENCE
OF
(DCA)
ANALOG
(IBC)
RESET
(TICB)
WATCHDOG
XTAL
(CLG)
V
SUBTRACT
ADC
V
(AVS)
(POR)
POWER-ON-RESET
(RGE)
GENERATOR
(WDT)
TIMER
(XOSC)
OSCILLATOR
ARA
ARF
ARD
1-BIT ADC
DDA
V
s
108f
(DNS)
NOISE
DIGITAL
s
4f
LEVEL
SHIFTER
SHAPER
BURST
DIGITAL
MODE
LOGIC
(DSP)
SIGNAL
PROCESSOR
RAM
DATA
SYSTEM
(BML)
DIGITAL
AMP
Σ ∆
ATS
1-BIT ADC
s
108f
(DDF)
FILTER
DECIMATING
s
4f
(SDR)
(1 kBYTE)
CDC-on
DDA
V
CODEC
AGM
AUXILIARY ADC (AAD)
DDA
V
DIGITAL
CONTROL
ISB BUS
CONTROLLER
BLOCK
TIMING CONTROL
CLOCK
GENERATOR
DD
V
ref
V
ANALOG VOLTAGE
MGD800
VANLO
EN_WATCHDOG RESET_OUT M_RESET VBGP
SSO
V
DDO
V
handbook, full pagewidth
Fig.1 Block diagram.
PSE
EA
ALE
A16
R_PWR
R_ENABLE
SLICE_CTR
REF_CLK
S_ENABLE
SYNTH_LOCK
S_CLK
S_DATA
S_PWR
VCO_BND_SW
1997 Jul 21 4
ANT_SW1
ANT_SW0
T_ENABLE
T_DATA
R_DATAP
R_DATAM
T_PWR_RMP
R_SLICED
T_GMSK
GP_CLK7
DPLL_DATA
XTAL1
XTAL2
CLK100
Philips Semiconductors Objective specification
DECT baseband controller PCD5091
5 PINNING INFORMATION
5.1 Pinning
handbook, full pagewidth
T_ENABLE
T_PWR_RMP
VCO_BND_SW
SYNTH_LOCK
S_ENABLE
SLICE_CTR
R_ENABLE
ANT_SW1
ANT_SW0
CLK100
T_DATA
T_GMSK
S_DATA
S_CLK
S_PWR
REF_CLK
V
SS1
V
DD_RF
V
DD3V_1
R_PWR
R_DATAP
R_DATAM
RSSI_AN
VANLI
VBAT
CLK3
DCK
FS1
DO
RESET_OUT
M_RESET
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
99989796959493929190898887868584838281
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DI
28
29
30
P0.6
P0.7
V
PCD5091
DD5V_3VSS5
EA
ALE
PSE
P2.7
P2.6
P2.5
P2.4
P2.3
80
TST2
79
TST1
78
V
V
77
A16
76
75
P2.2
P2.1
74
P2.0
73
P3.7
72
71
P3.6
P3.5
70
P3.4
69
P3.3
68
67
P3.2
P3.1
66
P3.0
65
V
64
V
63
BZP
62
BZM
61
V
60
59
P1.7
P1.6
58
P1.5
57
P1.4
56
55
P1.3
V
54
R_SLICED
53
DPLL_DATA
52
GP_CLK7
51
SS4
DD5V_2
SS3
SS2
DD3V_2
DD5V_1
31323334353637383940414243444546474849
XTAL2
XTAL1
SSO
V
VANLO
DDO
V
LIFM
LIFP
SSA
V
MICM
Fig.2 Pin configuration (QFP100).
1997 Jul 21 5
MICP
VMIC
50
MBH938
ref
V
DDA
VBGP
V
EARM
P1.0
EARP
EN_WATCHDOG
P1.1
P1.2
Loading...