• Low output distortion with on-chip filtering conforming to
CEPT recommendations
• Latched inputs for data bus applications
• I2C-bus compatible
• Selection of parallel or serial (I2C-bus) data input
(PCD3311C).
used, and a separate microcontroller is required to control
the devices.
Both the devices can interface to I
2
C-bus compatible
microcontrollers for serial input. The PCD3311C can also
interface directly to all standard microcontrollers,
accepting a binary coded parallel input.
With their on-chip voltage reference the PCD3311C and
PCD3312C provide constant output amplitudes which are
independent of the operating supply voltage and ambient
temperature.
An on-chip filtering system assures a very low total
2GENERAL DESCRIPTION
The PCD3311C and PCD3312C are single-chip silicon
gate CMOS integrated circuits. They are intended
principally for use in telephone sets to provide the
dual-tone multi-frequency (DTMF) combinations required
for tone dialling systems. The various audio output
frequencies are generated from an on-chip 3.58 MHz
quartz crystal-controlled oscillator. A separate crystal is
harmonic distortion in accordance with CEPT
recommendations.
In addition to the standard DTMF frequencies the devices
can also provide:
• Twelve standard frequencies used in simplex modem
applications for data rates from 300 to 1200 bits per
second
• Two octaves of musical scales in steps of semitones.
3QUICK REFERENCE DATA
SYMBOLPARAMETERMIN.TYP.MAX.UNIT
V
DD
I
DD
I
stb
V
HG(RMS)
V
LG(RMS)
G
v
operating supply voltage2.5−6.0V
operating supply current−−0.9mA
standby current−−3µA
DTMF HIGH group output voltage level (RMS value)158192205mV
DTMF LOW group output voltage level (RMS value)125150160mV
pre-emphasis (voltage gain) of group1.852.102.35dB
THDtotal harmonic distortion−−25−dB
T
amb
operating ambient temperature−25−+70°C
4ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAMEDESCRIPTIONVERSION
PCD3311CPDIP14plastic dual in-line package; 14 leads (300 mil)SOT27-1
PCD3311CTSO16plastic small outline package; 16 leads; body width 7.5 mmSOT162-1
PCD3312CPDIP8plastic dual in-line package; 8 leads (300 mil)SOT97-1
PCD3312CTSO8plastic small outline package; 8 leads; body width 7.5 mmSOT176-1
The Input Control Logic decodes the input data to
determine whether DTMF, modem or musical tones are
selected; and which particular tone or combination of
tones is required.
A code representing the required tones is sent to the
Divider Selection ROM which selects the correct division
ratio in both of the Frequency Dividers (or in one divider, if
only a single tone is required).
The Oscillator circuit provides a square wave of frequency
3.58 MHz. Each Frequency Divider divides the frequency
of the Oscillator to give a serial digital square wave with a
frequency simply related to that of the required tone.
The output from each Frequency Divider goes to a DAC,
which is also fed by a clock derived from the oscillator.
Using these two signals, the DAC produces an
approximate sine wave of the required frequency, with an
amplitude derived from the Voltage Reference.
The output from the DAC goes to an Adder where, for
DTMF, it is combined with the output from the other DAC.
The output from the Adder goes through two stages of Low
Pass Filters to give a smoothed tone (single or dual), and
finally to the TONE output.
7.4Data inputs (PCD3311C)
Inputs D0, D1, D2, D3, D4 and D5 are used in the parallel
data input mode of the PCD3311C. Inputs D0 and D1 are
also used in serial input mode when they act as the SCL
and SDA inputs respectively. Inputs D0 and D1 have no
internal pull-down or pull-up resistors and must not be left
open in any application. Inputs D2, D3, D4 and D5 have
internal pull-down.
D4 and D5 are used to select between DTMF dual, DTMF
single, modem and musical tones (see Table 1). D0, D1,
D2 and D3 select the tone combination or single tone
within the selected application. They also, in combination
with D4, select the standby mode. See Tables 2, 3, 4
and 5.
PCD 3312C has no parallel data pins as data input is via
2
C-bus.
the I
Table 1 Use of D5 and D4 to select application
D5D4APPLICATION
LOW LOW DTMF single tones; musical tones;
standby
LOW HIGH DTMF dual tones (all 16 combinations)
HIGH LOW modem tones
HIGH HIGH musical tones
7.2Clock/oscillator connection
The timebase for the PCD3311C and PCD3312C is a
crystal-controlled oscillator, requiring a 3.58 MHz quartz
crystal to be connected between OSCI and OSCO.
Alternatively, the OSCI input can be driven from an
external clock of 3.58 MHz.
7.3Mode selection (PCD3311C)
The MODE input selects the data input mode for the
PCD3311C. When MODE is connected to V
(HIGH),
DD
data can be received in the parallel mode. When
connected to VSS (LOW) or left open, data can be received
via the serial I2C-bus.
PCD 3312C has no MODE input as data input is via the
I2C-bus only.
7.5Strobe input (PCD3311C )
The STROBE input (with internal pull-down) allows the
loading of parallel data into D0 to D5 when MODE is HIGH.
The data inputs must be stable preceding the
positive-going edge of the strobe pulse (active HIGH).
Input data are loaded at the negative-going edge of the
strobe pulse and then the corresponding tone (or standby
mode) is provided at the TONE output. The output remains
unchanged until the negative-going edge of the next
STROBE pulse (for new data) is received. Figure 5 is an
example of the timing relationship between STROBE and
the data inputs.
When MODE is LOW, data is received serially via the
Fig.5Timing of STROBE, parallel data inputs and TONE output (770 Hz + 1477 Hz in example) in the parallel
mode (MODE = HIGH).
7.6I2C-bus clock and data inputs
SCL and SDA are the serial clock and serial data inputs
according to the I2C-bus specification, see Chapter 8.
SCL and SDA must be pulled up externally to VDD.
For the PCD3311C, SCL and SDA are combined with
parallel inputs D0 and D1 respectively - D0/SCL and
D1/SDA operate serially only when MODE is LOW.
7.7Address input
Address input A0 defines the least significant bit of the
2
C-bus address of the device (see Fig.6). The first 6 bits
I
of the address are fixed internally. By tying the A0 of each
device to VDD (HIGH) and VSS(LOW) respectively, two
different PCD3311C or PCD3312C devices can be
individually addressed on the bus.
Whether one or two devices are used, A0 must be
connected to VDD or VSS.
1996 Nov 217
7.8I
2
C-bus data configuration (see Fig.6)
The PCD3311C and PCD3312C are always slave
receivers in the I2C-bus configuration. The R/W bit in is
thus always LOW, indicating that the master
(microcontroller) is writing.
The slave address in the serial mode consists of 7 bits: 6
bits internally fixed, 1 externally set via A0. in the serial
mode, the same input data codes are used as in the
parallel mode. See Tables 2, 3, 4 and 5.
7.9Tone output
The single and dual tones provided at the TONE output are
first filtered by an on-chip switched-capacitor filter,
followed by an active RC low-pass filter. The filtered tones
fulfil the CEPT recommendations for total harmonic
distortion of DTMF tones. An on-chip reference voltage
provides output tone levels independent of the supply
voltage. Tables 3, 4 and 5 give the frequency deviation of
the output tones with respect to the standard DTMF,
modem and music frequencies.
In order to avoid an undefined state when the power is switched ON, the devices have an internal reset circuit which sets
the standby mode (oscillator OFF).
7.11TABLES OF INPUT AND OUTPUT
The specified output tones are obtained when a 3.579545 MHz crystal is used.
In each table, the logical states for the input data lines are related to voltage levels as follows:
1 = HIGH = V
0 = LOW = V
DD
SS
X = don’t care
Table 2 Input data for no output tone, TONE in 3-state
D5D4D3D2D1D0HEX
(1)
X0000000 or 20ON
X0000101 or 21OFF
X0001002 or 22OFF
X0001103 or 23OFF
Note
1. The alternative HEX values depend on the value of D5.