Philips p80c528, p83c524, p83c528 DATASHEETS

INTEGRATED CIRCUITS

DATA SHEET

P83C524; P80C528; P83C528

8-bit microcontrollers

Product specification			1997 Dec 15
File under Integrated Circuits, IC20

Philips Semiconductors Product specification

	8-bit microcontrollers			P83C524; P80C528;
				P83C528
	CONTENTS		15	IDLE AND POWER-DOWN OPERATION
	1	FEATURES	15.1	Power Control Register (PCON)
			15.2	Idle Mode
	2	GENERAL DESCRIPTION
			15.3	Power-down Mode
	3	QUICK REFERENCE DATA	15.4	Wake-up from Power-down Mode
	4	ORDERING INFORMATION	16	OSCILLATOR CIRCUIT
	5	BLOCK DIAGRAM	17	RESET CIRCUIT
	6	FUNCTIONAL DIAGRAM	17.1	Power-on reset
	7	PINNING INFORMATION	18	INSTRUCTION SET
	7.1	Pinning	19	LIMITING VALUES
	7.2	Pin description	20	DC CHARACTERISTICS
	8	FUNCTIONAL DESCRIPTION	21	AC CHARACTERISTICS
	8.1	General	21.1	AC Characteristics 16 MHz version
	8.2	Instruction Set Execution	21.2	AC Characteristics 24 MHz version
	9	MEMORY ORGANIZATION	22	I2C CHARACTERISTICS (BIT-LEVEL)
	9.1	Program Memory	23	XTAL1 CHARACTERISTICS
	9.2	Internal Data Memory	24	SERIAL PORT CHARACTERISTICS
	9.3	Addressing
			25	TIMING DIAGRAMS
	10	I/O FACILITIES
			25.1	Timing symbol definitions
	11	TIMERS/COUNTERS
			26	PACKAGE OUTLINES
	11.1	Timer 0 and Timer 1
			27	SOLDERING
	11.1.1	Timer/Counter Mode Control register (TMOD)
	11.1.2	Timer/Counter Control Register (TCON)	27.1	Introduction
	11.2	Timer 2	27.2	DIP
	11.2.1	Timer 2 Control Register (T2CON)	27.2.1	Soldering by dipping or by wave
	11.2.2	Capture Mode	27.2.2	Repairing soldered joints
	11.2.3	Automatic Reload Mode	27.3	PLCC and QFP
	11.2.4	Baud Rate Generator Mode	27.3.1	Reflow soldering
	11.3	Watchdog Timer T3	27.3.2	Wave soldering
	12	SERIAL PORT (UART)	27.3.3	Repairing soldered joints
	12.1	Serial Port Control Register (SCON)	28	DEFINITIONS
	12.2	SM0 and SM1 operating modes (SCON)	29	LIFE SUPPORT APPLICATIONS
	13	BIT-LEVEL I2C INTERFACE	30	PURCHASE OF PHILIPS I2C COMPONENTS

13.1I2C Interrupt Register (S1INT)

13.2Single-bit Data Register with I2C Auto-clock (S1BIT)

13.2.1Reading or Writing the S1BIT SFR

13.3Control and Status Register for the I2C-bus (S1SCS)

14 INTERRUPT SYSTEM

14.1Interrupt Enable Register (IE)

14.2Interrupt Priority Register (IP)

14.3 Interrupt Vectors

1997 Dec 15

2

Philips Semiconductors	Product specification
8-bit microcontrollers	P83C524; P80C528; P83C528

1 FEATURES

∙80C51 CPU

∙32 kbytes on-chip ROM, expandable externally to

64 kbytes Program Memory address space

∙P83C524:

–16 kbytes on-chip ROM, expandable externally from

32 kbytes to 64 kbytes Program Memory address space (address space 16 k to 32 k not usable)

∙P80C528:

–ROMless version of P83C528

∙P83C528:

–32 kbytes on-chip ROM, expandable externally from

32 kbytes to 64 kbytes Program Memory address space

∙EPROM versions are available: see separate data sheet P87C524 and P87C528

∙512 bytes on-chip RAM, expandable externally to

64 kbytes Data Memory address space

∙Four 8-bit I/O ports

∙Full-duplex UART compatible with the standard 80C51 and the 8052

∙Two standard 16-bit timer/counters

∙An additional 16-bit timer (functionally equivalent to the timer 2 of the 8052)

∙On-chip Watchdog Timer (WDT) with an own oscillator

∙Bit-level I2C-bus hardware serial I/O Port

∙7-source and 7-vector interrupt structure with 2 priority levels

∙Up to 3 external interrupt request inputs

∙Two programmable power reduction modes (Idle and Power-down)

∙Termination of Idle mode by any interrupt, external or WDT (watchdog) reset

∙Wake-up from Power-down by external interrupt, external or WDT reset

∙ROM code protection

∙XTAL frequency range: 3.5 MHz to 16 MHz and 3.5 MHz to 24 MHz

∙All packaging pin-outs fully compatible to the standard 8051/8052.

2 GENERAL DESCRIPTION

The P83C524 and P83C528 single-chip 8-bit microcontrollers are manufactured in an advanced CMOS process and are derivatives of the PCB80C51 microcontroller family. These devices provide architectural enhancements that make them applicable in a variety of applications in general control systems, especially in those systems which need a large ROM and RAM capacity on chip.

The P83C524 and P83C528 contain a non-volatile

16 k × 8 respectively 32 k × 8 read-only program memory, a volatile 512 bytes × 8 read/write data memory, four 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51), a 16-bit timer (identical to the timer 2 of the 8052), a multi-source, two-priority-level, nested interrupt structure, two serial interfaces (UART and bit-level I2C-bus), a watchdog timer (WDT) with a separate oscillator, an on-chip oscillator and timing circuits. For systems that require extra capability, the P83C524 and P83C528 can be expanded using standard TTL compatible memories and logic.

The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The P83C524 and P83C528 have the same instruction set as the PCB80C51 which consists of over 100 instructions: 49 one-byte, 46 two-byte and 16 three-byte. With a 16 MHz crystal, 58% of the instructions are executed in 750 ns and 40% in 1.5 μs. Multiply and divide instructions require 3 μs.

1997 Dec 15

3

Philips Semiconductors

Product specification

8-bit microcontrollers

P83C524; P80C528; P83C528

3

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITION

MIN.

MAX.

UNIT

P83C524, P80C528, P83C528 (see characteristics tables for extended temperature range versions)

VDD

supply voltage range

4.5

5.5

V

IDD

supply current: operating modes 16 MHz

VDD = 5.5 V, fCLK = 16 MHz

−

33

mA

IID

supply current: Idle mode 16 MHz

VDD = 5.5 V, fCLK = 16 MHz

−

6

mA

IPD

supply current: Power-down mode

2V ≤ VPD ≤ VDD max.

−

100

μA

Ptot

total power dissipation

−

1

W

Tstg

storage temperature range

−65

+150

°C

Tamb

operating ambient temperature range

−40

+85

°C

4

ORDERING INFORMATION

EXTENDED

PACKAGE

TEMPERATURE

FREQ.

TYPE NUMBER

NAME

DESCRIPTION

VERSION

RANGE (°C)

(MHZ)

ROMless

P80C528EBP

DIP40

plastic dual in-line package;

SOT129-1

0 to +70

3.5 to 16

40 leads (600 mil)

P80C528EFP

−40 to +85

P80C528IBP

0 to +70

3.5 to 24

P80C528IFP

−40 to +85

P80C528EBA

PLCC44

plastic leaded chip carrier; 44 leads

SOT187-2

0 to +70

3.5 to 16

P80C528EFA

−40 to +85

P80C528IBA

0 to +70

3.5 to 24

P80C528IFA

−40 to +85

P80C528EBB

QFP44

plastic quad flat package;

SOT307-2

0 to +70

3.5 to 16

44 leads (lead length 1.3 mm);

P80C528EFB

−40 to +85

body 10 × 10 × 1.75 mm

P80C528IBB

0 to +70

3.5 to 24

P80C528IFB

−40 to +85

ROM

P83C524EBP

DIP40

plastic dual in-line package;

SOT129-1

0 to +70

3.5 to 16

40 leads (600 mil)

P83C524EFP

−40 to +85

P83C524IBP

0 to +70

3.5 to 24

P83C524IFP

−40 to +85

P83C524EBA

PLCC44

plastic leaded chip carrier; 44 leads

SOT187-2

0 to +70

3.5 to 16

P83C524EFA

−40 to +85

P83C524IBA

0 to +70

3.5 to 24

P83C524IFA

−40 to +85

P83C524EBB

QFP44

plastic quad flat package;

SOT307-2

0 to +70

3.5 to 16

44 leads (lead length 1.3 mm);

P83C524EFB

−40 to +85

body 10 × 10 × 1.75 mm

P83C524IBB

0 to +70

3.5 to 24

P83C524IFB

−40 to +85

1997 Dec 15

4

Philips Semiconductors					Product	specification
8-bit microcontrollers			P83C524; P80C528; P83C528
EXTENDED		PACKAGE			TEMPERATURE		FREQ.
TYPE NUMBER	NAME	DESCRIPTION		VERSION	RANGE (°C)		(MHZ)
P83C528EBP	DIP40	plastic dual in-line package;		SOT129-1	0 to +70		3.5 to 16
		40 leads (600 mil)
P83C528EFP					−40 to +85
P83C528IBP					0 to +70		3.5 to 24
P83C528IFP					−40 to +85
P83C528EBA	PLCC44	plastic leaded chip carrier; 44 leads		SOT187-2	0 to +70		3.5 to 16
P83C528EFA					−40 to +85
P83C528IBA					0 to +70		3.5 to 24
P83C528IFA					−40 to +85
P83C528EBB	QFP44	plastic quad flat package;		SOT307-2	0 to +70		3.5 to 16
		44 leads (lead length 1.3 mm);
P83C528EFB					−40 to +85
		body 10 × 10 × 1.75 mm
P83C528IBB					0 to +70		3.5 to 24
P83C528IFB					−40 to +85

1997 Dec 15

5

_

frequency

microcontrollersbit-8

Semiconductors Philips

reference

counters

XTAL2

XTAL1

T0

T1

T2

T2EX

RST

15Dec1997

DIAGRAMBLOCK5

RAM

AUX - RAM

PROGRAM

OSCILLATOR

PROGRAM

DATA

DATA

TWO 16-BIT

MEMORY

16-BIT

WATCHDOG

AND

MEMORY

MEMORY

MEMORY

TIMER/EVENT

(32 K x 8

TIMER

TIMER

TIMING

(32 K x 8 ROM/

(256 x 8 RAM)

(256 x 8 RAM)

COUNTERS

or 16EPROM)K x 8 ROM)

6

CPU

P83C524

P80C528

P83C528

64K-BYTE BUS

PROGRAMMABLE

BIT-LEVEL

P83C524;

SERIAL PORT

PROGRAMMABLE I/O

I 2 C

EXPANSION

FULL DUPLEX UART

internal

CONTROL

SYNCHRONOUS

INTERFACE

SHIFT

interrupts

MBC455

INT0

INT1

control

parallel ports,

serial in

serial out

SDA

SCL

P83C528 P80C528;

address/data bus

external interrupts

and I/O pins

shared with Port 3

full pagewidth

specification Product

Fig.1

Block diagram.

handbook,

Philips Semiconductors	Product specification
8-bit microcontrollers	P83C524; P80C528; P83C528
6 FUNCTIONAL DIAGRAM

	VSS	VDD	RST
	XTAL1
	XTAL2
			Port 0	address and
				data bus
	EA
				T2
	PSEN			T2EX
	ALE	P83C524
		P80C528	Port 1
		P83C528
		P83C528
				SCL
				SDA
	RXD / data
	TXD / clock
	INT0
alternative	INT1		Port 2	address bus
functions	Port 3
	T0

T1

WR

RD

MBC454 - 1

Fig.2 Functional diagram.

1997 Dec 15

7

Philips Semiconductors	Product specification
8-bit microcontrollers	P83C524; P80C528; P83C528

7 PINNING INFORMATION

7.1Pinning

handbook, halfpage

VDD

T2 P1.0

1

40

T2EX P1.1

P0.0

AD0

2

39

P1.2

P0.1

AD1

3

38

P1.3

P0.2

AD2

4

37

P1.4

P0.3

AD3

5

36

P1.5

P0.4

AD4

6

35

SCL P1.6

P0.5

AD5

7

34

SDA P1.7

P0.6

AD6

8

33

RST

P0.7

AD7

9

32

RXD / data P3.0

10

P83C524

31

EA

P80C528

P83C528

TXD / clock P3.1

11

P83C528

30

ALE

INT0 P3.2

12

29

PSEN

INT1 P3.3

13

28

P2.7

A15

T0

P3.4

P2.6

A14

14

27

T1

P3.5

15

26

P2.5

A13

WR

P3.6

16

25

P2.4

A12

RD

P3.7

17

24

P2.3

A11

XTAL2

18

23

P2.2

A10

XTAL1

19

22

P2.1

A9

VSS

20

21

P2.0

A8

MBC453

Fig.3 Pin configuration DIP40 (SOT129-1).

1997 Dec 15

8

Philips Semiconductors	Product specification
8-bit microcontrollers	P83C524; P80C528; P83C528

handbook, full pagewidth

																										/ T2EX					/ T2								DD				/ AD0				/ AD1			/ AD2				/ AD3
															P1.4			P1.3				P1.2				P1.1					P1.0				n.c.								P0.0				P0.1			P0.2				P0.3
																																						V
														6				5			4				3					2				1				44				43				42				41			40
															44				43			42				41					40				39				38				37				36				35			34
			P1.5	7																																																					39				P0.4		/ AD4
	SCL / P1.6				8																																																					38			P0.5		/ AD5
					1																																																					33
	SDA / P1.7						9																																																			37			P0.6		/ AD6
							2																																																			32
			RST			10																																																				36			P0.7		/ AD7
						3																																																				31
RXD / data / P3.0					11																																																					35			EA
					4																										P83C524																											30
																															P80C528
			n.c.			12																									P83C528																											34			n.c.
						5																									P83C528																											29
TXD / clock / P3.1					13																																																					33			ALE
					6																																																					28
	INT0 / P3.2							14																																																		32			PSEN
								7																																																		27
	INT1 / P3.3					15																																																				31			P2.7		/ A15
						8																																																				26
	T0 / P3.4								16																																																	30			P2.6		/ A14
									9																																																	25
	T1 / P3.5			17																																																						29			P2.5		/ A13
				10																																																						24
																																																										23
					11
																																																										MBC452
														18				19			20				21					22				23				24				25				26				27			28
															/WRP3			/RDP3.7				XTAL214				XTAL1				V				17					P2.0/				P2.1				/P2.2				P2.3/			/P2.4
				.6													13								15						SS				n.c.				A8				A9				A1020				A11			A1222
				12																										16								18				19/								21

Fig.4 Pin configuration QFP44 (SOT307-2).

1997 Dec 15

9

Philips Semiconductors	Product specification
8-bit microcontrollers	P83C524; P80C528; P83C528

													/ T2EX			/ T2				DD		/ AD0		/ AD1		/ AD2		/ AD3
							P1.4		P1.3		P1.2		P1.1			P1.0		n.c.				P0.0		P0.1		P0.2		P0.3
																				V
							6		5		4		3			2		1		44		43		42		41		40
			P1.5	7																										39		P0.4		/ AD4
	SCL / P1.6			8																										38		P0.5		/ AD5
	SDA / P1.7			9																										37		P0.6		/ AD6
			RST	10																										36		P0.7		/ AD7
RXD / data / P3.0				11																										35		EA
																P83C524
			n.c.	12												P83CP80C528														34		n.c.
																P83C528
TXD / clock / P3.1				13																										33		ALE
	INT0 / P3.2			14																										32		PSEN
	INT1 / P3.3			15																										31		P2.7		/ A15
	T0 / P3.4			16																										30		P2.6		/ A14
	T1 / P3.5			17																										29		P2.5		/ A13
																														MBC452
							18		19		20		21			22		23		24		25		26		27		28
							/WRP3.6		/RDP3.7		XTAL2		XTAL1			V		n.c.		P2.0/ A8		P2.1/ A9		P2.2/ A10		P2.3/ A11		P2.4/ A12
																SS

Fig.5 Pin configuration PLCC44 (SOT187-2).

1997 Dec 15

10

Philips Semiconductors	Product specification
8-bit microcontrollers	P83C524; P80C528; P83C528

7.2Pin description

Table 1 Pin description for P83C524, P80C528 and P83C528; see note 1

		SYMBOL					PIN			DESCRIPTION
						SOT 129-1	SOT 187-2	SOT 307-2
	P1.0−P1.7					1 to 8	2−9	1−3,	Port 1: 8-bit quasi-bidirectional I/O Port. Port 1 can sink/source
							(1 n.c.)	40−44	one TTL (= 4 LSTTL) input. It can drive CMOS inputs without
									external pull-ups, except P1.6 and P1.7 which have open drain
								(39 n.c.)
									outputs.
									Port 1 alternative functions:
	T2					1	2	40	P1.0	Timer/event counter 2 external event counter input
										(falling edge triggered)
	T2EX					2	3	41	P1.1	Timer/event counter 2 capture/reload trigger or external
										interrupt 2 input (falling edge triggered)
	SCL					7	8	2	P1.6	I2C-bus Serial Port clock line
	SDA					8	9	3	P1.7	I2C-bus Serial Port data line.
	RST					9	10	4	RESET: a HIGH level on this pin for two machine cycles while the
									oscillator is running, resets the device. An internal pull-down
									resistor permits power-on reset using only a capacitor connected
									to VDD. After a WDT overflow this pin is pulled HIGH while the
									internal reset signal is active.
	P3.0−P3.7					10−17	11, 13−19	5, 7−13	Port 3: 8-bit quasi-bidirectional I/O Port with internal pull-ups.
							(12 n.c.)	(6 n.c.)	Port 3 can sink/source one TTL (= 4 LSTTL) input. It can drive
									CMOS inputs without external pull-ups.
									Port 3 alternative functions:
	RXD/data					10	11	5	P3.0	Serial Port data input (asynchronous) or data
										input/output (synchronous)
	TXD/clock					11	13	7	P3.1	Serial Port data output (asynchronous) or clock output
										(synchronous)
						12	14	8	P3.2	external interrupt 0 or gate control input for timer/event
		INT0
										counter 0
						13	15	9	P3.3	external interrupt 1 or gate control input for timer/event
		INT1
										counter 1
	T0					14	16	10	P3.4	external input for timer/event counter 0
	T1					15	17	11	P3.5	external input for timer/event counter 1
						16	18	12	P3.6	external data memory write strobe
	WR
						17	19	13	P3.7	external data memory read strobe.
	RD
									The generation or use of a Port 3 pin as an alternative function is
									carried out automatically by the P83C528 provided the associated
									Special Function Register (SFR) bit is set HIGH.
	XTAL2					18	20	14	Crystal input 2: output of the inverting amplifier that forms the
									oscillator. This pin left open-circuit when an external oscillator
									clock is used (see Figures 22 and 23).

1997 Dec 15

11

Philips Semiconductors

Product specification

8-bit microcontrollers

P83C524; P80C528; P83C528

SYMBOL

PIN

DESCRIPTION

SOT 129-1

SOT 187-2

SOT 307-2

XTAL1

19

21

15

Crystal input 1: input to the inverting amplifier that forms the

oscillator, and input to the internal clock generator. Receives the

external oscillator clock signal when an external oscillator is used

(see Figures 22 and 23).

VSS

20

22

16

Ground: circuit ground potential.

P2.0-P2.7

21−28

24−31

18−25

Port 2: 8-bit quasi-bidirectional I/O Port with internal pull-ups.

(23 n.c.)

(17 n.c.)

During access to external memories (RAM/ROM) that use 16-bit

addresses (MOVX @DPTR) Port 2 emits the high-order address

byte (A8 to A15). Port 2 can sink/source one TTL (= 4 LSTTL)

input. It can drive CMOS inputs without external pull-ups.

29

32

26

Program Store Enable output: read strobe to the external

PSEN

program memory via Port 0 and Port 2. It is activated twice each

machine cycle during fetches from external program memory.

When executing out of external program memory two activations of

PSEN

are skipped during each access to external data memory.

PSEN

is not activated (remains HIGH) during no fetches from

external program memory.

PSEN

can sink/source 8 LSTTL inputs.

It can drive CMOS inputs without external pull-ups.

ALE

30

33

27

Address Latch Enable output: latches the LOW byte of the

address during access to external memory in normal operation. It

is activated every six oscillator periods except during an external

data memory access. ALE can sink/source 8 LSTTL inputs. It can

drive CMOS inputs without an external pull-up.

31

35

29

External Access input: when during RESET,

is held at a TTL

EA

EA

(34 n.c.)

(28 n.c.)

HIGH level, the CPU executes out of the internal program ROM,

provided the program counter is less than 32768. When EA is held

at a TTL LOW level during RESET, the CPU executes out of

external program memory via Port 0 and Port 2.

EA

is not allowed

to float.

P0.0-P0.7

32−39

36−43

30−37

Port 0: 8-bit open drain bidirectional I/O Port. It is also the

multiplexed low-order address and data bus during accesses to

external memory (AD0 to AD7). During these accesses internal

pull-ups are activated. Port 0 can sink/source 8 LSTTL inputs.

VDD

40

44

38

Power supply: +5 V power supply pin during normal operation,

Idle mode and Power-down mode.

Note

1.To avoid a 'latch-up' effect at power-on, the voltage on any pin (at any time) must not be higher than VDD +0.5 V or lower than VSS −0.5 V respectively.

1997 Dec 15

12

Philips Semiconductors	Product specification
8-bit microcontrollers	P83C524; P80C528; P83C528

8 FUNCTIONAL DESCRIPTION

8.1General

The P83C524, P80C528 and P83C528 are stand-alone high-performance microcontrollers designed for use in real time applications such as instrumentation, industrial control, medium to high-end consumer applications and specific automotive control applications.

In addition to the 80C51 standard functions, the devices provide a number of dedicated hardware functions for these applications. The P83C524 and P83C528 are control-oriented CPUs with on-chip program and data memory. They can be extended with external program memory up to 64 kbytes. They can also access up to

64 kbytes of external data memory. For systems requiring extra capability, the P83C524 and P83C528 can be expanded using standard memories and peripherals.

The P83C524, P80C528 and P83C528 have two software selectable modes of reduced activity for further power reduction: Idle and Power-down. The Idle mode freezes the CPU while allowing the RAM, timers, serial ports and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator causing all other chip functions to be inoperative except the WDT if it is enabled. The Power-down mode can be terminated by an external reset, a WDT overflow, and in addition, by either of the two external interrupts.

8.2Instruction Set Execution

The P83C524, P80C528 and P83C528 use the powerful instruction set of the 80C51. Additional SFRs are incorporated to control the on-chip peripherals. The instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. When using a 16 MHz oscillator, 64 instructions execute in 750 ns and 45 instructions execute in 1.5 s. Multiply and divide instructions execute in 3 μs (see Chapter 18).

9 MEMORY ORGANIZATION

The central processing unit (CPU) manipulates operands in three memory spaces; these are the 64 kbyte external data memory (of which the lower 256 bytes reside in the internal AUX-RAM), 512 byte internal data memory (consisting of 256 bytes standard RAM and 256 bytes AUX-RAM) and the 64 kbyte internal and external program memory.

9.1Program Memory

The program memory address space of the P83C528 comprises an internal and an external memory portion. The P83C528 has 32 kbyte of program memory on-chip. The program memory can be externally expanded up to 64 kbyte. If the EA pin is held HIGH, the P83C528 executes out of the internal program memory unless the address exceeds 7FFFH. Locations 8000H through 0FFFFH are then fetched from the external program memory. If the EA pin is held LOW, the P83C528 fetches all instructions from the external program memory. Fig.6 illustrates the program memory address space.

By setting a mask programmable security bit the ROM content is protected i.e. it cannot be read out by any test mode or by any instruction in the external program memory space. The MOVC instructions are the only ones which have access to program code in the internal or external program memory. The EA input is latched during RESET and is 'don't care' after RESET. This implementation prevents reading from internal program code by switching from external program memory to internal program memory during MOVC instruction or an instruction that handles immediate data. Table 2 lists the access to the internal and external program memory by the MOVC instructions when the security bit has been set to a logical one. If the security bit has been set to a logical 0 there are no restrictions for the MOVC instructions.

64 K

handbook, halfpage

EXTERNAL

32768
32767								32767
			INTERNAL							EXTERNAL
16383 (1)				(EA = 1)							(EA = 0)
0								0

(1) Only for P83C524.	PROGRAM MEMORY MBC456 - 1

Fig.6 Program Memory Address Space.

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	Philips Semiconductors		Product specification
	8-bit microcontrollers	P83C524; P80C528; P83C528
	Table 2 Internal and external program memory access with security bit set
	INSTRUCTION	ACCESS TO INTERNAL	ACCESS TO EXTERNAL
		PROGRAM MEMORY	PROGRAM MEMORY
	MOVC in internal program memory	YES	YES
	MOVC in external program memory	NO	YES

9.2Internal Data Memory

The internal data memory is divided into three physically separated parts: 256 byte of RAM, 256 byte of AUX-RAM, and a 128 byte special function area (SFR). These parts can be addressed as follows (see Table 3 and Fig.11):

∙RAM 0 to 127 can be addressed directly and indirectly as in the 80C51. Address pointers are R0 and R1 of the selected register bank.

∙RAM 128 to 255 can only be addressed indirectly. Address pointers are R0 and R1 of the selected register bank.

∙AUX-RAM 0 to 255 is indirectly addressable as the external data memory locations 0 to 255 with the MOVX instructions. Address pointers are R0 and R1 of the selected register bank and DPTR. When executing from internal program memory, an access to AUX-RAM 0 to 255 will not affect the ports P0, P2, P3.6 and P3.7.

∙the SFRs can only be addressed directly in the address range from 128 to 255.

An access to external data memory locations higher than 255 will be performed with the MOVX DPTR instructions in the same way as in the 80C51 structure, i.e. with P0 and P2 as data/address bus and P3.6 and P3.7 as write and read timing signals (see Figures 7, 8, 9 and 10). Note that the external data memory cannot be accessed with R0 and R1 as address pointer.

Fig.11 shows the internal and external data memory address space. Fig.12 shows the Special Function Register (SFR) memory map. Four 8-bit register banks occupy locations 0 through 31 in the lower RAM area. Only one of these banks may be enabled at a time. The next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations.

The stack can be located anywhere in the internal 256 byte RAM. The stack depth is only limited by the available internal RAM space of 256 bytes. All registers except the Program Counter and the four 8-bit register banks reside in the SFR address space.

Table 3 Internal data memory access

LOCATION	ADDRESSED
RAM 0 to 127	DIRECT and INDIRECT
RAM 128 to 255	INDIRECT only
AUX-RAM 0 to 255	INDIRECT only with MOVX
Special Function Register (SFR) 128 to 255	DIRECT only

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Philips Semiconductors	Product specification
8-bit microcontrollers	P83C524; P80C528; P83C528

handbook, full pagewidth

one machine cycle

one machine cycle

S1

S2

S3

S4

S5

S6

S1

S2

S3

S4

S5

S6

ALE

PSEN

RD

WR

P2

P2 OUT

P0

P0 OUT

MBC457

a. Without a MOVX.

cycle 1

cycle 2

S1

S2

S3

S4

S5

S6

S1

S2

S3

S4

S5

S6

ALE

PSEN

RD

WR

P2

P2 OUT

P0

P0 OUT

MBC458

b. With a MOVX to the AUX-RAM (read and write).

Fig.7	Internal program memory execution.
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Philips Semiconductors	Product specification
8-bit microcontrollers	P83C524; P80C528; P83C528

handbook, full pagewidth

cycle 1

cycle 2

S1

S2

S3

S4

S5

S6

S1

S2

S3

S4

S5

S6

ALE

PSEN

RD

WR

P2

P2 OUT

DPH OUT

P2 OUT

P0

P0 OUT

DPL

DATA

OUT

IN

MBC459

a. With a MOVX to the External Data Memory (read).

handbook, full pagewidth

cycle 1

cycle 2

S1

S2

S3

S4

S5

S6

S1

S2

S3

S4

S5

S6

ALE

PSEN

RD

WR

P2

P2 OUT

P2 OUT

DPH OUT

P0

P0 OUT

DPL

DATA OUT

OUT

MBC460

b. With a MOVX to the External Data Memory (write).

Fig.8	Internal program memory execution (continued).
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Philips Semiconductors	Product specification
8-bit microcontrollers	P83C524; P80C528; P83C528

handbook, full pagewidth

one machine cycle

one machine cycle

ALE

S1

S2

S3

S4

S5

S6

S1

S2

S3

S4

S5

S6

PSEN

RD

WR

P2

PCH OUT

PCH OUT

PCH OUT

PCH OUT

PCH OUT

P0

INST

PCL

INST

PCL

INST

PCL

INST

PCL

IN

OUT

IN

OUT

IN

OUT

IN

OUT

MBC461

a. Without a MOVX.

cycle 1 cycle 2

S1

S2

S3

S4

S5

S6

S1

S2

S3

S4

S5

S6

ALE

PSEN

RD

WR

	P2	PCH OUT		PCH OUT		ADDRH OUT	PCH OUT
	P0	INST	PCL	INST	ADDRL		PCL
		IN	OUT	IN	OUT		OUT
					(read)
	P2	PCH OUT		PCH OUT		ADDRH OUT	PCH OUT
	P0	INST	PCL	INST	ADDRL	DATA OUT	PCL
		IN	OUT	IN	OUT		OUT
					(write)		MBC462

b.With a MOVX to the AUX-RAM (read and write).

Fig.9 External program memory execution.

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Philips Semiconductors	Product specification
8-bit microcontrollers	P83C524; P80C528; P83C528

cycle 1 cycle 2 handbook, full pagewidth

S1

S2

S3

S4

S5

S6

S1

S2

S3

S4

S5

S6

ALE

PSEN

RD

WR

P2

PCH OUT

PCH OUT

DPH OUT

PCH OUT

P0

INST

PCL

INST

DPL

DATA

PCL

IN

OUT

IN

OUT

IN

OUT

MBC463

a. With a MOVX to the External Data Memory (read).

cycle 1 cycle 2 handbook, full pagewidth

S1

S2

S3

S4

S5

S6

S1

S2

S3

S4

S5

S6

ALE

PSEN

RD

WR

P2

PCH OUT

PCH OUT

DPH OUT

PCH OUT

INST

PCL

INST

DPL

PCL

P0

DATA OUT

IN

OUT

IN

OUT

OUT

MBC464

b. With a MOVX to the External Data Memory (write).

Fig.10	External program memory execution (continued).
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Philips Semiconductors	Product specification
8-bit microcontrollers	P83C524; P80C528; P83C528

SHARED

ADDRESS LOCATION

FF

FF

FF

FFFF

UPPER

SPECIAL

128 BYTES

FUNCTION

INTERNAL

REGISTERS

80

RAM

80

AUX - RAM

EXTERNAL

256 BYTES

DATA

7F

MEMORY

LOWER

128 BYTES

INTERNAL

00

00

RAM

0100

DATA MEMORY

register

direct byte

indirect

addressing

addressing

MBC466 - 1

Fig.11 Internal and external data memory address space.

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Philips Semiconductors	Product specification
8-bit microcontrollers	P83C524; P80C528; P83C528

REGISTER				BIT MNEMONIC /					DIRECT BYTE
MNEMONIC				BIT ADDRESS (HEX)					ADDRESS (HEX)
T3									FFH
B	F7	F6	F5	F4	F3	F2	F1	F0	F0H
ACC	E7	E6	E5	E4	E3	E2	E1	E0	E0H

S1INT

S1BIT

S1SCS

								DAH
								D9H
SDI/	SCI/
SDO	SCO	CLH	BB	RBF	WBF	STR	ENS
DF	DE	DO	DC	DB	DA	D9	D8	D8H

CY

AC

FO

RSI

RSO

OV

FI

P

PSW

D7

D6

D5

D4

D3

D2

D1

D0

D0H

TH2

CDH

TL2

CCH

RCAP2H

CBH

RCAP2L

CAH

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

T2CON

CF

CE

CD

CC

CB

CA

C9

C8

C8H

- - -

PS1

PT2

PS

PT1

PX1

PT0

PX0

IP

BF

BE

BD

BC

BB

BA

B9

B8

B8H

P3

B0H

B7

B6

B5

B4

B3

B2

B1

B0

EA

ES1

ET2

ES

ET1

EX1

ET0

EX0

IE

AF

AE

AD

AC

AB

AA

A9

A8

A8H

WDCON

A5H

P2

A7

A6

A5

A4

A3

A2

A1

A0

A0H

SBUF

99H

SM0

SM1

SM2

REN

TB8

RB8

TI

RI

SCON

9F

9E

9D

9C

9B

9A

99

98

98H

P1

90H

97

96

95

94

93

92

91

90

TH1

8DH

TH0

8CH

TL1

8BH

TL0

8AH

TMOD

89H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

TCON

8F

8E

8D

8C

8B

8A

89

88

88H

PCON

87H

DPH

83H

DPL

82H

SP

81H

P0

87

86

85

84

83

82

81

80

80H

MBC465 - 1

Fig.12 Special Function Register (SFR) memory map.

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Philips Semiconductors	Product specification
8-bit microcontrollers	P83C524; P80C528; P83C528

9.3Addressing

The P83C528 has five modes for addressing:

∙Register

∙Direct

∙Register-Indirect

∙Immediate

∙Base-Register plus Index-Register-Indirect.

The first three methods can be used for addressing destination operands. Most instructions have a 'destination/source' field that specifies the data type, addressing methods and operands involved. For operations other than MOVs, the destination operand is also a source operand.

Access to memory addresses is as follows:

∙Register in one of the four 8-bit register banks through Register, Direct or Register-Indirect addressing.

∙512 bytes of internal RAM through Direct or Register-Indirect addressing. Bytes 0-127 of internal RAM may be addressed directly/indirectly. Bytes 128-255 of internal RAM share their address location with the SFRs and so may only be addressed indirectly as data RAM. Bytes 0-255 of AUX-RAM can only be addressed indirectly via MOVX.

∙SFR through Direct addressing at address locations 128-255.

∙External data memory through Register-Indirect addressing.

∙Program memory look-up tables through Base-Register plus Index-Register-Indirect addressing.

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Philips Semiconductors	Product specification
8-bit microcontrollers	P83C524; P80C528; P83C528

10 I/O FACILITIES

The P83C528 has four 8-bit ports. Ports 0-3 are the same as in the 80C51, with the exception of the additional function of Port 1. Port lines P1.0 and P1.1 may be used as inputs for Timer 2, P1.1 may also be used as an additional (third) external interrupt request input. Port lines P1.6 and P1.7 may be selected as the SCL and SDA lines of Serial Port SIO1 (I2C). Because the I2C-bus may be active while the device is disconnected from VDD, these pins are provided with open drain drivers. Pins P1.6 and P1.7 do not have pull-up devices when used as ports.

Ports 0, 1, 2, and 3 perform the following alternative functions:

∙Port 0: provides the multiplexed low-order address and data bus used for expanding the P83C528 with standard memories and peripherals.

∙Port 1: pins can be configured individually to provide: external interrupt request input (external interrupt 2); external inputs for Timer/counter 2; SCL and SDA for the I2C interface.

∙Port 2: provides the high-order address bus when expanding the P83C528 with external program memory and/or external data memory.

∙Port 3: pins can be configured individually to provide: external interrupt request inputs (external interrupt 0/1); external inputs for Timer/counter 0 and

Timer/counter 1; Serial Port receiver input and transmitter output control-signals to read and write external data memory.

Bits which are not used for the alternative functions may be used as normal bidirectional I/O pins. The generation or use of a Port 1 or Port 3 pin as an alternative function is carried out automatically by the P83C528 provided the associated SFR bit is HIGH. Otherwise the port pin is held at a logical LOW level.

handbook, full pagewidth	strong pull-up	+5 V
	2 oscillator
	periods	p2
	p1	p3
		I/O PIN
		PORT
Q
from port latch	n
		I1
input data
	INPUT	MLA513
read port pin	BUFFER

Fig.13 I/O buffers in the P83C528 (Ports 1, 2 and 3 except P1.6 and P1.7).

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Philips Semiconductors	Product specification
8-bit microcontrollers	P83C524; P80C528; P83C528

11 TIMERS/COUNTERS

The P83C528 contains three 16-bit timer/counters, Timer 0, Timer 1 and Timer 2, and one 8-bit timer, the Watchdog Timer T3. Timer 0, Timer 1 and Timer 2 may be programmed to carry out the following functions:

·measure time intervals and pulse durations

·count events

·generate interrupt requests.

11.1Timer 0 and Timer 1

Timers 0 and 1 each have a control bit in TMOD SFR that selects the timer or counter function of the corresponding timer. In the timer function, the register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1¤12 of the oscillator frequency.

In the counter function, the register is incremented in response to a HIGH-to-LOW transition at the corresponding external input pin, T0 or T1. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a HIGH in one cycle and a LOW in the next cycle, the counter is incremented. Thus, it takes two machine cycles (24 oscillator periods) to recognize a HIGH-to-LOW transition. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle.

Timer 0 and Timer 1 can be programmed independently to operate in one of four modes:

Mode 0 8-bit timer/counter with divide-by-32 prescaler

Mode 1 16-bit timer/counter

Mode 2 8-bit timer/counter with automatic reload

Mode 3 Timer 0: one 8-bit timer/counter and one 8-bit timer. Timer 1: stopped.

When Timer 0 is in Mode 3, Timer 1 can be programmed to operate in Modes 0, 1 or 2 but cannot set an interrupt request flag and generate an interrupt. However, the overflow from Timer 1 can be used to pulse the Serial Port transmission-rate generator. With a 16 MHz crystal, the counting frequency of these timer/counters is as follows:

·in the timer function, the timer is incremented at a frequency of 1.33 MHz (oscillator frequency divided by 12).

·in the counter function, the frequency handling range for external inputs is 0 Hz to 0.66 MHz.

Both internal and external inputs can be gated to the timer by a second external source for directly measuring pulse duration.

The timers are started and stopped under software control. Each one sets its interrupt request flag when it overflows from all logic 1's to all logic 0's (respectively, the automatic reload value), with the exception of Mode 3 as previously described.

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