Philips OM6206 User Manual

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INTEGRATED CIRCUITS

DATA SH EET

OM6206

65 × 102 pixels matrix LCD driver

Product speciﬁcation File under Integrated Circuits, IC17

2001 Nov 14

Philips Semiconductors Product speciﬁcation

65 × 102 pixels matrix LCD driver OM6206

CONTENTS

1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING

6.1 Pin functions

6.1.1 R0 to R64: row driver outputs

6.1.2 C0 to C101: column driver outputs

6.1.3 V

6.1.4 V

6.1.5 V

6.1.6 V

6.1.7 V

and V

SS1

, V

DD1

: LCD supply voltage

LCDIN LCDOUT LCDSENSE

: ground supply rails

SS2

and V

DD2

DD3

: voltage multiplier output

: voltage multiplier regulation input

: supply voltage rails

6.1.8 T1 to T5: test pins

6.1.9 SDIN: serial data line

6.1.10 SCLK: serial clock line

6.1.11 D/C: mode select

6.1.12 SCE: chip enable

6.1.13 OSC: oscillator

6.1.14 RES: reset 7 FUNCTIONAL DESCRIPTION

7.1 Oscillator

7.2 Address counter

7.3 Display data RAM (DDRAM)

7.4 Timing generator

7.5 Display address counter

7.6 LCD row and column drivers

7.7 Addressing

7.7.1 Data structure

8 INSTRUCTIONS

8.1 Initialization

8.2 Reset function

8.3 Function set

8.3.1 PD

8.3.2 V

8.3.3 H

8.4 Display control

8.4.1 D and E

8.5 Set Y-address of RAM

8.6 Set X-address of RAM

8.7 Set high-voltage generator stages

8.8 Bias system

8.9 Temperature control

8.10 Set VOP value 9 LIMITING VALUES 10 HANDLING 11 DC CHARACTERISTICS 12 AC CHARACTERISTICS 13 APPLICATION INFORMATION

13.1 Programming example for the OM6206

13.2 Application diagrams

13.3 Application for COG

13.4 Chip information 14 BONDING PAD INFORMATION 15 DEVICE PROTECTION CIRCUITS 16 TRAY INFORMATION 17 DATA SHEET STATUS 18 DEFINITIONS 19 DISCLAIMERS

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Philips Semiconductors Product speciﬁcation

65 × 102 pixels matrix LCD driver OM6206

1 FEATURES

• Single-chip LCD controller and driver

• 65 row and 102 column outputs

• Display data RAM 65 × 102 bits

• On-chip:

– Configurable 5 (4, 3 and 2) × voltage multiplier

generating V

(external V

LCD

also possible)

LCD

– Generation of intermediate LCD bias voltages – Oscillator requires no external components

(external clock also possible).

• External reset input pin RES

• Serial interface maximum 4.0 Mbits/s

• CMOS compatible inputs

• Multiplex rate of 1 : 65

• Logic supply voltage range from 2.5 to 5.5 V

to VSS)

DD1

• High-voltage generator supply voltage range from

2.5 to 4.5 V (V

DD2

and V

DD3

to VSS)

• Display supply voltage range from 4.5 to 9.0 V (V

to VSS)

LCD

• Low power consumption, suitable for battery operated systems

• Temperature compensation of V

LCD

• Temperature range from −40 to +85 °C

• Slim chip layout, suited for Chip-On-Glass (COG)

applications.

2 APPLICATIONS

• Telecom equipment.

3 GENERAL DESCRIPTION

The OM6206 is a low-power CMOS LCD controller and driver, designed to drive a graphic display of 65 rows and 102 columns. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD supply and bias voltages, resulting in a minimum of external components and low power consumption.

TheOM6206interfacesto microcontrollersvia aserial bus interface.

4 ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

OM6206U/Z − chip with bumps in tray −

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Philips Semiconductors Product speciﬁcation

65 × 102 pixels matrix LCD driver OM6206

5 BLOCK DIAGRAM

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LCDIN

LCDSENSE

LCDOUT

T1 T2 T3 T4 T5

SS1VSS2

214 to 217, 221, 222

224 to 229

237

230 to 236

218

198

223 220 219

DD1VDD2

200 to 213

174 to 179

BIAS

VOLTAGE

GENERATOR

HIGH

VOLTAGE

GENERATOR

181 to 193

DD3

C0 to C101

180

COLUMN DRIVERS

DATA LATCHES

DISPLAY DATA RAM

(DDRAM)

65 × 102

ADDRESS COUNTER

DATA

I/O BUFFER

37 to 138

OM6206

R0 to R64

2 to 15, 18 to 36, 139 to 156, 159 to 172

ROW DRIVERS

SHIFT REGISTER

RESET

OSCILLATOR

TIMING

GENERATOR

DISPLAY ADDRESS COUNTER

199

RES

OSC

195 194 196 197

SDIN SCLK

Fig.1 Block diagram.

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D/C

SCE

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Philips Semiconductors Product speciﬁcation

65 × 102 pixels matrix LCD driver OM6206

6 PINNING

SYMBOL PAD DESCRIPTION

R0 to R18 18 to 36 LCD row driver outputs R19 to R32 2 to 15 LCD row driver outputs R33 to R50 156 to 139 LCD row driver outputs R51 to R64 159 to 172 LCD row driver outputs C0 to C101 37 to 138 LCD column driver outputs V

SS1

214 to 217,

ground supply 1

221 and 222

SS2

DD1

DD2

DD3

LCDIN

LCDOUT

LCDSENSE

200 to 213 ground supply 2 174 to 179 supply voltage 1 181 to 193 supply voltage 2

180 supply voltage 3 224 to 229 LCD supply voltage (V 230 to 236 voltage multiplier output

)

LCD

237 voltage multiplier

regulation input (V

LCD

)

LCD

T1 218 test 1 input T2 198 test 2 output T3 223 test 3 input/output T4 220 test 4 input T5 219 test 5 input SCLK 194 serial clock input SDIN 195 serial data input D/

C 196 dataor commandselection

input SCE 197 chip enable (active LOW) OSC 199 oscillator signal input RES 1 external reset input (active

LOW)

6.1 Pin functions

6.1.1 R0 TO R64: ROW DRIVER OUTPUTS These pins output the row signals.

6.1.2 C0 TO C101: COLUMN DRIVER OUTPUTS These pins output the column signals.

6.1.3 V The supply rails V

SS1

AND V

SS1

: GROUND SUPPLY RAILS

SS2

and V

must be connected

SS2

together.

6.1.4 V V

and V

DD2

DD1,VDD2

DD3

AND V

: SUPPLY VOLTAGE RAILS

DD3

are the supply voltage for the internal voltagegenerator. Bothhave thesame voltageand should be connected together outside the chip. V supply voltage for the rest of the chip. V connected together with V

DD2

and V

DD1

can be

DD1

but in this case

DD3

care must be taken to respect the supply voltage range (see Chapter 11).

If the internal voltage generator is not used the pins V

DD2

and V

must be connected to pin V

DD3

DD1

connected to the supply voltage.

)

6.1.5 V

: LCD SUPPLY VOLTAGE

LCDIN

Positive supply voltage for the liquid crystal display. An external LCD supply voltage can be supplied using pin V

. In this case, V

LCDIN

has to be left open and

LCDOUT

the internal voltage generator has to be programmed to zero. If the OM6206 is in Power-down mode, the external LCD supply voltage has to be switched off.

6.1.6 V

: VOLTAGE MULTIPLIER OUTPUT

LCDOUT

Positive supply voltage for the liquid crystal display. If the internal voltage generator is used, the two supply rails V

LCDIN

and V

must be connected together. If an

LCDOUT

external supply is used this pin must be left open.

6.1.7 V

LCDSENSE

INPUT

is the input of the internal voltage multiplier

: VOLTAGE MULTIPLIER REGULATION

regulation. If the internal voltage generator is used then V

must be connected to V voltage is used then V

LCDSENSE

. If an external supply

LCDOUT

can be left open or

connected to ground.

6.1.8 T1 TO T5: TEST PINS T1, T3, T4 and T5 must be connected to VSS, T2 must be

left open. Not accessible to user.

is used as

LCDSENSE

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Philips Semiconductors Product speciﬁcation

65 × 102 pixels matrix LCD driver OM6206

6.1.9 SDIN: SERIAL DATA LINE Input for the data line.

6.1.10 SCLK: SERIAL CLOCK LINE Input for the clock signal: up to 4.0 Mbits/s.

6.1.11 D/C: MODE SELECT Input to select either command or address data input.

6.1.12 SCE: CHIP ENABLE The enable pin allows data to be clocked in. Signal is

active LOW.

6.1.13 OSC: OSCILLATOR When the on-chip oscillator is used this input must be

connected to VDD. An external clock signal, if used, is connected to this input. If theoscillator and external clock are both inhibited by connecting pin OSC to VSS, the display is not clocked and may be left in a DC state. To avoid this the chip should always be put into Power-down mode before stopping the clock.

6.1.14 RES: RESET This signal will reset the device and must be applied to

properly initialize the chip. Signal is active LOW.

7 FUNCTIONAL DESCRIPTION

7.1 Oscillator

The on-chip oscillator provides the clock signal for the display system.No external componentsare required and the OSC input must be connected to VDD. An external clock signal, if used, is connected to this input.

7.2 Address counter

The address counter assigns addresses to the display data RAM for writing. The X-address X6to X0 and the Y-address Y3to Y0 are set separately. After a write operation, the address counter is automatically incremented by 1 according to bit V (see Section 7.7).

7.3 Display Data RAM (DDRAM)

The OM6206 contains a 65 × 102 bits static RAM which stores the display data. The RAM is divided into eight banks of 102 bytes (8 × 8 × 102 bits) and one bank of 102 bits (1 × 102 bits). During RAM access, data is transferred to the RAM via the serial interface. There is a direct correspondence between X-address and column output number.

7.4 Timing generator

The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not affected by operations on the data bus.

7.5 Display address counter

The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the column outputs.

The display status (all dots on/off and normal/inverse video) is set by bits E and D in the command ‘Display control’ (see Table 2).

7.6 LCD row and column drivers

The OM6206 contains 65 rows and 102 column drivers, which connect the appropriate LCD bias voltages in sequence to the displayin accordance with the data tobe displayed. Figure 2 shows typical waveforms. Unused outputs should be left unconnected.

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Philips Semiconductors Product speciﬁcation

65 × 102 pixels matrix LCD driver OM6206

ROW0 R0(t)

ROW1 R1(t)

COL0 C0(t)

COL1 C1(t)

LCD

V3 − V

V V V

LCD 2 3

4 5 SS

LCD 2 3

4 5 SS

LCD 2 3

4 5 SS

LCD 2 3

4 5 SS

frame n frame n + 1

state1

state2

(t) (t)

− V

LCD

state1

state2

(t) = C1(t) to R0(t).

state1

(t) = C1(t) to R1(t).

state2

(t)

0 V

V3 − V

LCD

V3 − V

LCD

0 V

V3 − V

− V

012345678... ... 64 012345678... ... 64

Fig.2 Typical LCD driver waveforms.

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V4 − V 0 V

VSS − V

V4 − V

− V

LCD

V4 − V 0 V

VSS − V

V4 − V

− V

LCD

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LCD

Philips Semiconductors Product speciﬁcation

65 × 102 pixels matrix LCD driver OM6206

DDRAM

bank 0

top of LCD

bank 1

bank 2

bank 3

bank 7

bank 8

LCD

Fig.3 DDRAM to display mapping.

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Philips Semiconductors Product speciﬁcation

65 × 102 pixels matrix LCD driver OM6206

7.7 Addressing

Data is downloaded in bytes into the RAM matrix of OM6206 as indicated in Figs.3, 4, 5 and 6.

The display RAM has a matrix of 65 × 102 bits. The columns are addressed by the address pointer. The address ranges are: X from 0 to 101 (1100101) and Y from 0 to 8(1000). Addressesoutside theseranges are not allowed.

In vertical addressing mode (bit V = 1) the Y-address increments after each byte (see Fig.6).

7.7.1 DATA STRUCTURE

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LSB

MSB

After the last Y-address (Y = 8) Y wraps around to 0 and X increments to addressthe next column.

In horizontal addressing mode (bit V = 0) the X-address increments after each byte (see Fig.5). After the last X-address (X = 101) X wraps around to 0 and Y increments to address the next row.

After the very last address (X = 101, Y = 8) the address pointers wrap around to address X = 0, Y = 0.

Y-address

LSB

MSB

0 101X-address

Fig.4 RAM format, addressing.

MGT862

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Philips Semiconductors Product speciﬁcation

65 × 102 pixels matrix LCD driver OM6206

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09 110 2 3 4 5 6 7 8 917

0 101X-address

Y-address

MGT 863

Fig.5 Sequence of writing data bytes into RAM with vertical addressing (V = 1).

012 102 103 104 204 205 206 306 307 308 408 409 410 510 511 512 612 613 614 714 715 716 816 817 818 917

0 101X-address

Y-address

MGT864

Fig.6 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).

8 INSTRUCTIONS

The instruction format is divided into two modes:

• If D/C (mode select) is set LOW, the current byte is interpreted as command byte (see Table 1).

• If D/C is set HIGH, the following bytes are stored in the display data RAM. After every data byte the address counter is incremented automatically.

Thelevel ofthe D/C signalis readduringthe lastbit ofdata byte.

2001 Nov 14 10

Every instruction canbe sent in anyorder to the OM6206. The MSBof a byte istransmitted first (seeFig.7). Figure 8 shows one possible command stream, used to set up the LCD driver.

The serialinterface isinitialized whenSCE isHIGH. In this state SCLK clock pulses have no effect and no power is consumedby the serialinterface. Anegative edgeon SCE enablesthe serialinterfaceand indicatesthe startofa data transmission.

Philips Semiconductors Product speciﬁcation

65 × 102 pixels matrix LCD driver OM6206

handbook, halfpage

MSB (DB7) LSB (DB0)

Fig.7 General format of data stream.

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bias systemfunction set (H = 1)

Fig.8 Serial data stream, example.

Figures 9 and 10 show the serial bus protocol:

• When SCE is HIGH, SCLK clock signals are ignored. During the HIGH time of SCE, the serial interface is initialized (see Fig.11)

• SDIN is sampled at the positive edge of SCLK

• D/C indicates, whether the byte is a command

(D/C = LOW) or RAM data(D/C = HIGH); it is read with the eighth SCLK pulse

datadata

MGT865

set V

temperature control

X-addressY-addressdisplay controlfunction set (H = 0)

MGT866

• If SCE stays LOW after the last bit of a command/data byte, theserial interface expects bit 7of the next byte at the next positive edge of SCLK (see Fig.11)

• A reset pulse with RES interrupts the transmission. No data are written into the RAM. The registers are cleared. If SCE is LOW after the positive edge of RES, the serial interface is ready to receive bit 7 of a command/data byte (see Fig.11).

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SCE

D/C

SCLK

SDIN

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Fig.9 Serial bus protocol for transmission of one byte.

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