Philips OM5730 Datasheet

INTEGRATED CIRCUITS

DATA SH EET

OM5730

STB5860 (Set-Top Box) STB
concept

Preliminary specification
File under Integrated Circuits, IC02

1999 Aug 25

Philips Semiconductors Preliminary specification

STB5860 (Set-Top Box) STB concept OM5730

CONTENTS

1 FEATURES

1.1 SAA7219 features

1.1.1 General SAA7219 features

1.1.2 MPEG2 systems features

1.1.3 External interface features

1.2 SAA7215 family features

1.2.1 General SAA7215 family features

1.2.2 CPU related features

1.2.3 MPEG2 system features

1.2.4 MPEG2 video features

1.2.5 MPEG2 audio features

1.2.6 Graphics features
2 GENERAL DESCRIPTION

2.1 Introduction

2.2 Reference design goal

2.3 Benefits

2.3.1 Key system benefits

2.3.2 Key IC benefits
3 BLOCK DIAGRAMS
4 HARDWARE

4.1 IC list

4.2 Main board

4.2.1 SAA7219

4.2.2 SAA7215

4.3 Front-end

4.4 Front panel

4.4.1 LNB interface

4.4.2 IR

4.4.3 Keys

4.4.4 SCART control

4.5 Memory

4.5.1 Non-Volatile Memory (NVM)

4.5.2 DRAM

4.5.3 Boot ROM

4.5.4 Flash

4.5.5 Video and graphics RAM

4.5.6 Memory options

4.6 Connectors

5 SOFTWARE DESCRIPTION

5.1 Software overview

5.1.1 General software resources

5.1.2 Application layer

5.1.3 System control layer

5.1.4 Platform layer

5.1.5 I/O device drivers

5.2 General software resources

5.3 System control layer

5.4 Platform layer

5.5 Application layer

5.5.1 Top level menu

5.5.2 Installation menu

5.5.3 Tuning menu

5.5.4 Feature demonstration menu
6 DEVELOPMENT ENVIRONMENT

6.1 Summary of the STB5860 kit

6.1.1 The hardware

6.1.2 The software

6.1.3 Documentation

6.1.4 Test reports

6.2 How to get started

6.3 Hardware interface with the STB5860

6.4 Software interface with the STB5860

6.5 Running ‘hello world’
7 CONTENTS LIST FOR STB5860
8 DEFINITIONS
9 LIFE SUPPORT APPLICATIONS
10 PURCHASE OF PHILIPS I2C COMPONENTS

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Philips Semiconductors Preliminary specification

STB5860 (Set-Top Box) STB concept OM5730

1 FEATURES

1.1 SAA7219 features

1.1.1 GENERAL SAA7219 FEATURES

• Internal PR3930 32-bit RISC processor running at
81 MHz

• Comprehensive driver software and development tool
support

• A JTAG interface for board test support

• 8-kbyte 8-way set associative instruction cache

• 4-kbyte 4-way set associative instruction cache.

1.1.2 MPEG2 SYSTEMS FEATURES

• Parsing of Transport Stream (TS), Philips
Semiconductors hardware and proprietary software
data streams; maximum input rate is 108 Mbits/s

• A real time descrambler consisting of 3 modules:
– A control word bank containing 14 pairs (odd and

even) of control words and a default control word

– The Digital Video Broadcasting (DVB) descrambler

core implementing the stream decipher and block
decipher algorithms

– The MULTI2 descrambler algorithm implementing

the CBC and OFB mode descrambling functions.

• Hardware section filtering based on 32 different Packet
Identifiers (PIDs) with a flexible number of filter
conditions (8 or 4-byte condition plus8 or 4-byte mask)
per PID and a total filter capacity of 40 (8-byte condition
checks) or up to 80 (4-byte condition checks) filter
conditions

• 4 Transport Stream/Packetized Elementary Stream
(PES) filters for retrieval of data at TS or PES level for
applications such as subtitling, TXT or retrieval of
private data

• Flexible Direct Memory Access (DMA) based storage of
the 32 section substreams and 4 TS/PES data
substreams in the external memory

• System time base management with a double counter
mechanism for clock control and discontinuity handling
2 Presentation Time Stamp (PTS)/Decoding Time
Stamp (DTS) timers

• AGeneral Purpose/High speed (GP/HS) filter which can
serve as alternative input from e.g. IEEE 1394 devices.
It can also output either scrambled or descrambled
TS to IEEE 1394 devices.

1.1.3 EXTERNAL INTERFACE FEATURES

• A 32-bit microcontroller extension bus supporting
DRAM, SDRAM flash, (E)PROM and external memory
mapped I/O devices. It also supports a synchronous
interface to communicate with the integrated MPEG
Audio Video Graphics (AVG) decoder SAA7215 family
at 40.5 Mbytes/s.

• An IEEE 1284 interface supporting master and slave
modes; usable as a general purpose port

• 2 UART (RS232) data ports with DMA capabilities
(187.5 kbits/s) including hardware flow control RXD,
TXD, RTS and CTS for modem support

• Two dedicated smart card reader interfaces (ISO 7816
compatible) with DMA capabilities

• Two I2C-bus master/slave transceivers supporting the
standard (100 kbits/s) and fast (400 kbits/s) I2C-bus
modes

• 32 general purpose, bidirectional I/O interface pins, 8 of
which may also be used as interrupt inputs

• 2 Pulse Width Modulated (PWM) outputs with 8-bit
resolution.

1.2 SAA7215 family features

1.2.1 GENERAL SAA7215 FAMILY FEATURES

• Singleordoubleexternal synchronous DRAMorganized
as 1M × 16or2 × 1M × 16 interfacing at 81 MHz. Due to
efficient memory use in MPEG decoding, more than
1 Mbit is available for graphics in the single SDRAM
configuration whereas 17 Mbits are available in the
double SDRAM configuration targeted to BSkyB 3.00
and Canal+ 4.0 specifications.

• Dedicated input for compressed audio and video in PES
or ES in byte wide or bit serial format; accompanying
strobe signals distinguish between audio and video data

• Optimum compatibility with SAA7219 TMIPS controller

• Flexible memory allocation under control of the external

Central Processing Unit (CPU) enables optimized
partitioning of memory for different tasks

• Boundary scan testing implemented.

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Philips Semiconductors Preliminary specification

STB5860 (Set-Top Box) STB concept OM5730

1.2.2 CPU RELATED FEATURES

• External SDRAM self test

• Asynchronous interface possible with external

microcontroller

• Support of fast DMA transfer

• High speed/low latency interface with second graphics

SDRAM

• Byte access to the full SDRAM in the upper 16-Mbit
address range

• Fast 16-bit data plus 22-bit address synchronous
interface with external controller at up to 40.5 MHz

• Support of Motorola ColdFire and 68xxx interfaces as
well as LSI L64108 interface.

1.2.3 MPEG2 SYSTEM FEATURES

• Support for seamless time base change (edition)

• Processing of errors flagged by channel decoding

section.

1.2.4 MPEG2 VIDEO FEATURES

• Decoding of MPEG2 video up to main level and main
profile

• Output picture format: CCIR-601 4 : 2 : 2 interlaced
pictures; picture format 720 to 576 at 50 Hz or
720 to 480 at 60 Hz

• Support of constant and variable bit rates up to
15 Mbits/s for the elementary stream

• Digital video input/output interface on 8-bit,
27 MHz (CbYCrY multiplexed bus), at a CCIR-656
format

• Analog video output interface on both the RGB and
Y/C/CVBS formats (internal digital encoder)

• Horizontal and vertical pan and scan allows the
extraction of a window from the coded picture

• Flexible horizontal scaling from 0.5 up to 4 allows easy
aspect ratio conversion including support for 2.21 : 1
aspect ratio movies; in case of shrinking an anti-aliasing
pre-filter is applied

• Vertical scaling with fixed factors 0.5 and 0.75;
factor 0.75 is used for letter-box presentation, 1 or 2;
factor 0.5 realizes picture shrink

• Factor 2 can be used for up-conversion of pictures with
288 (240) lines or less

• Horizontalandverticalscalingcanbecombinedtoscale
pictures to1⁄4 their original size, thus freeing up screen
space for graphic applications like Electronic Program
Guides (EPGs)

• Non full screen MPEG pictures can be displayed in a
box of which position and background colour are
adjustable by the external microcontroller; structured
background is available as part of the graphic features

• Nominal video input buffer size for MP at ML 27-Mbit

• Decoding and presentation can be independently

handled under CPU control

• Various trick modes under control of external
microcontroller

• Freeze field/frame on I- or P-frames; restart on I-picture

• Freeze field on B-frames; restart at any moment

• Scanning and decoding of I- or I- and P-frames in a

IBP sequence

• Single-step mode

• Repeat/skip field for time base correction

• Repeat/skip frame for display parity integrity.

1.2.5 MPEG2 AUDIO FEATURES

• Decoding of 2 channel, layer I and II MPEG audio;
support for mono, stereo, intensity stereo and dual
channel mode

• Constant and variable bit rates up to 448 kbits/s

• Supported audio sampling frequencies:

48, 44.1, 32, 24, 22.05 and 16 kHz

• Selectable output channel in dual channel mode

• Dynamic range control at output

• Independentchannelvolumecontrol and programmable

inter-channel crosstalk through a baseband audio
processing unit

• Muting possibility via (external) controller; automatic
muting in case of errors

• Generation of ‘beeps’ with programmable tone height,
duration and amplitude

• Support for up to 8 channels linear Pulse Code
Modulated (PCM) elementary audio streams with
8, 16, 20 and 24 bits/sample and bit rates up to

6.144 Mbits/s

• 96 kHz Linear Pulse Code Modulated (LPCM) samples
will be mapped to a 48 kHz multi-channel format

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Philips Semiconductors Preliminary specification

STB5860 (Set-Top Box) STB concept OM5730

• Volume control for linear PCM samples in three steps:

−6, −12 and −18 dB

• Burst-formatting of AC-3 elementary streams and

MPEG-2 multi-channel streams in ES or PES format for
interconnection with an external multi-channel decoder
via the digital audio output or the IEC 958 output

• Serial multi-channel digital audio output with
16, 18, 20 or 24 bits/sample, compatible either to I2Sor
Japanese formats; output can be set to high impedance
mode via the external controller

• Serial Sony/Philips Digital Interface (SPDIF) (IEC 958)
audio output; output can be set to high-impedance
mode.

1.2.6 GRAPHICS FEATURES

• Graphics is presented in boxes independent of video
format

• Boxes can be up to full screen allowing double buffer
display mechanism

• Two independent graphics planes are available for
background and/or graphics overlay

• Two independent data paths with RGB 4 :4:4 and
YCbCr 4:2:2 formats available with independent
mixing

• RGB path transparent to YCbCr format

• Screen arrangement of boxes is determined by display

list mechanism which allows for multiple boxes,
background loading, fast switching, scrolling,
overlapping and fading of regions

• Real-time anti-flickering performed in hardware;
programmable hardware available for off-line
anti-flickering

• Hard-edged or soft-edged wiping of regions available

• Support of 2, 4, 8 and 16 bits/pixel in fixed bit maps

format or coded in accordance to the DVB variable/run
length standard for region based graphics

• Chrominance down-sampling filter switched per region

• Display colours are obtained via Colour Look-Up

Tables (CLUT)ordirectlyfrombitmap.CLUToutputcan
be YCbCrT at 8-bit for each signal component thus
enabling 16M different colours and 6-bit for T which
gives 64 mixing levels with video. CLUT output can also
be RGBT with same resolutions. Non-linear processing
available by means of LUTs.

• Conversion matrices available to allow any format on
any different data path (RGB or YCbCr)

• Graphics boxes may overlap vertically even inside one
graphics layer due to the use of flexible chained
descriptors

• Internal support for fast 3-D block moves in external
SDRAM through Data Manipulation Unit (DMU)

• DMU allows format conversion and bit manipulation
from a chained list of instructions

• Graphics mechanism can be used for signal generation
in the vertical blanking interval; useful for teletext, wide
screen signalling, closed caption, etc.

• Support for a single down loadable cursor of 1 K pixel
with programmable shape

• Supported shapes are 8 × 128, 16 × 64, 32 × 32,
64 × 16 and 128 × 8 pixels

• Cursor colours obtained via two 16 entry CLUTs with
YCbCrT at 6, 4, 4 respectively

• 2 bits and RGBT at 4, 4, 4 respectively 4 bits (or 4, 5, 3,
respectively 4 bits); mixing of cursor with video and
graphics in 4 levels

• Cursor can be moved freely across the screen without
overlapping restrictions.

2 GENERAL DESCRIPTION

2.1 Introduction

ThePhilipsSemiconductorsSet-Top Box (STB) conceptis
a Digital Media Broadcast (DMB) platform designed to
help developers bring the right product to market at the
right time, with a minimum of risk. A complete hardware
and software solution for fully-featured digital cable,
satellite and terrestrial system; it is based around a
powerful, programmable embedded microprocessor core,
allowing manufacturers to develop and rapidly evaluate
system designs and test application software.

This programmability is the key to maintaining flexibility
and reducing risk. Application software can be easily
modified to meet changing requirements, so highly
featured and differentiated STB designs can be brought
quickly to market. It also allows flexible handling of
graphics, so manufacturers can implement menus,
Electronic Program Guides and the sophisticated
graphics-based features expected by today’s users.

Sophisticated hardware is supported by a full suite of
software,developedinpartnershipwithcustomerstomeet
real-world needs and provide the reliability required for
consumer electronics products.

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Philips Semiconductors Preliminary specification

STB5860 (Set-Top Box) STB concept OM5730

2.2 Reference design goal

The Philips STB concept STB5860 is a reference design
of a complete hardware and software solution intended for
the digital satellite receiver set-top box market. This
reference design addresses the potential customer base
who is targeting the new world of digital media
broadcasting. The reference platform for a set-top box
combines the key ICs, the SAA7219 transport MPEG
source decoder and the SAA7215 family AVG
decoder/video encoder and the software to run a set-top
box.

As in many cases a platform is a stepping stone from
which evolution and specification enhancements can be
launched. The first reference design of the platform
contains the necessary functions which demonstrate the
performance and capabilities of the system.
Enhancements in the ICs as well as for SW modules will
be released during the lifetime of the platform.
The convention which has been used is that backwards
compatibility is guaranteed within the platform (STB5000
range).

The main objectives are:

• Firstly providing this complete system, greatly reduces
the required investments needed in scarce design
resources and helps customers focus on building a
position and responding quickly to the market demand

• Secondly, an advantage of the reference design
approach is that the system consisting of complex
functions realized in silicon and software can be
validated in tangible results

• Thirdly, to create a stable platform from which
customized solutions can be derived faster.

It is expected that in the coming years the market will grow
in all segments, satellite, cable and terrestrial; and that the
captive broadcasters gradually open up their system,
focusing more on the services rather then the contents of
the box. Their service role at the beginning is to create the
market by having box content, then it will change towards
the real core service activities bringing content and new
services to the home.

This changing behaviour of the service providers calls for
thesemiconductorproviderstooffercompetitivesolutions,
enabling the future dreams of the service providers. This
implies that in order to plan the evolution of the set-top box
functionality, one must be positioned and in control of the
whole system.

2.3 Benefits

2.3.1 KEY SYSTEM BENEFITS

• STB5860 offers a good compromise between flexibility,
performance and integration of functions which leads to
a very attractive price/performance offer.

• The SAA7219 performs the descrambling,
demultiplexing and control of the STB while the
SAA7215 family performs the media processing
functions such as MPEG2 audio video and graphics
processing.The communication between thetwo ICsas
well as the memory partitioning and management have
been designed so that a true unified memory concept
can be implemented with no performance degradation.

• Within the STB family of products, HW and SW
footprints will be maintained to ensure the maximum
possible reuse of resources.

• Philips offering the most comprehensive portfolio of ICs
combined with our well known technological capabilities
brings the best on a complete system level. This in
combination with our local technical support centres
gives the customer a fast and secure inroad to the new
field of emerging technology.

2.3.2 KEY IC BENEFITS

• SAA7219 incorporates a low cost high performance
32 bits MIPS processor with 4 kbytes instruction cache
and 1-kbyte data cache. In addition a 4-kbyte
second-level cache, designed for SW optimization but
can also be used for ‘last minute’ CPU intensive
software patches is offered to software developers,
boosting application performance.

• A flexible hardware/software partitioning and
optimization for DVB TS demultiplexing has been
designed targeted to Canal+ specification. This
partitioning makes parsing of incoming stream in
hardware, in order to off-load the processor and makes
most of the processing from system memory by the
MIPS processor, which leaves to software developers
the freedom to allocate the right priority at the
application level for MPEG system data handling.

• All required DVB/MPEG2 system services are covered
by the SAA7219, such as full DVB descrambling,
section filtering with 32 PIDs handled in hardware and
more if required in software, TS/PES filter for maximum
flexibility in the service handling and edition (time base
discontinuity)

1999 Aug 25 6