Philips OM5232-FBP, OM5232-FBB Datasheet

Philips Semiconductors Product specification

OM5232CMOS single-chip 8-bit microcontroller

December 1994

DESCRIPTION

The OM5232 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The OM5232 has the same instruction set as the 80C51.

See also: – OM5202 — ROMless version

– OM5234 — 16K bytes mask programmable ROM – OM5238 — 32K bytes mask programmable ROM

This device provides architectural enhancements that make it applicable in a variety of applications for general control systems. The OM5232 contains a non-volatile 8k × 8 read-only program memory, a volatile 256 × 8 read/write data memory, four 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51), a multi-source, two-priority-level, nested interrupt structure, UART and on-chip oscillator and timing circuits. For systems that require extra capability, the OM5232 can be expanded using standard TTL compatible memories and logic.

The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte and 17 three-byte. With a 16MHz crystal, 58% of the instructions are executed in 0.75µs and 40% in 1.5µs. Multiply and divide instructions require 3µs.

FEATURES

•80C51 central processing unit

•8k × 8 ROM, expandable externally to 64k bytes

•256 × 8 RAM, expandable externally to 64k bytes

•Two standard 16-bit timer/counters

•Four 8-bit I/O ports

•Two open drain I/O’s (P1.6, P1.7)

•Full-duplex UART facilities

•Power control modes

– Idle mode – Power-down mode

•ROM code protection

•Extended frequency range: 1.2 to 16 MHz

•Operating ambient temperature range: 0 to +70°C

PIN CONFIGURATIONS

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

P1.0 P1.1

P1.2 P1.3 P1.4 P1.5 P1.6

RST RxD/P3.0 TxD/P3.1

INT0

/P3.2

INT1

/P3.3 T0/P3.4 T1/P3.5

P1.7

/P3.7

XTAL2 XTAL1

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

DIP

SEE PAGE 2 FOR QFP PIN FUNCTIONS.

QFP

12 22

/P3.6

(SOT307–2)

PART NUMBER SELECTION

PHILIPS PART

ORDER NUMBER

PART MARKING

PACKAGE NUMBER

TEMPERATURE RANGE °C,

PACKAGE

FREQUENCY

MHz

OM5232/FBP/xxx

SOT129 0 to +70, Plastic Dual In–line Package, 40 leads 1.2 to 16

OM5232/FBB/xxx

SOT307–2 0 to +70, Plastic Quad Flat Pack, 44 leads 1.2 to 16

NOTE:

1. xxx denotes the ROM code number.

EQUIVALENT TYPES

Details are as specified by the data sheet for the equivalent type:

OM5202 = P80C652 without I

C function.

OM5232 = P83C652 without I

C function.

OM5234 = P83C654 without I

C function.

OM5238 = P83C528 without I

C function.

Philips Semiconductors Product specification

OM5232CMOS single-chip 8-bit microcontroller

December 1994

QFP PIN FUNCTIONS

QFP

44 34

12 22

(SOT307–2)

Pin Function Pin Function Pin Function

1 P1.5 16 V

SS1

31 P0.6/AD6 2 P1.6 17 NC 32 P0.5/AD5 3 P1.7 18 P2.0/A8 33 P0.4/AD4 4 RST 19 P2.1/A9 34 P0.3/AD3 5 P3.0/RxD 20 P2.2/A10 35 P0.2/AD2 6 V

SS4

21 P2.3/A11 36 P0.1/AD1 7 P3.1/TxD 22 P2.4/A12 37 P0.0/AD0 8 P3.2/INT0 23 P2.5/A13 38 V

9 P3.3/INT1 24 P2.6/A14 39 V

SS3

10 P3.4/T0 25 P2.7/A15 40 P1.0 11 P3.5/T1 26 PSEN 41 P1.1 12 P3.6/WR 27 ALE 42 P1.2 13 P3.7/RD 28 V

SS2

43 P1.3

14 XTAL2 29 EA/V

44 P1.4

15 XTAL1 30 P0.7/AD7

NOTE:

1. Due to EMC improvements, all V

pins (6, 16, 28, 39) must be

connected to VSS.

LOGIC SYMBOL

PORT 0PORT 1PORT 2

PORT 3

ADDRESS AND

DATA BUS

ADDRESS BUS

VSSV

ALTERNATE

FUNCTIONS

RST XTAL1 XTAL2

ALE

PSEN

RxD

TxD INT0 INT1

T0 T1

64K BYTE BUS

EXPANSION

CONTRTOL

PROG SERIAL PORT FULL DUPLEX UART

SYNCHRONOUS SHIFT

PROGRAMMABLE I/O

CPU

OSCILLATOR

AND

TIMING

PROGRAM

MEMORY

DATA

MEMORY

(256 x 8 RAM)

TWO 16-BIT

TIMER/EVENT

COUNTERS

T0 T1

COUNTERS

XTAL2 XTAL1

FREQUENCY REFERENCE

INTERNAL

INTERRUPTS

EXTERNAL

INTERRUPTS

CONTROL

PARALLEL PORTS,

ADDRESS/DATA BUS

AND I/O PINS

SERIAL IN SERIAL OUT

SHARED WITH

PORT 3

(8K x 8 ROM)

INT0

INT1

BLOCK DIAGRAM

Philips Semiconductors Product specification

OM5232CMOS single-chip 8-bit microcontroller

December 1994

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC

DIP QFP TYPE NAME AND FUNCTION

20 6, 16,

28, 39

I Ground: 0V reference. With the QFP package all VSS pins (V

SS1

to V

SS4

) must be connected.

40 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation.

P0.0–0.7 39–32 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them

float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s.

P1.0–P1.5 1–6 40–44,1I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which

are open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I

). Alternate functions

include: P1.6 7 2 I/O open drain output P1.7 8 3 I/O open drain output

P2.0–P2.7 21–28 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port

2 pins that are externally being pulled low will source current because of the internal pull-ups.

(See DC Electrical Characteristics: I

). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register.

P3.0–P3.7 10–17 5,

7–13

I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: I

). Port 3 also serves the special features of the 80C51 family, as

listed below:

10 5 I RxD (P3.0): Serial input port 11 7 O TxD (P3.1): Serial output port 12 8 I INT0 (P3.2): External interrupt 13 9 I INT1 (P3.3): External interrupt 14 10 I T0 (P3.4): Timer 0 external input 15 11 I T1 (P3.5): Timer 1 external input 16 12 O WR (P3.6): External data memory write strobe 17 13 O RD (P3.7): External data memory read strobe

RST 9 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.

An internal diffused resistor to V

permits a power-on reset using only an external capacitor to

ALE 30 27 I/O Address Latch Enable: Output pulse for latching the low byte of the address during an access

to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency. Note that one ALE pulse is skipped during each access to external data memory.

PSEN 29 26 O Program Store Enable: Read strobe to external program memory via Port 0 and Port 2. It is

activated twice each machine cycle during fetches from the external program memory. When executing out of external program memory two activations of PSEN

are skipped during each

access to external data memory. PSEN

is not activated (remains HIGH) during no fetches from

external program memory. PSEN

can sink/source 8 LSTTL inputs and can drive CMOS inputs

without external pull–ups.

EA 31 29 I External Access: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out of the

internal program memory ROM provided the Program Counter is less than 16384. If during a RESET, EA

is held a TTL LOW level, the CPU executes out of external program memory. EA is

not allowed to float.

XTAL1 19 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator

circuits.

XTAL2 18 14 O Crystal 2: Output from the inverting oscillator amplifier.

NOTE:

To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VDD + 0.5V or VSS – 0.5V, respectively.

Philips Semiconductors Product specification

OM5232CMOS single-chip 8-bit microcontroller

December 1994

Table 1. OM5232 Special Function Registers

SYMBOL DESCRIPTION

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB

RESET VALUE

ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H B* B Register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H DPTR:

DPH DPL

Data Pointer (2 bytes) Data Pointer High Data Pointer Low

83H 82H

00H 00H

AF AE AD AC AB AA A9 A8

IE*# Interrupt Enable A8H EA ES1 ES0 ET1 EX1 ET0 EX0 0x000000B

BF BE BD BC BB BA B9 B8

IP*# Interrupt Priority B8H – PS1 PS0 PT1 PX1 PT0 PX0 xx000000B

87 86 85 84 83 82 81 80

P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FFH

97 96 95 94 93 92 91 90

P1*# Port 1 90H SDA SCL FFH

A7 A6 A5 A4 A3 A2 A1 A0

P2* Port 2 A0H A15 A14 A13 A12 A11 A10 A9 A8 FFH

B7 B6 B5 B4 B3 B2 B1 B0 P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TXD RXD FFH PCON Power Control 87H SMOD – – – GF1 GF0 PD IDL 0xxx0000B

9F 9E 9D 9C 9B 9A 99 98 S0CON*# Serial 0 Port Control 98H SM0 SM1 SM2 REN TB8 RB8 TI RI 00H S0BUF# Serial 0 Data Buffer 99H xxxxxxxxB

D7 D6 D5 D4 D3 D2 D1 D0 PSW* Program Status Word D0H CY AC F0 RS1 RS0 OV F1 P 00H

reserved (Note 1) DAH 00H

SP Stack Pointer 81H 07H

reserved (Note 1) DBH 00H

reserved (Note 1) D9H F8H

reserved (Note 1) D8H 00000000B

8F 8E 8D 8C 8B 8A 89 88 TCON* Timer Control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H TH1 Timer High 1 8DH 00H TH0 Timer High 0 8CH 00H TL1 Timer Low 1 8BH 00H TL0 Timer Low 0 8AH 00H TMOD Timer Mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H

* SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs.

NOTE

1. Reserved for I

C; not supported in OM5232

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