Philips Semiconductors |
Product specification |
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CMOS single-chip 8-bit microcontroller |
OM5232 |
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DESCRIPTION |
PIN CONFIGURATIONS |
The OM5232 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The OM5232 has the same instruction set as the 80C51.
See also:
±OM5202 Ð ROMless version
±OM5234 Ð 16K bytes mask programmable ROM
±OM5238 Ð 32K bytes mask programmable ROM
This device provides architectural enhancements that make it applicable in a variety of applications for general control systems. The OM5232 contains a non-volatile 8k × 8 read-only program memory, a volatile 256 × 8 read/write data memory, four 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51), a multi-source, two-priority-level, nested interrupt structure, UART and on-chip oscillator and timing circuits. For systems that require extra capability, the OM5232 can be expanded using standard TTL compatible memories and logic.
The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte and 17 three-byte. With a 16MHz crystal, 58% of the instructions are executed in 0.75ms and 40% in 1.5ms. Multiply and divide instructions require 3ms.
FEATURES
•80C51 central processing unit
•8k × 8 ROM, expandable externally to 64k bytes
•256 × 8 RAM, expandable externally to 64k bytes
•Two standard 16-bit timer/counters
•Four 8-bit I/O ports
•Two open drain I/O's (P1.6, P1.7)
•Full-duplex UART facilities
•Power control modes
±Idle mode
±Power-down mode
•ROM code protection
•Extended frequency range: 1.2 to 16 MHz
•Operating ambient temperature range: 0 to +70°C
PART NUMBER SELECTION
P1.0 |
1 |
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40 |
VDD |
P1.1 |
2 |
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39 |
P0.0/AD0 |
P1.2 |
3 |
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38 |
P0.1/AD1 |
P1.3 |
4 |
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37 |
P0.2/AD2 |
P1.4 |
5 |
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36 |
P0.3/AD3 |
P1.5 |
6 |
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35 |
P0.4/AD4 |
P1.6 |
7 |
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34 |
P0.5/AD5 |
P1.7 |
8 |
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33 |
P0.6/AD6 |
RST |
9 |
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32 |
P0.7/AD7 |
RxD/P3.0 10 |
DIP |
31 |
EA |
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TxD/P3.1 11 |
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30 |
ALE |
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INT0/P3.2 12 |
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29 |
PSEN |
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INT1/P3.3 13 |
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28 |
P2.7/A15 |
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T0/P3.4 |
14 |
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27 |
P2.6/A14 |
T1/P3.5 |
15 |
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26 |
P2.5/A13 |
WR/P3.6 |
16 |
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25 |
P2.4/A12 |
RD/P3.7 17 |
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24 |
P2.3/A11 |
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XTAL2 |
18 |
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23 |
P2.2/A10 |
XTAL1 |
19 |
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22 |
P2.1/A9 |
VSS 20 |
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21 |
P2.0/A8 |
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44 |
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34 |
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1 |
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33 |
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QFP |
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(SOT307±2) |
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11 |
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23 |
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12 |
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22 |
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SEE PAGE 2 FOR QFP PIN FUNCTIONS.
PHILIPS PART |
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TEMPERATURE RANGE °C, |
FREQUENCY |
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ORDER NUMBER |
PACKAGE NUMBER |
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PACKAGE |
MHz |
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PART MARKING |
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OM5232/FBP/xxx 1) |
SOT129 |
0 to +70, Plastic Dual In±line Package, 40 leads |
1.2 to 16 |
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OM5232/FBB/xxx 1) |
SOT307±2 |
0 to +70, Plastic Quad Flat Pack, 44 leads |
1.2 to 16 |
NOTE:
1. xxx denotes the ROM code number.
EQUIVALENT TYPES
Details are as specified by the data sheet for the equivalent type:
OM5202 = P80C652 without I2C function.
OM5232 = P83C652 without I2C function.
OM5234 = P83C654 without I2C function.
OM5238 = P83C528 without I2C function.
December 1994 |
1 |
Philips Semiconductors |
Product specification |
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CMOS single-chip 8-bit microcontroller |
OM5232 |
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QFP PIN FUNCTIONS
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44 |
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34 |
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33 |
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QFP |
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(SOT307±2) |
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11 |
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23 |
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Pin |
Function |
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Pin |
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Function |
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Pin |
Function |
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1 |
P1.5 |
16 |
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VSS1 |
31 |
P0.6/AD6 |
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2 |
P1.6 |
17 |
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NC |
32 |
P0.5/AD5 |
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3 |
P1.7 |
18 |
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P2.0/A8 |
33 |
P0.4/AD4 |
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4 |
RST |
19 |
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P2.1/A9 |
34 |
P0.3/AD3 |
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5 |
P3.0/RxD |
20 |
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P2.2/A10 |
35 |
P0.2/AD2 |
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6 |
VSS4 |
21 |
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P2.3/A11 |
36 |
P0.1/AD1 |
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7 |
P3.1/TxD |
22 |
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P2.4/A12 |
37 |
P0.0/AD0 |
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8 |
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VDD |
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P3.2/INT0 |
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P2.5/A13 |
38 |
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9 |
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VSS3 |
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P3.3/INT1 |
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P2.6/A14 |
39 |
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10 |
P3.4/T0 |
25 |
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P2.7/A15 |
40 |
P1.0 |
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11 |
P3.5/T1 |
26 |
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41 |
P1.1 |
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PSEN |
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12 |
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27 |
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ALE |
42 |
P1.2 |
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P3.6/WR |
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13 |
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VSS2 |
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P3.7/RD |
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28 |
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43 |
P1.3 |
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14 |
XTAL2 |
29 |
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44 |
P1.4 |
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EA/VPP |
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15 |
XTAL1 |
30 |
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P0.7/AD7 |
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NOTE:
1.Due to EMC improvements, all VSS pins (6, 16, 28, 39) must be connected to VSS.
LOGIC SYMBOL
VDDVSS
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RST |
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XTAL1 |
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XTAL2 |
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EA |
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PSEN |
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ALE |
ALTERNATE FUNCTIONS |
PORT 3 |
RxD
TxD
INT0
INT1
T0
T1
WR
RD
PORT 0 |
ADDRESS AND DATA BUS |
PORT 1 |
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PORT 2 |
ADDRESS BUS |
BLOCK DIAGRAM
FREQUENCY |
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COUNTERS |
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REFERENCE |
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XTAL2 |
XTAL1 |
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T0 |
T1 |
OSCILLATOR |
PROGRAM |
DATA |
TWO 16-BIT |
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AND |
MEMORY |
MEMORY |
TIMER/EVENT |
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TIMING |
(8K x 8 ROM) |
(256 x 8 RAM) |
COUNTERS |
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CPU |
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INTERNAL |
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INTERRUPTS |
64K BYTE BUS |
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PROG SERIAL PORT |
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PROGRAMMABLE I/O |
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EXPANSION |
FULL DUPLEX UART |
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CONTRTOL |
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SYNCHRONOUS SHIFT |
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INT0 |
INT1 |
CONTROL |
PARALLEL PORTS, |
SERIAL IN |
SERIAL OUT |
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ADDRESS/DATA BUS |
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EXTERNAL |
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AND I/O PINS |
SHARED WITH |
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PORT 3 |
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INTERRUPTS |
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December 1994 |
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2 |
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Philips Semiconductors |
Product specification |
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CMOS single-chip 8-bit microcontroller |
OM5232 |
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PIN DESCRIPTIONS
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PIN NUMBER |
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MNEMONIC |
DIP |
QFP |
TYPE |
NAME AND FUNCTION |
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VSS |
20 |
6, 16, |
I |
Ground: 0V reference. With the QFP package all VSS pins (VSS1 to VSS4) must be connected. |
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28, 39 |
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VDD |
40 |
38 |
I |
Power Supply: This is the power supply voltage for normal, idle, and power-down operation. |
P0.0±0.7 |
39±32 |
37±30 |
I/O |
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them |
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float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address |
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and data bus during accesses to external program and data memory. In this application, it uses |
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strong internal pull-ups when emitting 1s. |
P1.0±P1.5 |
1±6 |
40±44, |
I/O |
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which |
1are open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current
because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Alternate functions include:
P1.6 |
7 |
2 |
I/O |
open drain output |
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P1.7 |
8 |
3 |
I/O |
open drain output |
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P2.0±P2.7 |
21±28 |
18±25 |
I/O |
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s |
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written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port |
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2 pins that are externally being pulled low will source current because of the internal pull-ups. |
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(See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches |
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from external program memory and during accesses to external data memory that use 16-bit |
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addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. |
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During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the |
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contents of the P2 special function register. |
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P3.0±P3.7 |
10±17 |
5, |
I/O |
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s |
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7±13 |
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written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port |
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3 pins that are externally being pulled low will source current because of the pull-ups. (See DC |
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Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as |
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listed below: |
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10 |
5 |
I |
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RxD (P3.0): Serial input port |
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11 |
7 |
O |
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TxD (P3.1): Serial output port |
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12 |
8 |
I |
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(P3.2): External interrupt |
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INT0 |
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13 |
9 |
I |
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(P3.3): External interrupt |
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INT1 |
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14 |
10 |
I |
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T0 (P3.4): Timer 0 external input |
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15 |
11 |
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T1 (P3.5): Timer 1 external input |
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16 |
12 |
O |
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(P3.6): External data memory write strobe |
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WR |
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17 |
13 |
O |
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(P3.7): External data memory read strobe |
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RD |
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RST |
9 |
4 |
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Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. |
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An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to |
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VDD. |
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ALE |
30 |
27 |
I/O |
Address Latch Enable: Output pulse for latching the low byte of the address during an access |
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to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator |
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frequency. Note that one ALE pulse is skipped during each access to external data memory. |
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29 |
26 |
O |
Program Store Enable: Read strobe to external program memory via Port 0 and Port 2. It is |
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PSEN |
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activated twice each machine cycle during fetches from the external program memory. When |
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executing out of external program memory two activations of PSEN are skipped during each |
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access to external data memory. PSEN is not activated (remains HIGH) during no fetches from |
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external program memory. PSEN can sink/source 8 LSTTL inputs and can drive CMOS inputs |
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without external pull±ups. |
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31 |
29 |
I |
External Access: If during a RESET, |
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EA |
EA |
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internal program memory ROM provided the Program Counter is less than 16384. If during a |
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RESET, EA is held a TTL LOW level, the CPU executes out of external program memory. EA is |
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not allowed to float. |
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XTAL1 |
19 |
15 |
I |
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator |
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circuits. |
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XTAL2 |
18 |
14 |
O |
Crystal 2: Output from the inverting oscillator amplifier. |
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NOTE:
To avoid ªlatch-upº effect at power-on, the voltage on any pin at any time must not be higher than VDD + 0.5V or VSS ± 0.5V, respectively.
December 1994 |
3 |
Philips Semiconductors |
Product specification |
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CMOS single-chip 8-bit microcontroller |
OM5232 |
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Table 1. |
OM5232 Special Function Registers |
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SYMBOL |
DESCRIPTION |
DIRECT |
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BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION |
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RESET |
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ADDRESS |
MSB |
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LSB |
VALUE |
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ACC* |
Accumulator |
E0H |
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E7 |
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E6 |
E5 |
E4 |
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E3 |
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E2 |
E1 |
E0 |
00H |
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B* |
B Register |
F0H |
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F7 |
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F6 |
F5 |
F4 |
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F3 |
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F2 |
F1 |
F0 |
00H |
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DPTR: |
Data Pointer |
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(2 bytes) |
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DPH |
Data Pointer High |
83H |
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00H |
DPL |
Data Pointer Low |
82H |
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00H |
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AF |
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AE |
AD |
AC |
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AB |
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AA |
A9 |
A8 |
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IE*# |
Interrupt Enable |
A8H |
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EA |
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ES1 |
ES0 |
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ET1 |
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EX1 |
ET0 |
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EX0 |
0x000000B |
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BF |
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BE |
BD |
BC |
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BB |
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BA |
B9 |
B8 |
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IP*# |
Interrupt Priority |
B8H |
± |
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PS1 |
PS0 |
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PT1 |
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PX1 |
PT0 |
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PX0 |
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87 |
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86 |
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85 |
84 |
83 |
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82 |
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81 |
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80 |
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P0* |
Port 0 |
80H |
AD7 |
AD6 |
AD5 |
AD4 |
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AD3 |
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AD2 |
AD1 |
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AD0 |
FFH |
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97 |
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96 |
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95 |
94 |
93 |
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92 |
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91 |
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90 |
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P1*# |
Port 1 |
90H |
SDA |
SCL |
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FFH |
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A7 |
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A6 |
A5 |
A4 |
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A3 |
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A2 |
A1 |
A0 |
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P2* |
Port 2 |
A0H |
A15 |
A14 |
A13 |
A12 |
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A11 |
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A10 |
A9 |
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A8 |
FFH |
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B7 |
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B6 |
B5 |
B4 |
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B3 |
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B2 |
B1 |
B0 |
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P3* |
Port 3 |
B0H |
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T1 |
T0 |
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TXD |
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RXD |
FFH |
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RD |
WR |
INT1 |
INT0 |
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PCON |
Power Control |
87H |
SMOD |
± |
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± |
± |
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GF1 |
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GF0 |
PD |
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IDL |
0xxx0000B |
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9F |
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9E |
9D |
9C |
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9B |
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9A |
99 |
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98 |
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S0CON*# |
Serial 0 Port Control |
98H |
SM0 |
SM1 |
SM2 |
REN |
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TB8 |
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RB8 |
TI |
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RI |
00H |
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S0BUF# |
Serial 0 Data Buffer |
99H |
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xxxxxxxxB |
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D7 |
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D6 |
D5 |
D4 |
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D3 |
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D2 |
D1 |
D0 |
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PSW* |
Program Status Word |
D0H |
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CY |
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AC |
F0 |
RS1 |
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RS0 |
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OV |
F1 |
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P |
00H |
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reserved (Note 1) |
DAH |
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00H |
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SP |
Stack Pointer |
81H |
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07H |
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reserved (Note 1) |
DBH |
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00H |
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reserved (Note 1) |
D9H |
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F8H |
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reserved (Note 1) |
D8H |
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00000000B |
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8F |
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8E |
8D |
8C |
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8B |
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8A |
89 |
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88 |
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TCON* |
Timer Control |
88H |
TF1 |
TR1 |
TF0 |
TR0 |
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IE1 |
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IT1 |
IE0 |
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IT0 |
00H |
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TH1 |
Timer High 1 |
8DH |
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00H |
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TH0 |
Timer High 0 |
8CH |
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00H |
TL1 |
Timer Low 1 |
8BH |
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00H |
TL0 |
Timer Low 0 |
8AH |
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00H |
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||||||||
TMOD |
Timer Mode |
89H |
GATE |
|
|
|
|
|
M1 |
M0 |
GATE |
|
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M1 |
|
M0 |
00H |
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C/T |
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C/T |
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|||||||||||||||||||
*SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
NOTE
1. Reserved for I2C; not supported in OM5232
December 1994 |
4 |
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