Philips om4068 DATASHEETS
INTEGRATED CIRCUITS
DATA SH EET
OM4068
LCD driver for low multiplex rates
Product specification
File under Integrated Circuits, IC12
1998 Jun 18
Philips Semiconductors Product specification
LCD driver for low multiplex rates
FEATURES
• Single-chip LCD controller/driver
• Static/duplex/triplex drive modes with up to
32/64/96 LCD segments drive capability per device
• Selectable backplane drive configuration: static or
2 or 3 backplane multiplexing
• Selectable display bias configuration drive: static,1⁄2 or
1
⁄
3
• 32 segment drivers
• Serial data input (word length 32 to 96 bits)
• On-chip generation of intermediate LCD bias voltages
• 2 MHz fast serial bus interface
• CMOS compatible
• Compatible with any 4-bit, 8-bit or 16-bit
microprocessors/microcontrollers
• May be cascaded for large LCD applications
• Logic supply voltage range (V
• Display supply voltage range (V
3.5 to 6.5 V
• Low power consumption, suitable for battery operated
systems
• No external components needed by the oscillator
• Manufactured in silicon gate CMOS process.
− VSS) of 2.5 to 5.5 V
DD
− VSS) of
LCD
OM4068
APPLICATIONS
• Telecom equipment
• Portable instruments
• Alarm systems
• Automotive equipment.
GENERAL DESCRIPTION
The OM4068 is a low-power CMOS LCD driver, designed
to drive Liquid Crystal Displays (LCDs) with low multiplex
rates. It generates the drive signals for any static or
multiplexed LCD containing up to three backplanes and up
to 32 segment lines and can be easily cascaded for larger
LCD applications. All necessary functions for the display
are provided in a single chip, including on-chip generation
of LCD bias voltages, resulting in a minimum of external
components and lower power consumption. A 3-line bus
structure enables serial data transfer with most
microprocessors/microcontrollers. All inputs are CMOS
compatible.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME DESCRIPTION VERSION
OM4068H
(1)
QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm);
SOT307-2
body 10 × 10 × 1.75 mm
OM4068P DIP40 plastic dual in-line package; 40 leads (600 mil) SOT129-1
OM4068U/5
(2)
die unsawn wafer −
OM4068U tray chip in tray −
Notes
1. Gull Wing package.
2. For details see Chapter “Bonding pad locations”.
1998 Jun 18 2
Philips Semiconductors Product specification
LCD driver for low multiplex rates
BLOCK DIAGRAM
handbook, full pagewidth
V
BACKPLANE OUTPUTS
M0
M1
LCD
BP2BP1 BP3 SEG1 to SEG32
4
LCD VOLTAGE
SELECTOR
(CONTROL LOGIC)
4
BIAS
VOLTAGE
GENERATOR
OM4068
(1)
32
DISPLAY SEGMENT OUTPUTS
4
DISPLAY LATCH
SCE
SHIFT REGISTER
OM4068
SCLK
SDIN
SDOUT
POWER-ON
RESET
VSSV
(1) SEG1, SEG6, SEG15 and SEG25 are not available in DIP40 package.
Fig.1 Block diagram.
1998 Jun 18 3
TIMING
GENERATOR
DD
OSCILLATOR
MBK817
Philips Semiconductors Product specification
LCD driver for low multiplex rates
PINNING
See notes 1 to 8.
SYMBOL
V
LCD
V
DD
V
SS
M0 7 22 drive mode select input 0
M1 8 23 drive mode select input 1
SDIN 9 24 serial bus data input
SCLK 10 25 serial bus clock input
SCE 11 26 serial bus clock enable
SDOUT 12 27 serial bus data output
BP1 13 28 LCD backplane driver output 1
BP2 14 29 LCD backplane driver output 2
BP3 15 30 LCD backplane driver output 3
SEG1 16 − LCD segment driver output 1
SEG2 17 31 LCD segment driver output 2
SEG3 18 32 LCD segment driver output 3
SEG4 19 33 LCD segment driver output 4
SEG5 20 34 LCD segment driver output 5
SEG6 21 − LCD segment driver output 6
SEG7 22 35 LCD segment driver output 7
SEG8 23 36 LCD segment driver output 8
SEG9 24 37 LCD segment driver output 9
SEG10 25 38 LCD segment driver output 10
SEG11 26 39 LCD segment driver output 11
SEG12 27 40 LCD segment driver output 12
SEG13 28 1 LCD segment driver output 13
SEG14 29 2 LCD segment driver output 14
SEG15 30 − LCD segment driver output 15
SEG16 31 3 LCD segment driver output 16
SEG17 32 4 LCD segment driver output 17
SEG18 33 5 LCD segment driver output 18
SEG19 34 6 LCD segment driver output 19
SEG20 35 7 LCD segment driver output 20
SEG21 36 8 LCD segment driver output 21
SEG22 37 9 LCD segment driver output 22
SEG23 38 10 LCD segment driver output 23
SEG24 39 11 LCD segment driver output 24
SEG25 40 − LCD segment driver output 25
SEG26 41 12 LCD segment driver output 26
QFP44 DIP40
4 19 LCD supply voltage
5 20 positive supply voltage
6 21 ground
PIN
DESCRIPTION
OM4068
1998 Jun 18 4
Philips Semiconductors Product specification
LCD driver for low multiplex rates
SYMBOL
SEG27 42 13 LCD segment driver output 27
SEG28 43 14 LCD segment driver output 28
SEG29 44 15 LCD segment driver output 29
SEG30 1 16 LCD segment driver output 30
SEG31 2 17 LCD segment driver output 31
SEG32 3 18 LCD segment driver output 32
Notes
1. SEG1 to SEG32 (LCD segment driver outputs) output the multi-level signals for the LCD segments.
2. BP0, BP1 and BP2 (LCD backplane driver outputs) output the multi-level signals for the LCD backplanes.
3. V
4. SDIN (serial data line): input for the bus data line.
5. SCL (serial clock line): input for the bus clock line.
6. SDOUT (serial data output): output of the shift register to allow serial cascading of the OM4068 with other devices.
7. SCE (serial clock enable): input for enable/disable acquisition on the data input line. If disabled, data on the serial
8. M0 and M1 (display mode select inputs): inputs to select the LCD drive configurations; static, duplex or triplex.
(LCD power supply): power supply for the LCD.
LCD
bus are not accepted by the device.
QFP44 DIP40
PIN
DESCRIPTION
OM4068
1998 Jun 18 5
Philips Semiconductors Product specification
LCD driver for low multiplex rates
handbook, full pagewidth
SEG28
SEG29
44
43
1SEG30
2
SEG31
SEG32
3
V
4
LCD
V
5
DD
V
6
SS
7
M0
M1
8
SDIN
9
SCLK
10
SCE
11
SEG27
42
SEG26
41
OM4068H
SEG25
40
SEG24
39
SEG23
38
SEG22
37
SEG21
36
SEG20
35
SEG19
34
33
32
31
30
29
28
27
26
25
24
23
OM4068
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
12
13
14
15
16
17
18
BP1
BP2
BP3
SEG1
SEG2
SDOUT
SEG3
Fig.2 Pin configuration (QFP44).
19
SEG4
20
SEG5
21
SEG6
22
MBK814
SEG7
1998 Jun 18 6
Philips Semiconductors Product specification
LCD driver for low multiplex rates
handbook, halfpage
SEG13 SEG12
SEG14 SEG11
SEG16 SEG10
SEG17 SEG9
SEG18 SEG8
SEG19 SEG7
SEG20 SEG5
SEG21 SEG4
SEG22 SEG3
SEG23 SEG2
SEG24 BP3
SEG26 BP2
SEG27 BP1
SEG28 SDOUT
SEG29 SCE
SEG30 SCLK
SEG31 SDIN
SEG32 M1
V
LCD
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
OM4068P
MBK815
OM4068
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
M0
V
21
SS
Fig.3 Pin configuration (DIP40).
1998 Jun 18 7
Philips Semiconductors Product specification
LCD driver for low multiplex rates
FUNCTIONAL DESCRIPTION
The OM4068 is a low-power LCD driver designed to
interface with any microprocessor/microcontroller and a
wide variety of LCDs. It can drive any static or multiplexed
LCD containing up to three backplanes and
up to 96 segments.
Table 1 Selection of display configurations
NUMBER OF 7-SEGMENTS NUMERIC
BACKPLANES
3 96 12 12 96 dots (3 × 32)
2 64 8 8 64 dots (2 × 32)
1 32 4 4 32 dots (1 × 32)
DISPLAY
SEGMENTS
OM4068
The display configurations possible with the OM4068
depend on the number of active backplane outputs
required; a selection of display configurations is given in
Table 1.
A typical system (MUX 1 : 3) is shown in Fig.4.
DIGITS
INDICATOR
SYMBOLS
DOT MATRIX
handbook, full pagewidth
(1) 28 segment drivers for DIP40 package.
V
DD
MICROPROCESSOR/
MICROCONTROLLER
V
SS
HOST
SDIN
SCLK
SCE
Fig.4 Typical system configuration.
The host microprocessor/microcontroller maintains the
3-line bus communication channel with OM4068.
The internal oscillator requires no external components.
The appropriate intermediate biasing voltage for the
multiplexed LCD waveforms are generated on-chip.
V
M1 M0
DD
OM4068
V
LCD
V
32 segment drivers
3 backplanes
SS
SDOUT
(1)
LCD PANEL
(up to 96
elements)
MBK818
The only other connections required to complete the
system are to the power supplies (VSS, VDDand V
suitable capacitors to decouple the V
LCD
VSS.
) and
LCD
and VDD pins to
1998 Jun 18 8
Philips Semiconductors Product specification
LCD driver for low multiplex rates
Power-on reset
The on-chip power-on reset block initializes the chip after
power-on or power failures. The OM4068 resets to a
starting condition as follows:
• All backplane and segment outputs are set to V
(display off)
• All shift registers and latches are set in 3-state
• SDOUT (allowing serial cascading) is set to logic 0 (with
SCE LOW)
• Power-down mode.
Data transfers on the serial bus should be avoided for
0.5 ms following power-on to allow completion of the reset
action.
Power-down
After power-on the chip is in power-down mode as long as
the serial clock is not active. During power-down all static
currents are switched off (no internal oscillator, no timing
and no bias level generation) and all LCD-outputs are
3-stated. The power-on reset functions remain enabled.
The power-down mode is disabled at the first rising edge
of the serial clock SCLK.
LCD bias voltage generator
The intermediate bias voltages for the LCD display are
generated on-chip. This removes the need for an external
resistive bias chain and significantly reduces the system
power consumption. The full-scale LCD voltage V
equals V
− VSS. The optimum value of VOP depends on
LCD
the LCD threshold voltage (Vth) and the number of bias
levels.
SS
OP
OM4068
The bias levels depend on the multiplex rate and are
selected automatically when the display configuration is
selected using M1 and M0.
LCD voltage selector
The LCD voltage selector (control logic) coordinates the
multiplexing of the LCD in accordance with the selected
drive or display configuration. The operation of the voltage
selector is controlled by the input pins M0 and M1
(see Table 2).
Table 2 Drive mode selection
M1 M0 DRIVE MODE
0 0 test mode (not user accessible)
0 1 static drive (1 : 1)
1 0 duplex drive (1 : 2)
1 1 triplex drive (1 : 3)
For multiplex rates of 1 : 2 three bias levels are used
including V
1 : 3 multiplex rate. The various biasing configurations
together with the biasing characteristics as functions of
VOP=V
(D), are given in Table 3.
A practical value for VOP is determinated by equating
V
off(rms)
typically when the LCD exhibits approximately 10%
contrast. In static mode a suitable choice is VOP>3Vth.
and VSS. Four bias level are used for the
LCD
− VSS and the resulting discrimination ratios
LCD
with a defined LCD threshold voltage (Vth),
Fractional LCD biasing voltages are obtained from an
internal voltage divider of three series resistors (1⁄3bias)
connected between V
and VSS. The centre resistor can
LCD
be switched out of the circuit to provide a1⁄2bias voltage
level for the 1 : 2 multiplex configuration.
1998 Jun 18 9
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