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Philips Semiconductors Linear Products	Product specification


6-Bit A/D converter (parallel outputs)	NE5037

DESCRIPTION

The NE5037 is a low cost, complete successive-approximation analog-to-digital (A/D) converter, fabricated using Bipolar/I2L technology. With an external reference voltage, the NE5037 will accept input voltages between 0V and VREF. An external START pulse of at least 300ns in duration will provide the 6-bit result of the conversion in parallel format. Full conversion with no missing codes occurs in 9μs.

FEATURES

•TTL-compatible inputs and outputs

•3-State output buffer

•Easy interface to CMOS microprocessors

•Fast conversionÐ9 μs

•Guaranteed no missing codes over full temp range

•Single-supply operation, +5V

•Positive true binary outputs

•High-impedance analog inputs

PIN CONFIGURATION

N Package


	VCC		1	16	B5 (MSB)

	VREF		2	15	B4

	VIN		3	14	B3
					B2
ANALOG GND			4	13	B2

DIGITAL GND			5	12	B1
	CLK
	CLK		6	11	B0

	START		7	10		EOC

		CS	8	9		EO

TOP VIEW

•μP-based appliances

•Light level monitors

•Head position sensing

•Electronic toys

•Joystick interface

APPLICATIONS

•Temperature control

ORDERING INFORMATION

DESCRIPTION	TEMPERATURE RANGE	ORDER CODE	DWG #

16-Pin Plastic Dual In-Line Package (DIP)	0 to +70°C	NE5037N	0406C

BLOCK DIAGRAM

				VCC
				1
			1/2	COM
			1/2
	IIN		LSB
2	IIN		6±BIT	IO
2	V/I		6±BIT	IO
VREF	V/I		DAC
			DAC
				DB	16	DB5
				DB		DB5
3	V/I
VIN	V/I
4
AGND	CONTROL
	CONTROL		SAR
5	LOGIC		SAR		11
5	LOGIC				11
DGND				DB		DBO
6
CLK
				EOC	10	EOC
				EOC		EOC
7	8	9
START	CS	EOC

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853-0939 13721

Philips Semiconductors Linear Products	Product specification

6-Bit A/D converter (parallel outputs)	NE5037

ABSOLUTE MAXIMUM RATINGS

	SYMBOL				PARAMETER		RATING	UNIT

VCC		Power supply voltage					7	V
VREF		Reference voltage					7	V
VIN(Analog)		Analog input voltage					7	V
VIN(Digital)		Digital input voltage				CLK)	7	V
VIN(Digital)		Digital input voltage	(CS,	OE,	START,	CLK)	7	V
DOUT		Data outputs (DB0 to DB5)
		3-state mode					7	V
		Enabled mode (each output)					5	mA

		End of conversion					VCC
EOC		End of conversion					VCC
GND		Analog GND to digital GND					±1	V
TA		Operating temperature range					0 to 70	°C
TSTG		Storage temperature range					-65 to 150	°C
TSOLD		Lead soldering temperature (10 seconds)					300	°C
P		Maximum power dissipation, T =25°C (still-air)1
D					A
		N package					1450	mW

NOTES:

1. Derate above 25°C at the following rates:

N package=11.6mW/°C

DC ELECTRICAL CHARACTERISTICS

VCC=5.0V; VREF=2.0V; Clock=1MHz; 0°C ≤ TA ≤ 70°C unless otherwise specified. Typical values are specified at 25°C

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

Min

Typ

Max

Resolution

Bits

Relative accuracy1,2

1/4

1/2

LSB

VCC

Positive supply voltage

+4.75

+5.0

+5.50

Full-scale gain error2,3,4

=2.0V, T =25°C

±1

±2

LSB

REF

Zero-scale offset error2

=2.0V, T =25°C

±1/2

-1/2, +2

LSB

REF

PSR

Power supply rejection, Max change in full-scale2

V =2.0V, 4.75V≤V

≤5.5V

±1/2

±1

LSB

REF

IIN

Analog input bias current

0≤VIN≤2.5V

μA

IREF

Reference bias current

0≤VREF≤2.5V

μA

RIN

Analog input resistance

MΩ

VIH

Logic º1' input voltage

2.0

VIL

Logic º0' input voltage

0.8

IIH

Logic º1' input current

μA

IIL

Logic º0' input current

μA

Logic º1' output current5

2.4V≤V

300

μA

Logic º0' output current5

≤0.4V

1.6

IOZ

3-State leakage current

±0.1

±40

μA

ICC

Positive supply current

Power dissipation

132

NOTES:

1.Relative accuracy is defined as the deviation of the code transition points from the ideal code transition points on a straight line drawn from zero-scale to full-scale of the device.

2.Specifications given in LSBs refer to the weight of the least significant bit at the 6-bit level which is 1.56% of the full-scale voltage.

3.Full-scale gain error is the deviation of the full-scale code transition point (111110 to 111111) from its ideal value.

4.The analog input voltage (VIN) range is 0V to VREF nominally, with the output remaining at 111111 even though the input may increase from VREF to VCC. (For optimum performance, VREF can be any value from 1.5V to 2.5V.)

5.The data outputs have active pull-ups. The EOC line is open-collector with a nominal 5kΩ internal pull-up resistor.

August 31, 1994

583

Philips Semiconductors Linear Products	Product specification

6-Bit A/D converter (parallel outputs)	NE5037

AC ELECTRICAL CHARACTERISTICS

VCC=5.0V; VREF=2.0V; Clock=1MHz; 0°C ≤ TA ≤ 70°C unless otherwise specified. Typical values are specified at 25°C (Refer to AC test figures.)

SYMBOL

PARAMETER

FROM

TEST CONDITIONS

LIMITS

UNIT

Min

Typ

Max

fMAX

Maximum clock frequency

MHz

Start pulse width

300

Minimum positive/negative

300

clock pulse width

tCONV

Conversion time

Clock cycles

Propagation delay1

Data out

T =25°C t

=t ≤20ns

500

P (OUT DATA)

Propagation delay2

Clock

T =25°C t

=t ≤20ns

800

EOC

P (OUT EOC)

tP (3-STATE)

Propagation delay, 3-State

3-State Data

TA=25°C tR=tF≤20ns

500

NOTES:

1.Propagation delay of data outputs is defined as the delay in the data outputs reading their final value after the low going edge of OE.

2.Propagation delay of EOC is defined as the delay in EOC going low, following the low going edge of the 9th clock pulse after the start pulse.

CIRCUIT DESCRIPTION

NE5037 is a complete 6-bit, parallel output, microprocessor compatible, A/D converter which incorporates the successive-approximation method. The chip includes the internal control logic, the successive-approximation register (SAR), 6-bit

DAC, comparator and output buffers. An externally-generated clock source (max frequency=1MHz) must be provided to Pin 6. An external reference voltage supplied to Pin 2 sets the full-scale range of the A/D converter.

The CS pin must be at a low level prior to the start of the conversion process. Upon receipt of a START pulse, the internal control logic resets the SAR. On the first low-going edge of the clock pulse, successive approximation conversion commences. Successive bits beginning with the MSB (D5) are supplied to the input of the internal

6-bit current output DAC by the I2L successive approximation register.

The comparator determines whether the output current of the DAC is greater or less than the input current, which is converted from the unknown analog input voltage through the V/I converter. If the DAC output is greater, that bit of the DAC is set to º0' and the corresponding output buffer goes to º0' simultaneously. If it is less, it stays at `1' and the output buffer also stays at `1'. On successive clock pulses, successive bits of the DAC are tried and the corresponding output buffer represents the bits of the DAC. On the eighth low-going edge of the clock pulse (after the receipt of the start pulse), the EOC pin goes low, thereby indicating that the conversion is complete. The output data is now valid. In order to access the result of the conversion, the OE pin must be set to a low level. EOC is reset to a high state when OE is low. When OE is in a º1' state, the output buffers are in a high impedance state.

Refer to Figure 1 for the timing diagram.

CS	DON'T CARE
	DON'T CARE
START
CLK
OE
EOC
	HIGH	HIGH	HIGH
DATA	IMPEDANCE	IMPEDANCE	IMPEDANCE
DATA
OUTPUTS
	DATA
	READY
	HIGH		HIGH
	AVAILABLE	AVAILABLE
	Figure 1. Timing Diagram
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