N74F521D
74F521
8-bit identity comparator
Product specification
IC15 Data Handbook
1990 May 15
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74F5218-bit identity comparator
2
May 15, 1990 853–0372 99601
FEA TURES
•Compares two 8-bit words in 6.5ns typical
•Expandable to any word length
DESCRIPTION
The 74F521 is an expandable 8-bit comparator. It compares two
words of up to 8 bits each and provides a Low output when the two
words match bit for bit. The expansion input I
A=B
also serves as an
active-Low enable input.
TYPE
TYPICAL
PROPAGATION
DELA Y
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F521 7.0ns 24mA
PIN CONFIGURATION
SF00273
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
I
A=B
A0
B0
A1
B1
A2
B2
A3
B3
GND
V
CC
Q
A=B
B7
A7
B6
A6
B5
B4
A5
A4
ORDERING INFORMA TION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V ±10%, T
amb
= 0°C to +70°C
PKG DWG #
20-pin plastic DIP N74F521N SOT146-1
20-pin plastic SOL N74F521D SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW
A0 – A7 Word A inputs 1.0/1.0 20µA/0.6mA
B0 – B7 Word B inputs 1.0/1.0 20µA/0.6mA
I
A=B
Expansion or Enable input (active Low) 1.0/1.0 20µA/0.6mA
Q
A=B
Identity output (active Low) 50/33 1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
Q
A=B
19
V
CC
= Pin 20
GND = Pin 10
SF00274
2
3
4
5
6
7
8
9
11
12
13
14
15
A0
B0
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
16
17
18
B6
A7
B7
I
A=B
1
IEC/IEEE SYMBOL
SF00275
COMP
19
2
4
6
8
11
13
15
17
0
3
A=B
A
3
5
7
9
12
14
15
18
0
7
B
1
EN
Philips Semiconductors Product specification
74F5218-bit identity comparator
May 15, 1990
3
LOGIC DIAGRAM
V
CC
= Pin 20
GND = Pin 10
SF00276
19
Q
A=B
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
1
A0
B0
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
I
A=B
FUNCTION TABLE
INPUTS OUTPUT
I
A=B
A, B Q
A=B
L A=B* L
L A≠B H
H A=B* H
H A≠B H
H = High voltage level
L = Low voltage level
X = Don’t care
* A0=B0, A1=B1, A2=B2, etc.
APPLICATIONS
I
A=B
SF00277
A16 B16 A23 B23
Q
A=B
I
A=B
A8 B8 A15 B15
Q
A=B
I
A=B
A0 B0 A7 B7
Q
A=B
PARALLEL EXPANSION
I
A=B
A16 B16 A23 B23
Q
A=B
I
A=B
A8 B8 A15 B15
Q
A=B
I
A=B
A0 B0 A7 B7
Q
A=B
ENABLE
LOW
ENABLE
LOW
RIPPLE EXPANSION
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