N74F51D
74F51
Dual 2-wide 2-input, 2-wise 3-input
AND-OR-invert gate
Product specification
IC15 Data Handbook
1989 Mar 03
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74F51Dual 2-wide 2-input, 2-wide 3-input AND-OR-invert gate
2
March 3, 1989 853–0054 95962
TYPE
TYPICAL
PROPAGATION
DELA Y
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F51 3.0ns 3.5mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V ±10%,
T
amb
= 0°C to +70°C
PKG DWG #
14-pin plastic DIP N74F51N SOT27-1
14-pin plastic SO N74F51D SOT108-1
PIN CONFIGURATION
14
13
12
11
10
9
87
6
5
4
3
2
1
GND
V
CC
D0e
D0d
Q0
D0f
D0c
D0b
D0a
D1a
Q
1
D1b
D1c
D1d
SF00085
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW
Dna, Dnb, Dnc, Dnd, Dne, Dnf Data inputs 1.0/1.0 20µA/0.6mA
Q0, Q1 Data outputs 50/33 1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
D1aD0fD0b D0c D0d D1b D1cD0e
Q0 Q1
86
12 13 9 10 11 2 3 4
V
CC
= Pin 14
GND = Pin 7
SF00086
D0a
1
D1d
5
IEC/IEEE SYMBOL
SF00087
1
8
6
9
10
11
13
12
1
2
3
4
5
1
&
&
&
&
LOGIC DIAGRAM
V
CC
= Pin 14
GND = Pin 7
SF00088
1
12
13
2
3
D0a
D0b
D0c
D1a
D1b
Q0
8
9
10
11
D0d
D0e
D0f
4
5
D1c
D1d
Q1
6
FUNCTION TABLE FOR 3-INPUT GATES
INPUTS OUTPUT
D0a D0b D0c D0d D0e D0f Q0
H H H X X X L
X X X H H H L
All other combinations H
NOTES:
H = High voltage level
L = Low voltage level
X = Don’t care
FUNCTION TABLE FOR 2-INPUT GATES
INPUTS OUTPUT
D1a D1b D1c D1d Q1
H H X X L
X X H H L
All other combinations H
NOTES:
H = High voltage level
L = Low voltage level
X = Don’t care
Philips Semiconductors Product specification
74F51Dual 2-wide 2-input, 2-wide 3-input AND-OR-invert gate
March 3, 1989
3
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER RATING UNIT
V
CC
Supply voltage –0.5 to +7.0 V
V
IN
Input voltage –0.5 to +7.0 V
I
IN
Input current –30 to +5 mA
V
OUT
Voltage applied to output in High output state –0.5 to V
CC
V
I
OUT
Current applied to output in Low output state 40 mA
T
amb
Operating free-air temperature range 0 to +70 °C
T
stg
Storage temperature range –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5.0 5.5 V
V
IH
High-level input voltage 2.0 V
V
IL
Low-level input voltage 0.8 V
I
IK
Input clamp current –18 mA
I
OH
High-level output current –1 mA
I
OL
Low-level output current 20 mA
T
amb
Operating free-air temperature range 0 +70 °C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
SYMBOL
PARAMETER
TEST
CONDITIONS
1
MIN TYP
2
MAX
UNIT
p
V
CC
= MIN, V
IL
= MAX ±10%V
CC
2.5 V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
V
IH
= MIN, I
OH
= MAX ±5%V
CC
2.7 3.4 V
p
V
CC
= MIN, V
IL
= MAX ±10%V
CC
0.30 0.50 V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
V
IH
= MIN, I
OL
= MAX ±5%V
CC
0.30 0.50 V
V
IK
Input clamp voltage V
CC
= MIN, I
I
= I
IK
–0.73 –1.2 V
I
I
Input current at maximum input
voltage
V
CC
= MAX, V
I
= 7.0V 100 µA
I
IH
High-level input current V
CC
= MAX, V
I
= 2.7V 20 µA
I
IL
Low-level input current V
CC
= MAX, V
I
= 0.5V –0.6 mA
I
OS
Short-circuit output current
3
V
CC
= MAX –60 –150 mA
pp
I
CCH
V
IN
= GND 1.8 3.0 mA
I
CC
S
u
ppl
y
c
u
rrent
(total)
I
CCL
V
CC
=
MAX
V
IN
= 4.5V 5.5 7.5 mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
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