Philips N74F50729D, N74F50729N Datasheet
INTEGRATED CIRCUITS
74F50729
Synchronizing dual D-type flip-flop with
edge-triggered set and reset with
metastable immune characteristics
Product specification
IC15 Data Handbook
1990 Sep 14
Philips Semiconductors Product specification
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
FEA TURES
•Metastable immune characteristics
•Output skew less than 1.5ns
•High source current (I
applications
= 15mA) ideal for clock driver
OH
•See 74F5074 for synchronizing dual D–type flip–flop
•See 74F50109 for synchronizing dual J–K positive
edge–triggered flip–flop
•See 74F50728 for synchronizing cascaded dual D–type flip–flop
•Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F50729 is a dual positive edge–triggered D–type featuring
individual data, clock, set and reset inputs; also true and
complementary outputs.
The 74F50729 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
metastable state. Typical metastability parameters for the 74F50729
are: τ ≅ 135ps and τ ≅ 9.8 X 10
of the rate at which a latch in a metastable state resolves that
condition and T
represents a function of the measurement of the
o
propensity of a latch to enter a metastable state.
Set (SDn) and reset (RDn) are asynchronous positive–edge
triggered inputs and operate independently of the clock (CPn) input.
Data must be stable just one setup time prior to the low–to–high
transition of the clock for guaranteed propagation delays.
Clock triggering occurs at a voltage level and is not directly related
to the transition time of the positive–going pulse. Following the hold
time interval, data at the Dn input may be changed without affecting
the levels of the output.
6
sec where τ represents a function
PIN CONFIGURATION
RD0
D0
CP0
SD0
Q0
Q
GND
TYPE TYPICAL f
74F50729 120 MHz 19mA
74F50729
V
MAX
14
CC
13
RD1
D1
12
11
CP1
10
SD1
9
Q1
87
Q1
SF00611
TYPICAL SUPPL Y
CURRENT (TOTAL)
1
2
3
4
5
0
6
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE INDUSTRIAL RANGE
DESCRIPTION
VCC = 5V ±10%, VCC = 5V ±10%,
T
= 0°C to +70°C T
amb
= –40°C to +85°C
amb
PKG DWG #
14–pin plastic DIP N74F50729N I74F50729N SOT27-1
14–pin plastic SO N74F50729D I74F50729D SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION
74F (U.L.) HIGH/
LOW
D0, D1 Data inputs 1.0/0.417 20µA/250µA
CP0, CP1 Clock inputs (active rising edge) 1.0/1.0 20µA/20µA
SD0, SD1 Set inputs (active rising edge) 1.0/1.0 20µA/20µA
RD0, RD1 Reset inputs (active rising edge) 1.0/1.0 20µA/20µA
Q0, Q1, Q0, Q1 Data outputs 750/33 15mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
1990 Sep 14 853-1390 00420
2
LOAD VALUE HIGH/
LOW
Philips Semiconductors Product specification
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
LOGIC SYMBOL
212
D1D0
Q0 Q0 Q1 Q1
56 98
SF00612
VCC = Pin 14
GND = Pin 7
3
CP0
4
SD0
RD0
1
11
CP1
10
SD1
13
RD1
MET ASTABLE IMMUNE CHARACTERISTICS
Philips Semiconductors uses the term ‘metastable immune’ to
describe characteristics of some of the products in its family.
Specifically the 74F50XXX family presently consist of 4 products
which will not glitch or display metastable immune characteristics.
This term means that the outputs will not glitch or display an output
anomaly under any circumstances including setup and hold time
violations. This claim is easily verified on the 74F5074. By running
two independent signal generators (see Fig. 1) at nearly the same
frequency (in this case 10MHz clock and 10.02 MHz data) the
device–under–test can be often be driven into metastable state. If
the Q output is then used to trigger a digital scope set to infinite
persistence the Q
run by continuously operating the devices in the region where
metastability will occur.
When the device–under–test is a 74F74 (which was not designed
with metastable immune characteristics) the waveform will appear
as in Fig. 2.
Figure 2 shows clearly that the Q
respect to the Q trigger point. This also implies that the Q or Q
output waveshapes may be distorted. This can be verified on an
analog scope with a charge plate CRT. Perhaps of even greater
interest are the dots running along the 3.5V volt line in the upper
right hand quadrant. These show that the Q
state even though the Q output glitched to at least 1.5 volt, the
trigger point of the scope.
When the device–under–test is a metastable immune part, such as
the 74F5074, the waveform will appear as in Fig. 3. The 74F5074 Q
output will appear as in Fig. 3. The 74F5074 Q output will not vary
with respect to the Q trigger point even when the a part is driven into
a metastable state. Any tendency towards internal metastability is
resolved by Philips Semiconductors patented circuitry. If a
metastable event occurs within the flop the only outward
output will build a waveform. An experiment was
output can vary in time with
output did not change
IEC/IEEE SYMBOL
manifestation of the event will be an increased clock–to–Q/Q
propagation delay. This propagation delay is, of course, a function of
the metastability characteristics of the part defined by τ and T
The metastability characteristics of the 74F5074 and related part
types represent state–of–the–art TTL technology.
After determining the T
between failures (MTBF) is simple. Suppose a designer wants to
use the 74F50729 for synchronizing asynchronous data that is
arriving at 10MHz (as measured by a frequency counter), has a
clock frequency of 50MHz, and has decided that he would like to
sample the output of the 74F50729 10 nanoseconds after the clock
edge. He simply plugs his number into the equation below:
MTBF = e
In this formula, fC is the frequency of the clock, fI is the average
input event frequency , and t’ is the time after the clock pulse that the
output is sampled (t’ < h, h being the normal propagation delay). In
this situation the f
because input events consist of both of low and high transitions.
Multiplying f
clear that the MTBF is greater than 10
formula the actual MTBF is 1.51 X 10
(t’/t)
/ TofCf
by fC gives an answer of 10
I
SIGNAL GENERATOR
SIGNAL GENERATOR
74F50729
4
3
2
1
10
11
12
13
and t of the flop, calculating the mean time
0
I
will be twice the data frequency of 20 MHz
I
Figure 1. Test Setup
S
1D
R
S
2D
R
&
C1
C2
DQ
3
6
9
8
SF00613
15
Hz2. From Fig. 3. it is
10
seconds. Using the above
10
seconds or about 480 years.
TRIGGER
DIGITAL
SCOPE
INPUT
SF00586
CP
Q
0.
1990 Sep 14
3
Philips Semiconductors Product specification
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
COMP ARISON OF METASTABLE IMMUNE AND NON–IMMUNE CHARACTERISTICS
4
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
Figure 2. 74F74 Q output triggered by Q output, setup and hold times violated
74F50729
SF00587
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
Figure 3. 74F74 Q output triggered by Q output, setup and hold times violated
SF00588
1990 Sep 14
4
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