Philips N74F50729D, N74F50729N Datasheet

INTEGRATED CIRCUITS

74F50729

Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics

Product specification

1990 Sep 14

IC15 Data Handbook

m n r

Philips Semiconductors	Product specification

Synchronizing dual D-type flip-flop with edge-triggered

74F50729

set and reset and metastable immune characteristics

FEATURES			PIN CONFIGURATION
•Metastable immune characteristics
•Output skew less than 1.5ns									VCC
•High source current (IOH = 15mA) ideal for clock driver			RD0			1		14
applications				D0		2		13	RD1
									D1
•See 74F5074	for synchronizing dual D±type flip±flop		CP0			3		12
•See 74F50109 for synchronizing dual J±K		positive	SD0			4		11	CP1
				Q0
edge±triggered flip±flop						5		10	SD1
•See 74F50728 for synchronizing cascaded dual D±type flip±flop
				Q0		6		9	Q1
•Industrial temperature range available (±40°C to +85°C)			GND			7		8		Q1
								SF00611

DESCRIPTION

The 74F50729 is a dual positive edge±triggered D±type featuring individual data, clock, set and reset inputs; also true and complementary outputs.

The 74F50729 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74F50729 are: τ 135ps and τ 9.8 X 106 sec where τ represents a function of the rate at which a latch in a metastable state resolves that condition and To represents a function of the measurement of the propensity of a latch to enter a metastable state.

Set (SDn) and reset (RDn) are asynchronous positive±edge triggered inputs and operate independently of the clock (CPn) input. Data must be stable just one setup time prior to the low±to±high transition of the clock for guaranteed propagation delays.

Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive±going pulse. Following the hold time interval, data at the Dn input may be changed without affecting the levels of the output.

		TYPICAL SUPPLY
TYPE	TYPICAL fMAX	CURRENT (TOTAL)
74F50729	120 MHz	19mA

ORDERING INFORMATION

						ORDER CODE
					COMMERCIAL RANGE		INDUSTRIAL RANGE
DESCRIPTION					VCC = 5V ±10%,		VCC = 5V ±10%,	PKG DWG #
					Tamb = 0°C to +70°C		Tamb = ±40°C to +85°C
14±pin plastic DIP					N74F50729N		I74F50729N	SOT27-1
14±pin plastic SO					N74F50729D		I74F50729D	SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS					DESCRIPTION		74F (U.L.) HIGH/	LOAD VALUE HIGH/
							LOW	LOW
D0, D1					Data inputs		1.0/0.417	20μA/250μA
CP0, CP1					Clock inputs (active rising edge)		1.0/1.0	20μA/20μA
SD0, SD1					Set inputs (active rising edge)		1.0/1.0	20μA/20μA
RD0, RD1					Reset inputs (active rising edge)		1.0/1.0	20μA/20μA
Q0, Q1,					Data outputs		750/33	15mA/20mA
	Q0, Q1

NOTE: One (1.0) FAST unit load is defined as: 20μA in the high state and 0.6mA in the low state.

1990 Sep 14

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853-1390 00420

Philips Semiconductors	Product specification

Synchronizing dual D-type flip-flop with edge-triggered

74F50729

set and reset and metastable immune characteristics

LOGIC SYMBOL												IEC/IEEE SYMBOL
												4				S	&	3
				2		12
														3
																	C1
												2
3				D0		D1										1D
		CP0																6
4
		SD0										1				R
1		RD0
11		CP1										10
10		SD1														S		9
13		RD1													11		C2
		Q0		Q0		Q1 Q1						12
																2D		8
		5		6		9		8				13				R
VCC = Pin 14
GND = Pin 7								SF00612										SF00613

METASTABLE IMMUNE CHARACTERISTICS

Philips Semiconductors uses the term `metastable immune' to describe characteristics of some of the products in its family. Specifically the 74F50XXX family presently consist of 4 products which will not glitch or display metastable immune characteristics. This term means that the outputs will not glitch or display an output anomaly under any circumstances including setup and hold time violations. This claim is easily verified on the 74F5074. By running two independent signal generators (see Fig. 1) at nearly the same frequency (in this case 10MHz clock and 10.02 MHz data) the device±under±test can be often be driven into metastable state. If the Q output is then used to trigger a digital scope set to infinite persistence the Q output will build a waveform. An experiment was run by continuously operating the devices in the region where metastability will occur.

When the device±under±test is a 74F74 (which was not designed with metastable immune characteristics) the waveform will appear as in Fig. 2.

Figure 2 shows clearly that the Q output can vary in time with respect to the Q trigger point. This also implies that the Q or Q output waveshapes may be distorted. This can be verified on an analog scope with a charge plate CRT. Perhaps of even greater interest are the dots running along the 3.5V volt line in the upper right hand quadrant. These show that the Q output did not change state even though the Q output glitched to at least 1.5 volt, the trigger point of the scope.

When the device±under±test is a metastable immune part, such as

the 74F5074, the waveform will appear as in Fig. 3. The 74F5074 Q output will appear as in Fig. 3. The 74F5074 Q output will not vary with respect to the Q trigger point even when the a part is driven into a metastable state. Any tendency towards internal metastability is resolved by Philips Semiconductors patented circuitry. If a metastable event occurs within the flop the only outward

manifestation of the event will be an increased clock±to±Q/Q propagation delay. This propagation delay is, of course, a function of the metastability characteristics of the part defined by τ and T0.

The metastability characteristics of the 74F5074 and related part types represent state±of±the±art TTL technology.

After determining the T0 and t of the flop, calculating the mean time between failures (MTBF) is simple. Suppose a designer wants to use the 74F50729 for synchronizing asynchronous data that is arriving at 10MHz (as measured by a frequency counter), has a clock frequency of 50MHz, and has decided that he would like to sample the output of the 74F50729 10 nanoseconds after the clock edge. He simply plugs his number into the equation below:

MTBF = e(t'/t)/ TofCfI

In this formula, fC is the frequency of the clock, fI is the average input event frequency, and t' is the time after the clock pulse that the output is sampled (t' < h, h being the normal propagation delay). In this situation the fI will be twice the data frequency of 20 MHz because input events consist of both of low and high transitions. Multiplying fI by fC gives an answer of 1015 Hz2. From Fig. 3. it is clear that the MTBF is greater than 1010 seconds. Using the above formula the actual MTBF is 1.51 X 1010 seconds or about 480 years.

SIGNAL GENERATOR		D	Q		TRIGGER

DIGITAL

SCOPE

SIGNAL GENERATOR		CP Q				INPUT

SF00586

Figure 1. Test Setup

1990 Sep 14

3

Philips Semiconductors	Product specification

Synchronizing dual D-type flip-flop with edge-triggered

74F50729

set and reset and metastable immune characteristics

COMPARISON OF METASTABLE IMMUNE AND NON±IMMUNE CHARACTERISTICS

4

3

2

1

0

Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive

SF00587

Figure 2. 74F74 Q output triggered by Q output, setup and hold times violated

3

2

1

0

Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive

SF00588

Figure 3. 74F74 Q output triggered by Q output, setup and hold times violated

1990 Sep 14

4