Philips N74F50728N, N74F50728D Datasheet

INTEGRATED CIRCUITS

74F50728

Synchronizing cascaded dual positive edge-triggered D-type flip-flop

Positive specification

1990 Sep 14

IC15 Data Handbook

m n r

Philips Semiconductors	Product specification

Synchronizing cascaded dual positive

74F50728

edge-triggered D-type flip-flop

FEATURES

•Metastable immune characteristics

•Output skew less than 1.5ns

•See 74F5074 for synchronizing dual D-type flip-flop

•See 74F50109 for synchronizing dual J±K positive edge-triggered flip-flop

•See 74F50729 for synchronizing dual dual D-type flip-flop with edge-triggered set and reset

•Industrial temperature range available (±40°C to +85°C)

Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive±going pulse. Following the hold time interval, data at the Dn input may be changed without affecting the levels of the output. Data entering the 74F50728 requires two clock cycles to arrive at the outputs.

The 74F50728 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74F50728 are: τ 135ps and T0 9.8 X 106 sec where τ represents a function of the rate at which a latch in a metastable state resolves that condition and To represents a function of the measurement of the propensity of a latch to enter a metastable state.

DESCRIPTION

The 74F50728 is a cascaded dual positive edge±triggered D±type featuring individual data, clock, set and reset inputs; also true and complementary outputs.

Set (SDn) and reset (RDn) are asynchronous active low inputs and operate independently of the clock (CPn) input. They set and reset both flip±flops of a cascaded pair simultaneously. Data must be stable just one setup time prior to the low±to±high transition of the clock for guaranteed propagation delays.

		TYPICAL SUPPLY
TYPE	TYPICAL fmax	CURRENT (TOTAL)
74F50728	145 MHz	23mA

ORDERING INFORMATION

								ORDER CODE
							COMMERCIAL RANGE		INDUSTRIAL RANGE
DESCRIPTION							VCC = 5V ±10%,		VCC = 5V ±10%,	PKG DWG #
							Tamb = 0°C to +70°C		Tamb = ±40°C to +85°C
14±pin plastic DIP							N74F50728N		I74F50728N	SOT27-1
14±pin plastic SO							N74F50728D		I74F50728D	SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
		PINS					DESCRIPTION		74F (U.L.) HIGH/	LOAD VALUE HIGH/
									LOW	LOW
		D0, D1					Data inputs		1.0/0.417	20μA/250μA
	CP0, CP1						Clock inputs (active rising edge)		1.0/1.0	20μA/20μA
							Set inputs (active low)		1.0/1.0	20μA/20μA
	SD0, SD1
							Reset inputs (active low)		1.0/1.0	20μA/20μA
	RD0, RD1
Q0, Q1,							Data outputs		50/33	1.0mA/20mA
			Q0, Q1

NOTE: One (1.0) FAST unit load is defined as: 20μA in the high state and 0.6mA in the low state.

September 14, 1990

2

853-1389 00421

Philips Semiconductors	Product specification

Synchronizing cascaded dual positive

74F50728

edge-triggered D-type flip-flop

PIN CONFIGURATION

									VCC
	RD0				1		14
		D0			2		13		RD1
									D1
CP0					3		12
					4		11	CP1
	SD0
		Q0
					5		10		SD1
		Q0			6		9	Q1
GND					7		8
									Q1
						SF00605

LOGIC DIAGRAM

4, 10

SDn
Dn	2, 12	D	Q	D	Q	5, 9	Qn
		CP	Q	CP	Q 6, 8		Q n

3, 11

CPn

1, 13

RDn

Vcc = Pin 14
GND = Pin 7	SF00608

NOTE: Data entering the flip±flop requires two clock cycles to arrive at the output.

LOGIC SYMBOL

2 12

D0 D1

3CP0

4 SD0

1 RD0

11	CP1
10	SD1
13	RD1

Q0 Q0 Q1 Q1

5 6 9 8

VCC = Pin 14

GND = Pin 7

SF00606

IEC/IEEE SYMBOL

	4	S	&
			3

3

C1

2 1D

6

1 R

10 S

9

11

C2

12 2D

8

13 R

SF00607

SYNCHRONIZING SOLUTIONS

Synchronizing incoming signals to a system clock has proven to be costly, either in terms of time delays or hardware. The reason for this is that in order to synchronize the signals a flip±flop must be used to ºcaptureº the incoming signal. While this is perhaps the only way to synchronize a signal, to this point, there have been problems with this method. Whenever the flop's setup or hold times are violated the flop can enter a metastable state causing the outputs in turn to glitch, oscillate, enter an intermediate state or change state in some abnormal fashion. Any of these conditions could be responsible for causing a system crash. To minimize this risk, flip±flops are often cascaded so that the input signal is captured on the first clock pulse and released on the second clock pulse (see Fig.1). This gives the first flop about one clock period minus the flop delay and minus the second flop's clock±to±Q setup time to resolve any metastable condition. This method greatly reduces the probability of the outputs of the synchronizing device displaying an abnormal state but the trade-off is that one clock cycle is lost to synchronize the incoming data and two separate flip±flops are required to produce the cascaded flop circuit. In order to assist the designer of synchronizing circuits Philips Semiconductors is offering the 74F50728.

D

Q

D

Q

Q OUTPUT

DATA

CLOCK

Q

Q

OUTPUT

CP

CP

Q

SF00609

Figure 1.

The 50728 consists of two pair of cascaded D±type flip±flops with metastable immune features and is pin compatible with the 74F74. Because the flops are cascaded on a single part the metastability

September 14, 1990

3

Philips Semiconductors	Product specification

Synchronizing cascaded dual positive

74F50728

edge-triggered D-type flip-flop

characteristics are greatly improved over using two separate flops that are cascaded. The pin compatibility with the 74F74 allows for plug±in retrofitting of previously designed systems.

Because the probability of failure of the 74F50728 is so remote, the metastability characteristics of the part were empirically determined based on the characteristics of its sister part, the 74F5074. The table below shows the 74F5074 metastability characteristics.

Having determined the T0 and τ of the flop, calculating the mean time between failures (MTBF) for the 74F50728 is simple. It is, however, somewhat different than calculating MTBF for a typical part because data requires two clock pulses to transit from the input to the output. Also, in this case a failure is considered of the output beyond the normal propagation delay.

Suppose a designer wants to use the flop for synchronizing asynchronous data that is arriving at 10MHz (as measured by a frequency counter), and is using a clock frequency of 50MHz. He simply plugs his number into the equation below:

MTBF = e(t'/t)/TofCfI

In this formula, fC is the frequency of the clock, fI is the average input event frequency, and t' is the period of the clock input (20 nanoseconds). In this situation the fI will be twice the data frequency of 20 MHz because input events consist of both of low and high data transitions. From Fig. 2 it is clear that the MTBF is greater than 1041 seconds. Using the above formula the actual MTBF is 2.23 X 1042 seconds or about 7 X 1034 years.

TYPICAL VALUES FOR τ AND T0 AT VARIOUS VCCS AND TEMPERATURES

		Tamb = 0°C		Tamb = 25°C		Tamb = 70°C
	τ	T0	τ	T0	τ	T0
VCC = 5.5V	125ps	1.0 X 109 sec	138ps	5.4 X 106 sec	160ps	1.7 X 105 sec
VCC = 5.0V	115ps	1.3 X 1010 sec	135ps	9.8 X 106 sec	167ps	3.9 X 104 sec
VCC = 4.5V	115ps	3.4 X 1013 sec	132ps	5.1 X 108 sec	175ps	7.3 X 104 sec

MEAN TIME BETWEEN FAILURES VERSUS DATA FREQUENCY AT VARIOUS CLOCK FREQUENCY

1070

Clock = 40MHz

1060

1050

Mean time

Clock = 50MHz

between failures

(seconds)

1040

Clock = 650MHz

1030

Clock = 70MHz

Clock = 80MHz

1020

1 billion years

Clock = 100MHz

1010

1000

1K

100K

10M

NOTE: V

= 5V, T = 25°C, τ =135ps, To = 9.8 X 108 sec

Data frequency (Hz)

SF00610

CC

amb

Figure 2.

September 14, 1990

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