INTEGRATED CIRCUITS
74F50109
Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics
Product specification |
1990 Sep 14 |
IC15 Data Handbook
m n r
Philips Semiconductors |
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Product specification |
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Synchronizing dual J±K positive edge-triggered
74F50109
flip-flop with metastable immune characteristics
FEATURE
•Metastable immune characteristics
•Output skew guaranteed less than 1.5ns
•High source current (IOH = 15mA) ideal for clock driver applications
•Pinout compatible with 74F109
•See 74F5074 for synchronizing dual D-type flip-flop
•See 74F50728 for synchronizing cascaded D-type flip-flop
•See 74F50729 for synchronizing dual D-type flip-flop with edge-triggered set and reset
TYPE |
TYPICAL fmax |
TYPICAL SUPPLY |
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CURRENT( TOTAL) |
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74F50109 |
150MHz |
22mA |
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ORDERING INFORMATION
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ORDER CODE |
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COMMERCIAL RANGE |
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DESCRIPTION |
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VCC = 5V ±10%, |
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PKG DWG # |
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Tamb = 0°C to +70°C |
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16±pin plastic DIP |
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N74F50109N |
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SOT38-4 |
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16±pin plastic SO |
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N74F50109D |
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SOT109-1 |
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INPUT AND OUTPUT LOADING |
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AND FAN OUT TABLE |
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74F (U.L.) |
LOAD |
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PINS |
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DESCRIPTION |
HIGH/ |
VALUE |
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LOW |
HIGH/LOW |
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J0, J1 |
J inputs |
1.0/0.417 |
20μA/250μA |
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K inputs |
1.0/0.417 |
20μA/250μA |
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K0, K1 |
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CP0, CP1 |
Clock inputs |
1.0/0.033 |
20μA/20μA |
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(active rising edge) |
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Set inputs |
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20μA/20μA |
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SD0, SD1 |
1.0/0.033 |
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(active low) |
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Reset inputs |
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20μA/20μA |
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RD0, RD1 |
1.0/0.033 |
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(active low) |
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Q0, Q1, |
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Data outputs |
750/33 |
15mA/20mA |
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Q0, Q1 |
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NOTE: One (1.0) FAST unit load is defined as: 20μA in the high state and 0.6mA in the low state.
PIN CONFIGURATION
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RD0 |
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1 |
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16 |
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VCC |
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J0 |
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2 |
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15 |
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RD1 |
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K0 |
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3 |
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14 |
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J1 |
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CP0 |
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4 |
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13 |
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K1 |
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5 |
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12 |
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CP1 |
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SD0 |
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Q0 |
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6 |
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11 |
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SD1 |
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Q1 |
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7 |
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10 |
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Q0 |
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GND |
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8 |
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9 |
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Q1 |
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SF00598 |
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LOGIC SYMBOL
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2 |
14 |
3 |
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13 |
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4 |
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CP0 |
J0 |
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J1 |
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K0 |
K1 |
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5 |
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SD0 |
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1 |
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RD0 |
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12 |
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CP1 |
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11 |
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SD1 |
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15 |
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RD1 |
Q0 |
Q0 |
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Q1 Q1 |
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6 |
7 |
10 |
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9 |
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VCC = Pin 16 |
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GND = Pin 8 |
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SF00599 |
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IEC/IEEE SYMBOL
2 |
1J |
6 |
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4 |
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C1 |
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3 |
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1K |
7 |
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1 |
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R |
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14 |
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2J |
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C2 |
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2K |
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15 |
R |
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SF00600
September 14, 1990 |
2 |
853-1388 00422 |
Philips Semiconductors |
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Product specification |
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Synchronizing dual J±K positive edge-triggered
74F50109
flip-flop with metastable immune characteristics
LOGIC DIAGRAM
Q |
7, 9 |
6, 10 |
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Q |
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K |
3, 13 |
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J |
2, 14 |
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CP |
4, 12 |
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SD |
5, 11 |
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RD |
1, 15 |
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VCC = Pin 16 |
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GND = Pin 8 |
SF00601 |
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DESCRIPTION |
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The 74F50109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs.
Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input.
The J and K are edge±triggered inputs which control the state changes of the flip±flops as described in the function table.
The J and K inputs must be stable just one setup time prior to the low±to±high transition of the clock for guaranteed propagation
delays. The JK design allows operation as a D flip±flop by tying J and K inputs together.
The 74F50109 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74F50109 are: τ 135ps and τ 9.8 X 106 sec where τ represents a function of the rate at which a latch in a metastable state resolves that condition and T0 represents a function of the measurement of the propensity of a latch to enter a metastable state.
device±under±test can be often be driven into a metastable state. If the Q output is then used to trigger a digital scope set to infinite persistence the Q output will build a waveform.0 An experiment was run by continuously operating the devices in the region where metastability will occur.
When the device±under±test is a 74F74 (which was not designed with metastable immune characteristics) the waveform will appear as in Fig. 2.
Fig. 2 shows clearly that the Q output can vary in time with respect to the Q trigger point. This also implies that the Q or Q output waveshapes may be distorted. This can be verified on an analog scope with a charge plate CRT. Perhaps of even greater interest are the dots running along the 3.5V volt line in the upper right hand quadrant. These show that the Q output did not change state even though the Q output glitched to at least 1.5 volts, the trigger point of the scope.
When the device±under±test is a metastable immune part, such as the 74F5074, the waveform will appear as in Fig. 3. The 74F5074 Q output will appear as in Fig. 3. The 74F5074 Q output will not vary with respect to the Q trigger point even when the a part is driven into a metastable state. Any tendency towards internal metastability is resolved by Philips Semiconductors patented circuitry. If a metastable event occurs within the flop the only outward manifestation of the event will be an increased clock±to±Q/Q propagation delay. This propagation delay is, of course, a function of the metastability characteristics of the part defined by τ and T0.
The metastability characteristics of the 74F5074 and related part types represent state±of±the±art TTL technology.
After determining the T0 and t of the flop, calculating the mean time between failures (MTBF) is simple. Suppose a designer wants to use the 74F50729 for synchronizing asynchronous data that is arriving at 10MHz (as measured by a frequency counter), has a clock frequency of 50MHz, and has decided that he would like to sample the output of the 74F50109 10 nanoseconds after the clock edge. He simply plugs his number into the equation below:
MTBF = e(t'/t)/ TofCfI
In this formula, fC is the frequency of the clock, fI is the average input event frequency, and t' is the time after the clock pulse that the output is sampled (t' < h, h being the normal propagation delay). In this situation the fI will be twice the data frequency of 20 MHz because input events consist of both of low and high transitions. Multiplying fI by fC gives an answer of 1015 Hz2. From Fig. 4 it is clear that the MTBF is greater than 1010 seconds. Using the above formula MTBF is 1.51 X 1010 seconds or about 480 years.
METASTABLE IMMUNE CHARACTERISTICS
Philips Semiconductors uses the term 'metastable immune' to describe characteristics of some of the products in its FAST family.
Specifically the 74F50XXX family presently consist of 4 products which displays metastable immune characteristics. This term means that the outputs will not glitch or display an output anomaly under any circumstances including setup and hold time violations.
This claim is easily verified on the 74F5074. By running two independent signal generators (see Fig. 1) at nearly the same frequency (in this case 10MHz clock and 10.02 MHz data) the
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SIGNAL GENERATOR |
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D |
Q |
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TRIGGER |
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DIGITAL |
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SCOPE |
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SIGNAL GENERATOR |
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CP |
Q |
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INPUT |
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SF00586 |
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Figure 1. |
Test setup |
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September 14, 1990 |
3 |
Philips Semiconductors |
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Product specification |
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Synchronizing dual J±K positive edge-triggered
74F50109
flip-flop with metastable immune characteristics
COMPARISON OF METASTABLE IMMUNE AND NON±IMMUNE CHARACTERISTICS
4
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
SF00602
Figure 2. 74F74 Q output triggered by Q output, Setup and Hold times violated
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2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
SF00588
Figure 3. 74F74 Q output triggered by Q output, Setup and Hold times violated
September 14, 1990 |
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