INTEGRATED CIRCUITS
74F379A
Quad register
Product specification |
1996 Mar 12 |
IC15 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Quad register |
74F379A |
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FEATURES
•Edge±triggered D±type inputs
•Buffered positive edge±triggered clock
•Buffered common enable input
•True and complementary outputs
•Offers light loading PNP inputs (IIL = ±20μA)
DESCRIPTION
The 74F379A is a 4±bit register with buffered common enable (E). This device is similar to the 74F175A but features the common enable rather than common master reset.
TYPE |
TYPICAL fmax |
TYPICAL SUPPLY CURRENT (TOTAL) |
74F379A |
200MHz |
29mA |
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ORDERING INFORMATION
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ORDER CODE |
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DESCRIPTION |
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COMMERCIAL RANGE |
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PKG, DWG. # |
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VCC = 5V ±10%, Tamb = 0°C to +70°C |
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16±pin plastic DIP |
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N74F379AN |
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SOT38±4 |
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16±pin plastic SO |
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N74F379AD |
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SOT109±1 |
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INPUT AND OUTPUT LOADING AND FAN OUT TABLE |
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TYPE |
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PINS |
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DESCRIPTION |
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74F (U.L.) HIGH/ |
LOAD VALUE |
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LOW |
HIGH/LOW |
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D0 ± D3 |
Data inputs |
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1.0/0.033 |
20μA/20μA |
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74F379A |
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CP |
Clock pulse input (active rising edge) |
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1.0/0.033 |
20μA/20μA |
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Enable input (active low) |
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1.0/0.033 |
20μA/20μA |
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E |
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Q0 ± Q3 |
True outputs |
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50/33 |
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1.0mA/20mA |
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Complementary outputs |
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50/33 |
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15mA/20mA |
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Q0 ± Q3 |
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Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20μA in the high state and 0.6mA in the low state.
PIN CONFIGURATION |
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LOGIC SYMBOL |
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VCC |
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4 |
5 |
12 |
13 |
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E |
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1 |
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16 |
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Q0 |
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Q3 |
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2 |
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15 |
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D0 |
D1 |
D2 |
D3 |
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Q0 |
3 |
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14 |
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Q3 |
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D0 |
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D3 |
9 |
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CP |
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4 |
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13 |
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1 |
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E |
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D1 |
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D2 |
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5 |
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12 |
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Q0 Q0 |
Q1 Q1 Q2 |
Q2 Q3 |
Q3 |
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Q1 |
6 |
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11 |
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Q2 |
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Q1 |
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Q2 |
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7 |
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10 |
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3 |
2 |
6 |
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7 |
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11 |
10 |
14 |
15 |
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GND |
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CP |
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8 |
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9 |
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VCC = Pin 16 |
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SF00354 |
GND = Pin 8 |
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SF00355 |
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1996 Mar 12 |
2 |
853-0027 16555 |
Philips Semiconductors |
Product specification |
|
|
|
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Quad register |
74F379A |
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IEC/IEEE SYMBOL |
FUNCTION TABLE |
1 |
G1 |
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9 |
1C2 |
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4 |
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2 |
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2D |
3 |
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5 |
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7 |
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6 |
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12 |
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10 |
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11 |
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13 |
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15 |
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14 |
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SF00356 |
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INPUTS |
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OUTPUTS |
OUTPUT |
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CP |
Dn |
Qn |
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E |
Qn |
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H |
↑ |
X |
NC |
NC |
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L |
↑ |
h |
H |
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L |
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L |
↑ |
l |
L |
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H |
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Notes to function table
H = High±voltage level
h= High state must be present one setup time before the low±to±high clock transition
L = Low±voltage level
l= Low state must be present one setup time before the low±to±high clock transition
NC= |
No change |
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X |
= |
Don't care |
↑ |
= |
Low±to±high clock transition |
LOGIC DIAGRAM
D0 |
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D1 |
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D2 |
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D3 |
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4 |
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5 |
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12 |
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13 |
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9 |
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CP |
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D |
Q |
D Q |
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D Q |
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D |
Q |
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CP |
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CP |
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CP |
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CP Q |
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E |
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E |
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E |
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E |
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1 |
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E |
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3 |
2 |
6 |
7 |
11 |
10 |
14 |
15 |
VCC = Pin 16 |
Q0 |
Q0 |
Q1 |
Q1 |
Q2 Q2 |
Q3 Q3 |
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GND = Pin 8 |
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SF00357 |
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1996 Mar 12 |
3 |
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