INTEGRATED CIRCUITS
74F378
Hex D flip-flop with enable
Product specification |
1989 Oct 05 |
IC15 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Hex D flip-flop with enable |
74F378 |
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FEATURES
•6-bit high-speed parallel register
•Positive edge-triggered D-type inputs
•Fully buffered common Clock and Enable inputs
•Input clamp diodes limit high speed termination effects
•Fully TTL and CMOS compatible
DESCRIPTION
The 74F378 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low.
The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transformed to the corresponding flop-flop's Q output. The E input must be stable one setup time prior to the Low-to-High clock transition for predictable operation.
PIN CONFIGURATION
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E |
1 |
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16 |
VCC |
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Q0 |
2 |
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15 |
Q5 |
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D0 |
3 |
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14 |
D5 |
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D1 |
4 |
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13 |
D4 |
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Q1 |
5 |
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12 |
Q4 |
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D2 |
6 |
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11 |
D3 |
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Q2 |
7 |
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10 |
Q3 |
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GND |
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8 |
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9 |
CP |
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SF00927 |
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TYPE |
TYPICAL fmax |
TYPICAL SUPPLY |
CURRENT (TOTAL) |
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74F378 |
100MHz |
35mA |
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ORDERING INFORMATION
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COMMERCIAL |
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DESCRIPTION |
RANGE |
PKG DWG # |
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VCC = 5V ±10%, |
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Tamb = 0°C to +70°C |
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16±pin plastic DIP |
N74F378N |
SOT38-4 |
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16±pin plastic SO |
N74F378D |
SOT109-1 |
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INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS |
DESCRIPTION |
74F (U.L.) |
LOAD VALUE |
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HIGH/LOW |
HIGH/LOW |
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D0 ± D5 |
Data inputs |
1.0/1.0 |
20μA/0.6mA |
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CP |
Clock pulse input (active rising edge) |
1.0/1.0 |
20μA/0.6mA |
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Enable input (active low) |
1.0/1.0 |
20μA/0.6mA |
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E |
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Q0 ± Q5 |
Data outputs |
50/33 |
1.0mA/20mA |
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NOTE:
One (1.0) FAST unit load is defined as: 20μA in the High state and 0.6mA in the Low state.
1989 Oct 05 |
2 |
853±0067 97804 |
Philips Semiconductors |
Product specification |
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Hex D flip-flop with enable |
74F378 |
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LOGIC SYMBOL |
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IEC/IEEE SYMBOL |
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3 |
4 |
6 |
11 |
13 |
14 |
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1 |
G1 |
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9 |
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1C2 |
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D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
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2D |
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9 |
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4 |
5 |
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CP |
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1 |
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E |
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6 |
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7 |
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Q0 |
Q1 Q2 |
Q3 Q4 |
Q5 |
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11 |
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10 |
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13 |
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12 |
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2 |
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5 |
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7 |
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10 |
12 |
15 |
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14 |
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15 |
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VCC = Pin 16 |
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SF00916 |
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GND = Pin 8 |
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SF00917 |
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LOGIC DIAGRAM
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D0 |
D1 |
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D2 |
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D3 |
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D4 |
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D5 |
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3 |
4 |
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6 |
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11 |
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13 |
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14 |
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E |
1 |
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D |
Q |
D |
Q |
D |
Q |
D |
Q |
D |
Q |
D |
Q |
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CP |
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CP |
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CP |
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CP |
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CP |
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CP |
CP |
9 |
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2 |
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5 |
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7 |
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10 |
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12 |
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15 |
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Q0 |
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Q1 |
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Q2 |
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Q3 |
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Q4 |
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Q5 |
VCC = Pin 16 |
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GND = Pin 8 |
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SF00918 |
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FUNCTION TABLE
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INPUTS |
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OUTPUTS |
OPERATING |
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CP |
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Dn |
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Qn |
MODE |
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E |
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l |
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↑ |
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h |
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H |
Load ª1º |
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l |
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↑ |
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l |
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L |
Load ª0º |
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h |
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↑ |
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X |
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no change |
Hold (do nothing) |
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H |
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X |
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X |
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no change |
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H |
= |
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High-voltage level |
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h |
= |
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High-voltage level one setup time |
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prior to the Low-to-High clock transition |
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L |
= |
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Low-voltage level |
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l |
= |
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Low-voltage level one setup time |
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prior to the Low-to-High clock transition |
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X |
= |
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Don't care |
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↑ |
= |
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Low-to-High clock transition |
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1989 Oct 05 |
3 |
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