Philips N74F299N, N74F299DB Datasheet

INTEGRATED CIRCUITS

74F299

8-bit universal shift/storage register (3-State)

Product specification

1990 Mar 01

IC15 Data Handbook

m n r

Philips Semiconductors	Product specification
8-bit universal shift/storage register (3-State)	74F299

FEATURES

•Common parallel I/O for reduced pin count

•Additional serial inputs and outputs for expansion

•Four operating modes: Shift left, shift right, load and store

•3-State outputs for bus-oriented applications

DESCRIPTION

The 74F299 is an 8-bit universal shift/storage register with 3-State outputs. Four modes of operation are possible: Hold (store), shift left, shift right and parallel load. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins.

Additional outputs are provided for flip-flops Q0 and Q7 to allow easy serial cascading. A separate active-Low Master Reset is used to reset the register.

The 74F299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Function Table. All flip-flop outputs are brought out through 3-State buffers to separate

I/O pins that also serve as data inputs in the parallel load mode.

Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words.

PIN CONFIGURATION

	S0			1				20	VCC
									S1
OE0				2				19
									DS7
OE1				3				18
I/O6									Q7
				4				17
I/O4									I/O7
				5				16
I/O2									I/O5
				6				15
I/O0									I/O3
				7				14
	Q0								I/O1
				8				13
									CP
	MR			9				12
GND									DS0
				10				11

		SF00865
			TYPICAL
TYPE	TYPICAL fMAX		SUPPLY CURRENT
			(TOTAL)
74F299	115MHz		58mA

A Low signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of clock are observed.

A High signal on either OE0 or OE1 disables the 3-State buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-State buffers are also disabled by High signals on both S0 and S1 in preparation for a parallel load operation.

ORDERING INFORMATION

	ORDER CODE
DESCRIPTION	COMMERCIAL	PKG DWG #
	RANGE
	VCC = 5V ±10%,
	Tamb = 0°C to +70°C
20-pin plastic DIP	N74F299N	SOT146-1
20-pin plastic SOL	N74F299D	SOT163-1
20-pin plastic SSOP II	N74F299DB	SOT339-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

	PINS					DESCRIPTION	74F(U.L.)	LOAD VALUE
							HIGH/LOW	HIGH/LOW
	DS0					Serial data input for right shift	1.0/1.0	20μA/0.6mA
	DS7					Serial data input for left shift	1.0/1.0	20μA/0.6mA
	S0, S1					Mode select inputs	1.0/2.0	20μA/1.2mA
	CP					Clock pulse input (Active rising edge)	1.0/1.0	20μA/0.6mA
						Asynchronous Master Reset input (Active Low)	1.0/1.0	20μA/0.6mA
	MR
						Output Enable input (Active Low)	1.0/1.0	20μA/0.6mA
	OE0, OE1
	Q0, Q7					Serial outputs	50/33	1.0mA/20mA
	I/On					Multiplexed parallel data inputs or	3.5/1.0	70μA/0.6mA
						3-State parallel outputs	150/40	3.0mA/24mA

NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20μA in the High State and 0.6mA in the Low state.

1990 Mar 01

2

853-0365 98989

Philips Semiconductors	Product specification
8-bit universal shift/storage register (3-State)	74F299

LOGIC SYMBOL

LOGIC SYMBOL (IEEE/IEC)

11

18

9

SRG8

4R

2

&

DS0

DS7

3

3EN13

1

S0

1

0

M

0

S1

19

19

1

3

12

CP

12

C4/1→ /2←

9

MR

11

8

2

OE0

1, 4D

7

3

OE1

3, 4D

13

5, 13

Z5

Q0

I/00

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

Q7

3, 4D

6

6, 13

Z6

8

7

13

6

14

5

15

4

16

17

VCC = Pin 20

14

GND = Pin 10

SF00866

5

15

4

16

3, 4D

18

12, 13

Z12

17

2, 4D

FUNCTION TABLE

SF00890

INPUTS

INPUTS

OPERATING MODE

OEn

MR

S1

S0

CP

L

L

X

X

X

Asynchronous Reset; Q0 - Q7 = Low

L

H

H

H

↑

Parallel load; I/On → Qn (I/On outputs disabled)

L

H

L

H

↑

Shift right; DS0 → Q0, Q0 → Q1, etc.

L

H

H

L

↑

Shift left; DS7 → Q7, Q7 → Q6, etc.

L

H

L

L

X

Hold

H

X

X

X

X

Outputs in High Z

H

=

High voltage level

L

=

Low voltage level

X

=

Don't care

↑

=

Low-to-High clock transition

1990 Mar 01

3

Philips Semiconductors	Product specification
8-bit universal shift/storage register (3-State)	74F299

LOGIC DIAGRAM

	DS7	18
	OE0	2			17	Q7
	OE1	3	CP
		19	D	Q	16	I/O7
	S1
				RD
		1
	S0
			CP
			D	Q	4	I/O6
				RD
			CP
			D	Q	15	I/O5
				RD
			CP
			D	Q	5	I/O4
				RD
			CP
			D	Q	14	I/O3
				RD
			CP
			D	Q	6	I/O2
				RD
			CP
			D	Q	13	I/O1
				RD
			CP
			D	Q	7	I/O0
		11		RD
	DS0
	CP	12			8	Q0
VCC = Pin 20	MR	9
GND = Pin 10					SF00868
1990 Mar 01			4

Philips Semiconductors	Product specification
8-bit universal shift/storage register (3-State)	74F299

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)

	SYMBOL	PARAMETER		RATING	UNIT
	VCC	Supply voltage		±0.5 to +7.0	V
	VIN	Input voltage		±0.5 to +7.0	V
	IIN	Input current		±30 to +5	mA
	VOUT	Voltage applied to output in High output state		±0.5 to +VCC	V
	IOUT	Current applied to output in Low output state	Q0, Q7	40	mA
			I/On	48	mA
	Tamb	Operating free-air temperature range		0 to +70	°C
	Tstg	Storage temperature		±65 to +150	°C

RECOMMENDED OPERATING CONDITIONS

SYMBOL	PARAMETER			LIMITS		UNIT
			MIN	NOM	MAX
VCC	Supply voltage		4.5	5.0	5.5	V
VIH	High-level input voltage		2.0			V
VIL	Low-level input voltage				0.8	V
IIK	Input clamp current				±18	mA
IOH	High-level output current	Q0, Q7			±1	mA
		I/On			±3	mA
IOL	Low-level output current	Q0, Q7			20	mA
		I/On			24	mA
Tamb	Operating free-air temperature range		0		70	°C

1990 Mar 01

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