INTEGRATED CIRCUITS
74F259
Latch
Product specification |
1989 Apr 11 |
IC15 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Latch |
74F259 |
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FEATURES
•Combines demultiplexer and 8-bit latch
•Serial-to-parallel capability
•Output from each storage bit available
•Random (addressable) data entry
•Easily expandable
•Common reset input
•Useful as 1-of-8 active-High decoder
DESCRIPTION
The 74F259 addressable latch has four distinct modes of operation which are selectable by controlling the Master Reset (MR) and Enable (E) inputs (see Function Table). In the addressable latch mode, data at the Data inputs is written into the addressed latches.
The addressed latches will follow the Data input with all unaddressed latches remaining in their previous states. In the store mode, all latches remain in their previous states and are unaffected by the Data or Address inputs. To eliminate the possibility of entering erroneous data in the latches, the enable should be held High (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode (MR=E=Low), addressed outputs will follow the level of the Data input, with all other outputs Low. In the Master Reset mode, all outputs are Low and unaffected by the Address and Data inputs.
PIN CONFIGURATION
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A0 |
1 |
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16 |
VCC |
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A1 |
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15 |
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MR |
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A2 |
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E |
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Q0 |
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D |
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Q1 |
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Q7 |
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Q2 |
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Q6 |
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Q3 |
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Q5 |
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GND |
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8 |
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9 |
Q4 |
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SF00823 |
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TYPE |
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TYPICAL |
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TYPICAL SUPPLY |
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PROPAGATION |
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CURRENT (TOTAL) |
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DELAY |
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74F259 |
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7.5ns |
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31mA |
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ORDERING INFORMATION |
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ORDER CODE |
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DESCRIPTION |
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COMMERCIAL RANGE |
PKG DWG # |
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VCC = 5V ±10%, |
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Tamb = 0°C to +70°C |
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16-pin plastic DIP |
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N74F259N |
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SOT38-4 |
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16-pin plastic SO |
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N74F259D |
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SOT109-1 |
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INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS |
DESCRIPTION |
74F (U.L.) |
LOAD VALUE |
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HIGH/LOW |
HIGH/LOW |
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D |
Data input |
1.0/1.0 |
20μA/0.6mA |
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A0, A1, A2 |
Address inputs |
1.0/1.0 |
20μA/0.6mA |
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Enable input (active Low) |
1.0/1.0 |
20μA/0.6mA |
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E |
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Master Reset inputs (active Low) |
1.0/1.0 |
20μA/0.6mA |
MR |
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Q0 ± Q7 |
Data outputs |
50/33 |
1.0mA/20mA |
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NOTE:
One (1.0) FAST unit load is defined as: 20μA in the High state and 0.6mA in the Low state.
1989 Apr 11 |
2 |
853±0362 06316 |
Philips Semiconductors |
Product specification |
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Latch |
74F259 |
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LOGIC SYMBOL |
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IEC/IEEE SYMBOL |
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1 |
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8M |
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G8 |
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Z9 |
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15 |
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Z10 |
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D |
A0 |
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A1 |
A3 |
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14 |
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E |
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9, 10D |
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4 |
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10m 0R |
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9, 10D |
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5 |
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10m |
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15 |
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MR |
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1R |
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9, 10D |
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6 |
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Q0 |
Q1 |
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Q2 |
Q3 |
Q4 |
Q5 |
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Q6 |
Q7 |
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10m |
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2R |
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9, 10D |
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7 |
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10m |
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3R |
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4 |
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9, 10D |
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9 |
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10m |
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4R |
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9, 10D |
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10 |
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10m |
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5R |
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9, 10D |
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11 |
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10m |
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6R |
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VCC = Pin 16 |
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9, 10D |
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12 |
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10m |
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7R |
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GND = Pin 8 |
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SF00824 |
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SF00825 |
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FUNCTION TABLE |
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INPUTS |
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OUTPUTS |
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OPERATING MODE |
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D |
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A0 |
A1 |
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A2 |
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Q0 |
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Q1 |
Q2 |
Q3 |
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Q4 |
Q5 |
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Q6 |
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Q7 |
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MR |
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E |
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L |
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H |
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X |
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X |
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X |
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L |
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L |
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L |
L |
L |
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L |
L |
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L |
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L |
Master Reset |
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L |
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L |
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d |
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L |
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L |
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L |
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Q=d |
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L |
L |
L |
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L |
L |
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L |
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L |
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L |
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L |
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d |
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H |
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L |
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L |
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L |
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Q=d |
L |
L |
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L |
L |
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L |
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L |
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L |
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L |
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d |
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L |
H |
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L |
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L |
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L |
Q=d |
L |
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L |
L |
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L |
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L |
Demultiplex |
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• |
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• |
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• |
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• |
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• |
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• |
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• |
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• |
• |
• |
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• |
• |
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• |
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• |
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(active-High decoder |
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• |
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• |
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• |
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• |
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• |
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• |
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• |
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• |
• |
• |
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• |
• |
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• |
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• |
when D=H) |
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• |
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• |
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• |
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• |
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• |
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• |
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• |
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• |
• |
• |
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• |
• |
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• |
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• |
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L |
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L |
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d |
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H |
H |
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H |
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L |
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L |
L |
L |
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L |
L |
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L |
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Q=d |
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H |
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H |
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X |
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X |
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X |
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X |
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q0 |
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q1 |
q2 |
q3 |
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q4 |
q5 |
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q6 |
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q7 |
Store (do nothing) |
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H |
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L |
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d |
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L |
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L |
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L |
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Q=d |
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q1 |
q2 |
q3 |
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q4 |
q5 |
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q6 |
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q7 |
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H |
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L |
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d |
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H |
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L |
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L |
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q0 |
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Q=d |
q2 |
q3 |
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q4 |
q5 |
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q6 |
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q7 |
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H |
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L |
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d |
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L |
H |
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L |
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q0 |
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q1 |
Q=d |
q3 |
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q4 |
q5 |
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q6 |
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q7 |
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• |
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• |
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• |
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• |
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• |
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• |
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• |
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• |
• |
• |
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• |
• |
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• |
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• |
Addressable Latch |
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• |
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• |
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• |
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• |
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• |
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• |
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• |
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• |
• |
• |
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• |
• |
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• |
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• |
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• |
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• |
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• |
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• |
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• |
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• |
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• |
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• |
• |
• |
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• |
• |
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• |
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• |
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H |
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L |
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d |
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H |
H |
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H |
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q0 |
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q1 |
q2 |
q3 |
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q4 |
q5 |
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q6 |
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Q=d |
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H |
= |
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High voltage level |
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L |
= |
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Low voltage level |
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X |
= |
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Don't care |
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d |
= |
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High or Low data one setup time prior to the Low-to-High Enable transition |
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q |
= |
|
Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared. |
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1989 Apr 11 |
3 |
Philips Semiconductors |
Product specification |
|
|
|
|
Latch |
74F259 |
|
|
|
|
LOGIC DIAGRAM
|
|
12 |
Q7 |
|
|
|
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11 |
Q6 |
|
|
|
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10 |
Q5 |
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9 |
Q4 |
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7 |
Q3 |
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6 |
Q2 |
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D |
13 |
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E |
14 |
|
|
|
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|
MR |
15 |
5 |
|
|
Q1 |
||
|
|
|
|
A2 |
3 |
|
|
A1 |
2 |
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|
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|
A0 |
1 |
4 |
Q0 |
|
|
||
VCC = Pin 16 |
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|
|
GND = Pin 8 |
|
SF00826 |
|
|
|
||
1989 Apr 11 |
4 |
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