Philips N74F259N, N74F259D Datasheet
INTEGRATED CIRCUITS
74F259
Latch
Product specification
IC15 Data Handbook
1989 Apr 11
Philips Semiconductors Product specification
74F259Latch
FEA TURES
•Combines demultiplexer and 8-bit latch
•Serial-to-parallel capability
•Output from each storage bit available
•Random (addressable) data entry
•Easily expandable
•Common reset input
•Useful as 1-of-8 active-High decoder
DESCRIPTION
The 74F259 addressable latch has four distinct modes of operation
which are selectable by controlling the Master Reset (MR
Enable (E
) inputs (see Function Table). In the addressable latch
mode, data at the Data inputs is written into the addressed latches.
The addressed latches will follow the Data input with all
unaddressed latches remaining in their previous states. In the store
mode, all latches remain in their previous states and are unaffected
by the Data or Address inputs. To eliminate the possibility of entering
erroneous data in the latches, the enable should be held High
(inactive) while the address lines are changing. In the 1-of-8
decoding or demultiplexing mode (MR
=E=Low), addressed outputs
will follow the level of the Data input, with all other outputs Low. In
the Master Reset mode, all outputs are Low and unaffected by the
Address and Data inputs.
) and
PIN CONFIGURATION
1
A0
2
A1
3
A2
4
Q0
5
Q1
6
Q2
Q3
GND
TYPE TYPICAL
PROPAGATION
DELAY
74F259 7.5ns 31mA
16
V
CC
15
MR
14
E
13
D
12
Q7
11
Q6
107
Q5
98
Q4
SF00823
TYPICAL SUPPL Y
CURRENT (TOTAL)
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
VCC = 5V ±10%,
T
= 0°C to +70°C
amb
16-pin plastic DIP N74F259N SOT38-4
16-pin plastic SO N74F259D SOT109-1
PKG DWG #
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION 74F (U.L.)
HIGH/LOW
D Data input 1.0/1.0 20µA/0.6mA
A0, A1, A2 Address inputs 1.0/1.0 20µA/0.6mA
E Enable input (active Low) 1.0/1.0 20µA/0.6mA
MR Master Reset inputs (active Low) 1.0/1.0 20µA/0.6mA
Q0 – Q7 Data outputs 50/33 1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOAD VALUE
HIGH/LOW
1989 Apr 11 853–0362 06316
2
Philips Semiconductors Product specification
OPERATING MODE
Demulti lex
H)
74F259Latch
LOGIC SYMBOL
E
14
MR
15
VCC = Pin 16
GND = Pin 8
13 3
1
DA3
A02A1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
45679101112
SF00824
IEC/IEEE SYMBOL
1
2
3
14
13
15
0
2
G8
Z9
Z10
9, 10D
10m 0
9, 10D
10m 1
9, 10D
10m 2
9, 10D
10m 3
9, 10D
10m 4
9, 10D
10m 5
9, 10D
10m 6R
9, 10D
10m 7
8M
0
7
R
R
R
R
R
R
R
4
5
6
7
9
10
11
12
SF00825
FUNCTION TABLE
INPUTS OUTPUTS
MR E D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
L H X X X L L L L L L L L L Master Reset
L L d L L L Q=d L L L L L L L
L L d H L L L Q=d L L L L L L
L L d L H L L L Q=d L L L L L
• • • • • • • • • • • • • •
• • • • • • • • • • • • • •
• • • • • • • • • • • • • •
L L d H H H L L L L L L L Q=d
H H X X X X q0 q1 q2 q3 q4 q5 q6 q7 Store (do nothing)
H L d L L L Q=d q1 q2 q3 q4 q5 q6 q7
H L d H L L q0 Q=d q2 q3 q4 q5 q6 q7
H L d L H L q0 q1 Q=d q3 q4 q5 q6 q7
• • • • • • • • • • • • • •
• • • • • • • • • • • • • •
• • • • • • • • • • • • • •
H L d H H H q0 q1 q2 q3 q4 q5 q6 Q=d
H = High voltage level
L = Low voltage level
X = Don’t care
d = High or Low data one setup time prior to the Low-to-High Enable transition
q = Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared.
p
(active-High decoder
when D=
Addressable Latch
1989 Apr 11
3
Philips Semiconductors Product specification
74F259Latch
LOGIC DIAGRAM
12
Q7
11
Q6
MR
10
Q5
9
Q4
7
Q3
6
Q2
13
D
14
E
15
5
Q1
VCC = Pin 16
GND = Pin 8
1989 Apr 11
3
A2
2
A1
1
A0
4
SF00826
Q0
4
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