Philips N74ALS74AD, N74ALS74ADB, N74ALS74AN Datasheet
74ALS74A
Dual D-type flip-flop with set and reset
Product specification 1996 Jul 01
INTEGRATED CIRCUITS
IC05 Data Handbook
Philips Semiconductors Product specification
74ALS74ADual D-type flip-flop with set and reset
2
1996 Jul 01 853–1278 01670
DESCRIPTION
The 74ALS74 is a dual positive edge-triggered D-type flip-flop
featuring individual data, clock, set, and reset inputs; also true and
complementary outputs. Set (S
D) and reset (RD) are asynchronous
active-Low inputs and operate independently of the clock input.
When set and reset are inactive (High), data at the D input is
transferred to the Q and Q
outputs on the Low-to-High transition of
the clock. Data must be stable just one setup time prior to the
Low-to-High transition of the clock for predictable operation. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. Following the hold time
interval, data at the D input may be changed without affecting the
levels of the output.
TYPE
TYPICAL f
MAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74ALS74A 150MHz 3.0mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
V
CC
= 5V ±10%,
T
amb
= 0°C to +70°C
DRAWING
NUMBER
14-pin plastic DIP 74ALS74AN SOT27-1
14-pin plastic SO 74ALS74AD SOT108-1
14-pin plastic SSOP
Type II
74ALS74ADB SOT337-1
PIN CONFIGURATION
14
13
12
11
10
9
87
6
5
4
3
2
1
GND
V
CC
SD1
Q1
Q1
CP1
R
D1
D1
R
D0
D0
Q
0
CP0
S
D0
Q0
SF00045
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0, D1 Data inputs 1.0/2.0 20µA/0.2mA
CP0, CP1 Clock inputs (active rising edge) 1.0/2.0 20µA/0.2mA
SD0, SD1 Set inputs (active-Low) 2.0/4.0 40µA/0.4mA
RD0, RD1 Reset inputs (active-Low) 2.0/4.0 40µA/0.4mA
Q0, Q1, Q0, Q1 Data outputs 20/80 0.4mA/8mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
Q0 Q0 Q1 Q1
56 98
VCC = Pin 14
GND = Pin 7
3
4
1
11
10
13
CP0
SD0
RD0
CP1
SD1
RD1
D0 D1
212
SF00046
IEC/IEEE SYMBOL
4
3
2
1
10
11
12
13
5
6
9
8
&
S
S
C1
C2
R
1D
2D
R
SF00047
Philips Semiconductors Product specification
74ALS74ADual D-type flip-flop with set and reset
1996 Jul 01
3
LOGIC DIAGRAM
VCC = Pin 14
GND = Pin 7
5, 9
6, 8
Q
Q
4, 10
1, 13
3, 11
2, 12
S
D
R
D
CP
D
SF00048
FUNCTION TABLE
INPUTS OUTPUTS OPERATING
SD RD CP D Q Q MODE
L H X X H L Asynchronous set
H L X X L H Asynchronous reset
L L X X H H Undetermined*
H H ↑ h H L Load “1”
H H ↑ l L H Load “0”
H H ↑ X NC NC Hold
H = High voltage level
h = High state must be present one setup time prior to
Low-to-High clock transition
L = Low voltage level
l = Low state must be present one setup time prior to
Low-to-High clock transition
NC= No change from the previous setup
X = Don’t care
↑ = Low-to-High clock transition
↑
= Not Low-to-High clock transition
* = Both outputs will be High while both S
D and RD are Low,
but the output states are unpredictable if S
D and RD go
High simultaneously
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER RATING UNIT
V
CC
Supply voltage –0.5 to +7.0 V
V
IN
Input voltage –0.5 to +7.0 V
I
IN
Input current –30 to +5 mA
V
OUT
Voltage applied to output in High output state –0.5 to V
CC
V
I
OUT
Current applied to output in Low output state 16 mA
T
amb
Operating free-air temperature range 0 to +70 °C
T
stg
Storage temperature range –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5.0 5.5 V
V
IH
High-level input voltage 2.0 V
V
IL
Low-level input voltage 0.8 V
I
Ik
Input clamp current –18 mA
I
OH
High-level output current –0.4 mA
I
OL
Low-level output current
8 mA
T
amb
Operating free-air temperature range 0 +70 °C
Loading...