INTEGRATED CIRCUITS
74ALS74A
Dual D-type flip-flop with set and reset
Product specification |
1996 Jul 01 |
IC05 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Dual D-type flip-flop with set and reset |
74ALS74A |
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DESCRIPTION
The 74ALS74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock input. When set and reset are inactive (High), data at the D input is transferred to the Q and Q outputs on the Low-to-High transition of the clock. Data must be stable just one setup time prior to the Low-to-High transition of the clock for predictable operation. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be changed without affecting the levels of the output.
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TYPICAL |
TYPE |
TYPICAL fMAX |
SUPPLY CURRENT |
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(TOTAL) |
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74ALS74A |
150MHz |
3.0mA |
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ORDERING INFORMATION
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ORDER CODE |
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DRAWING |
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DESCRIPTION |
COMMERCIAL RANGE |
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VCC = 5V ±10%, |
NUMBER |
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Tamb = 0°C to +70°C |
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14-pin plastic DIP |
74ALS74AN |
SOT27-1 |
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14-pin plastic SO |
74ALS74AD |
SOT108-1 |
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14-pin plastic SSOP |
74ALS74ADB |
SOT337-1 |
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Type II |
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PIN CONFIGURATION
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RD0 |
1 |
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14 |
VCC |
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D0 |
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2 |
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13 |
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RD1 |
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CP0 |
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D1 |
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3 |
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12 |
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CP1 |
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SD0 |
4 |
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11 |
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Q0 |
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5 |
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10 |
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SD1 |
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Q1 |
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Q0 |
6 |
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9 |
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GND |
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7 |
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8 |
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Q1 |
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SF00045 |
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
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PINS |
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DESCRIPTION |
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74ALS (U.L.) |
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LOAD VALUE |
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HIGH/LOW |
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HIGH/LOW |
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D0, D1 |
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Data inputs |
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1.0/2.0 |
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20μA/0.2mA |
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CP0, CP1 |
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Clock inputs (active rising edge) |
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1.0/2.0 |
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20μA/0.2mA |
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Set inputs (active-Low) |
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2.0/4.0 |
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40μA/0.4mA |
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SD0, SD1 |
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Reset inputs (active-Low) |
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2.0/4.0 |
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40μA/0.4mA |
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RD0, RD1 |
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Q0, Q1, |
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Data outputs |
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20/80 |
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0.4mA/8mA |
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Q0, Q1 |
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NOTE: One (1.0) ALS unit load is defined as: 20μA in the High state and 0.1mA in the Low state. |
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LOGIC SYMBOL |
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IEC/IEEE SYMBOL |
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2 |
12 |
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4 |
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S |
& |
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5 |
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3 |
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CP0 |
D0 |
D1 |
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3 |
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C1 |
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2 |
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1D |
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6 |
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4 |
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SD0 |
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1 |
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R |
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1 |
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RD0 |
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11 |
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CP1 |
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10 |
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S |
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10 |
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SD1 |
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9 |
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11 |
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13 |
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RD1 |
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C2 |
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12 |
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Q0 |
Q0 |
Q1 Q1 |
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2D |
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8 |
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13 |
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R |
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VCC = Pin 14 |
5 |
6 |
9 8 |
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GND = Pin 7 |
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SF00046 |
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SF00047 |
1996 Jul 01 |
2 |
853±1278 01670 |
Philips Semiconductors |
Product specification |
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Dual D-type flip-flop with set and reset |
74ALS74A |
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LOGIC DIAGRAM
SD |
4, 10 |
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RD |
1, 13 |
5, 9 |
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Q |
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3, 11 |
6, 8 |
CP |
Q |
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D |
2, 12 |
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VCC = Pin 14 |
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GND = Pin 7 |
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SF00048 |
FUNCTION TABLE
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INPUTS |
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OUTPUTS |
OPERATING |
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CP |
D |
Q |
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MODE |
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SD |
RD |
Q |
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L |
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H |
X |
X |
H |
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L |
Asynchronous set |
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H |
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L |
X |
X |
L |
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H |
Asynchronous reset |
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L |
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L |
X |
X |
H |
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H |
Undetermined* |
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H |
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H |
↑ |
h |
H |
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L |
Load ª1º |
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H |
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H |
↑ |
l |
L |
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H |
Load ª0º |
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H |
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H |
↑ |
X |
NC |
NC |
Hold |
H = High voltage level
h= High state must be present one setup time prior to Low-to-High clock transition
L = Low voltage level
l= Low state must be present one setup time prior to Low-to-High clock transition
NC= |
No change from the previous setup |
X = |
Don't care |
↑= Low-to-High clock transition
↑= Not Low-to-High clock transition
*= Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL |
PARAMETER |
RATING |
UNIT |
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VCC |
Supply voltage |
±0.5 to +7.0 |
V |
VIN |
Input voltage |
±0.5 to +7.0 |
V |
IIN |
Input current |
±30 to +5 |
mA |
VOUT |
Voltage applied to output in High output state |
±0.5 to VCC |
V |
IOUT |
Current applied to output in Low output state |
16 |
mA |
Tamb |
Operating free-air temperature range |
0 to +70 |
°C |
Tstg |
Storage temperature range |
±65 to +150 |
°C |
RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
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LIMITS |
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UNIT |
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MIN |
NOM |
MAX |
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VCC |
Supply voltage |
4.5 |
5.0 |
5.5 |
V |
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VIH |
High-level input voltage |
2.0 |
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V |
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VIL |
Low-level input voltage |
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0.8 |
V |
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IIk |
Input clamp current |
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±18 |
mA |
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IOH |
High-level output current |
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±0.4 |
mA |
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IOL |
Low-level output current |
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8 |
mA |
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Tamb |
Operating free-air temperature range |
0 |
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+70 |
°C |
1996 Jul 01 |
3 |