Philips N74ALS74AD, N74ALS74ADB, N74ALS74AN Datasheet

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Philips N74ALS74AD, N74ALS74ADB, N74ALS74AN Datasheet

INTEGRATED CIRCUITS

74ALS74A

Dual D-type flip-flop with set and reset

Product specification

1996 Jul 01

IC05 Data Handbook

m n r

Philips Semiconductors

Product specification

 

 

 

 

 

Dual D-type flip-flop with set and reset

74ALS74A

 

 

 

 

 

 

DESCRIPTION

The 74ALS74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock input. When set and reset are inactive (High), data at the D input is transferred to the Q and Q outputs on the Low-to-High transition of the clock. Data must be stable just one setup time prior to the Low-to-High transition of the clock for predictable operation. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be changed without affecting the levels of the output.

 

 

TYPICAL

TYPE

TYPICAL fMAX

SUPPLY CURRENT

 

 

(TOTAL)

 

 

 

74ALS74A

150MHz

3.0mA

 

 

 

ORDERING INFORMATION

 

ORDER CODE

 

 

 

DRAWING

DESCRIPTION

COMMERCIAL RANGE

 

VCC = 5V ±10%,

NUMBER

 

Tamb = 0°C to +70°C

 

14-pin plastic DIP

74ALS74AN

SOT27-1

 

 

 

14-pin plastic SO

74ALS74AD

SOT108-1

 

 

 

14-pin plastic SSOP

74ALS74ADB

SOT337-1

Type II

 

 

 

 

 

PIN CONFIGURATION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RD0

1

 

14

VCC

 

 

 

 

D0

 

 

 

 

 

 

 

 

 

 

 

2

 

13

 

RD1

 

CP0

 

 

 

D1

 

3

 

12

 

 

 

 

 

 

 

 

 

CP1

 

 

SD0

4

 

11

 

 

Q0

 

 

 

 

 

 

 

 

 

5

 

10

 

SD1

 

 

 

 

 

 

 

 

 

Q1

 

 

 

Q0

6

 

9

GND

 

 

 

 

 

 

 

7

 

8

 

Q1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SF00045

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

 

 

PINS

 

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

74ALS (U.L.)

 

 

LOAD VALUE

 

 

 

 

 

 

 

 

 

 

 

 

 

HIGH/LOW

 

 

HIGH/LOW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D0, D1

 

Data inputs

 

 

1.0/2.0

 

 

 

20μA/0.2mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CP0, CP1

 

Clock inputs (active rising edge)

 

 

1.0/2.0

 

 

 

20μA/0.2mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Set inputs (active-Low)

 

 

2.0/4.0

 

 

 

40μA/0.4mA

 

SD0, SD1

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset inputs (active-Low)

 

 

2.0/4.0

 

 

 

40μA/0.4mA

 

RD0, RD1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q0, Q1,

 

 

 

 

 

 

Data outputs

 

 

20/80

 

 

 

0.4mA/8mA

Q0, Q1

 

 

 

 

NOTE: One (1.0) ALS unit load is defined as: 20μA in the High state and 0.1mA in the Low state.

 

 

 

 

 

LOGIC SYMBOL

 

 

 

 

 

 

 

 

 

 

IEC/IEEE SYMBOL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

S

&

 

5

 

3

 

 

 

CP0

D0

D1

 

 

3

 

C1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1D

 

 

6

 

4

 

 

 

SD0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

 

1

 

 

 

RD0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

 

 

CP1

 

 

 

 

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

 

SD1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

 

 

 

 

 

 

 

 

 

 

11

 

 

 

13

 

 

 

RD1

 

 

 

 

 

 

 

 

C2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q0

Q0

Q1 Q1

 

 

 

2D

 

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC = Pin 14

5

6

9 8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND = Pin 7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SF00046

 

 

 

 

 

 

 

 

SF00047

1996 Jul 01

2

853±1278 01670

Philips Semiconductors

Product specification

 

 

 

Dual D-type flip-flop with set and reset

74ALS74A

 

 

 

LOGIC DIAGRAM

SD

4, 10

 

 

 

RD

1, 13

5, 9

 

Q

 

3, 11

6, 8

CP

Q

 

 

D

2, 12

 

 

 

VCC = Pin 14

 

GND = Pin 7

 

 

 

SF00048

FUNCTION TABLE

 

 

 

 

INPUTS

 

OUTPUTS

OPERATING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CP

D

Q

 

 

 

MODE

 

SD

RD

Q

 

L

 

H

X

X

H

 

L

Asynchronous set

 

 

 

 

 

 

 

 

 

 

 

H

 

L

X

X

L

 

H

Asynchronous reset

 

 

 

 

 

 

 

 

 

 

 

L

 

L

X

X

H

 

H

Undetermined*

 

 

 

 

 

 

 

 

 

 

 

H

 

H

h

H

 

L

Load ª1º

 

 

 

 

 

 

 

 

 

 

 

H

 

H

l

L

 

H

Load ª0º

 

 

 

 

 

 

 

 

 

 

H

 

H

X

NC

NC

Hold

H = High voltage level

h= High state must be present one setup time prior to Low-to-High clock transition

L = Low voltage level

l= Low state must be present one setup time prior to Low-to-High clock transition

NC=

No change from the previous setup

X =

Don't care

= Low-to-High clock transition

= Not Low-to-High clock transition

*= Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)

SYMBOL

PARAMETER

RATING

UNIT

 

 

 

 

VCC

Supply voltage

±0.5 to +7.0

V

VIN

Input voltage

±0.5 to +7.0

V

IIN

Input current

±30 to +5

mA

VOUT

Voltage applied to output in High output state

±0.5 to VCC

V

IOUT

Current applied to output in Low output state

16

mA

Tamb

Operating free-air temperature range

0 to +70

°C

Tstg

Storage temperature range

±65 to +150

°C

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

 

LIMITS

 

UNIT

 

 

 

MIN

NOM

MAX

 

 

 

 

 

 

 

 

 

VCC

Supply voltage

4.5

5.0

5.5

V

VIH

High-level input voltage

2.0

 

 

V

VIL

Low-level input voltage

 

 

0.8

V

IIk

Input clamp current

 

 

±18

mA

IOH

High-level output current

 

 

±0.4

mA

IOL

Low-level output current

 

 

8

mA

Tamb

Operating free-air temperature range

0

 

+70

°C

1996 Jul 01

3

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