INTEGRATED CIRCUITS
LPC2106/2105/2104 USER MANUAL
Preliminary |
2003 Oct 02 |
Supersedes data of 2003 Sep 17 |
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P s
on o s
Philips Semiconductors |
Preliminary User Manual |
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ARM-based Microcontroller |
LPC2106/2105//2104 |
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2 |
October 02, 2003 |
Philips Semiconductors |
Preliminary User Manual |
ARM-based Microcontroller |
LPC2106/2105/2104 |
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Table of Contents |
List of Figures . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 |
List of Tables . . . . . . . . . . . . . . . |
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Document Revision History . . . . |
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Introduction . . . . . . . . . . . . . . . . |
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Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ARM7TDMI-S Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
On-Chip Flash Memory System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
On-Chip Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
LPC2106/2105/2104 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
LPC2106/2105/2104 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
29 |
Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
29 |
LPC2106/2105/2104 Memory Re-mapping and Boot Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
33 |
Prefetch Abort and Data Abort Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
36 |
System Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Summary of System Control Block Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
External Interrupt Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Memory Mapping Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PLL (Phase Locked Loop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
VPB Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Wakeup Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Memory Accelerator Module (MAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
55 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Memory Accelerator Module Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
MAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
MAM Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Vectored Interrupt Controller (VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
61 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
VIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
VIC Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
71 |
LPC2106/2105/2104 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 LPC2106/2105/2104 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Pin Description for LPC2106/2105/2104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3 |
October 02, 2003 |
Philips Semiconductors |
Preliminary User Manual |
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ARM-based Microcontroller |
LPC2106/2105/2104 |
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Pin Connect Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
81 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
81 |
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
81 |
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
81 |
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
81 |
GPIO Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
83 |
UART 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
85 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
85 |
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
85 |
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
86 |
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
94 |
UART 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
97 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Example Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Pulse Width Modulator (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
4 |
October 02, 2003 |
Philips Semiconductors |
Preliminary User Manual |
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|
ARM-based Microcontroller |
LPC2106/2105/2104 |
|
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Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
RTC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Miscellaneous Register Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Consolidated Time Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Time Counter Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Alarm Register Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
RTC Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Reference Clock Divider (Prescaler) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Flash Memory System and Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Flash Memory System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Flash boot Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Boot process FlowChart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Sector Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 JTAG FLASH Programming interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
EmbeddedICE Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
201 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
201 |
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
201 |
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
201 |
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
202 |
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
203 |
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
204 |
Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
205 |
Embedded Trace Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
207 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
211 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
211 |
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
211 |
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
211 |
How to Enable RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
215 |
RealMonitor build options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Figure 1: LPC2106/2105/2104 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 2: System Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 3: Peripheral Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 4: AHB Peripheral Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 5: VPB Peripheral Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 6: Map of lower memory is showing re-mapped and re-mappable areas. . . . . . . . . . . . . . . . . . . . 35 Figure 7: Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation,
c) external crystal model used for CX1/X2 evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 8: External Interrupt Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 9: PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 10: Reset Block Diagram including Wakeup Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 11: VPB Divider Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 12: Simplified Block Diagram of the Memory Accelerator Module . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 13: Block Diagram of the Vectored Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 14: LPC2106/2105/2104 48-pin package (LQFP48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 15: UART0 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 16: UART1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 17: I2C Bus Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 18: Slave Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 19: Format in the master transmitter mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 20: Format of master receiver mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 21: A master receiver switch to master transmitter after sending repeated START. . . . . . . . . . . . 114 Figure 22: Slave Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 23: Format of slave receiver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 24: Format of slave transmitter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 25: I2C Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Figure 26: SPI Data Transfer Format (CPHA = 0 and CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Figure 27: SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 28: A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled.. . . 140 Figure 29: A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled. . . . 140 Figure 30: Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Figure 31: PWM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Figure 32: Sample PWM waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Figure 33: RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Figure 34: RTC Prescaler block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Figure 35: Watchdog Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Figure 36: Flash Sector Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Figure 37: Map of lower memory after any reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Figure 38: Boot Process flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Figure 39: IAP Parameter passing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Figure 40: EmbeddedICE Debug Environment Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Figure 41: Waveforms for normal operation (not in debug mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Figure 42: Waveforms for Debug mode using the primary JTAG pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Figure 43: ETM Debug Environment Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Figure 44: RealMonitor components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Figure 45: RealMonitor as a state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Figure 46: Exception Handlers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
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Preliminary User Manual |
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LPC2106/2105/2104 |
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October 02, 2003 |
Philips Semiconductors |
Preliminary User Manual |
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LPC2106/2105/2104 |
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Table 1: LPC2106/2105/2104 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 2: ARM Exception Vector Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 3: LPC2106/2105/2104 Memory Mapping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 4: Pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 5: Summary of System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 6: Recommended values for CX1/X2 when oscillation mode is used . . . . . . . . . . . . . . . . . . . . . . . 39 Table 7: External Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 8: External Interrupt Flag Register (EXTINT - 0xE01FC140). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 9: External Interrupt Wakeup Register (EXTWAKE - 0xE01FC144) . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 10: MEMMAP Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 11: Memory Mapping Control Register (MEMMAP - 0xE01FC040). . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 12: PLL Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 13: PLL Control Register (PLLCON - 0xE01FC080) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 14: PLL Configuration Register (PLLCFG - 0xE01FC084) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 15: PLL Status Register (PLLSTAT - 0xE01FC088) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 16: PLL Control Bit Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 17: PLL Feed Register (PLLFEED - 0xE01FC08C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 18: PLL Divider Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 19: PLL Multiplier Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 20: Power Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 21: Power Control Register (PCON - 0xE01FC0C0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 22: Power Control for Peripherals Register (PCONP - 0xE01FC0C4). . . . . . . . . . . . . . . . . . . . . . . . 50 Table 23: VPBDIV Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 24: VPB Divider Register (VPBDIV - 0xE01FC100). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 25: MAM Responses to Program Accesses of Various Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 26: MAM Responses to Data and DMA Accesses of Various Types. . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 27: Summary of System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 28: MAM Control Register (MAMCR - 0xE01FC000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 29: MAM Timing Register (MAMTIM - 0xE01FC004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 30: VIC Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 31: Software Interrupt Register (VICSoftInt - 0xFFFFF018, Read/Write) . . . . . . . . . . . . . . . . . . . . . 64 Table 32: Software Interrupt Clear Register (VICSoftIntClear - 0xFFFFF01C, Write Only). . . . . . . . . . . . . 64 Table 33: Raw Interrupt Status Register (VICRawIntr - 0xFFFFF008, Read-Only) . . . . . . . . . . . . . . . . . . . 64 Table 34: Interrupt Enable Register (VICINtEnable - 0xFFFFF010, Read/Write) . . . . . . . . . . . . . . . . . . . . 65 Table 35: Software Interrupt Clear Register (VICIntEnClear - 0xFFFFF014, Write Only) . . . . . . . . . . . . . . 65 Table 36: Interrupt Select Register (VICIntSelect - 0xFFFFF00C, Read/Write) . . . . . . . . . . . . . . . . . . . . . 65 Table 37: IRQ Status Register (VICIRQStatus - 0xFFFFF000, Read-Only) . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 38: IRQ Status Register (VICFIQStatus - 0xFFFFF004, Read-Only) . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 39: Vector Control Registers (VICVectCntl0-15 - 0xFFFFF200-23C, Read/Write) . . . . . . . . . . . . . . 66 Table 40: Vector Address Registers (VICVectAddr0-15 - 0xFFFFF100-13C, Read/Write) . . . . . . . . . . . . . 66 Table 41: Default Vector Address Register (VICDefVectAddr - 0xFFFFF034, Read/Write) . . . . . . . . . . . . 66 Table 42: Vector Address Register (VICVectAddr - 0xFFFFF030, Read/Write) . . . . . . . . . . . . . . . . . . . . . 67 Table 43: Protection Enable Register (VICProtection - 0xFFFFF020, Read/Write). . . . . . . . . . . . . . . . . . . 67 Table 44: Connection of Interrupt Sources to the Vectored Interrupt Controller . . . . . . . . . . . . . . . . . . . . . 68 Table 45: Pin description for LPC2106/2105/2104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 46: Pin description and corresponding functions for LPC2106/2105/2104 . . . . . . . . . . . . . . . . . . . . 73 Table 47: Pin Connect Block Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 48: Pin Function Select Register 0 (PINSEL0 - 0xE002C000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 49: Pin Function Select Register 1 (PINSEL1 - 0xE002C004). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 50: Pin Function Select Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 51: GPIO Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 52: GPIO Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 53: GPIO Pin Value Register (IOPIN - 0xE0028000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 54: GPIO Output Set Register (IOSET - 0xE0028004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 55: GPIO Output Clear Register (IOCLR - 0xE002800C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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Preliminary User Manual |
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ARM-based Microcontroller |
LPC2106/2105/2104 |
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Table 56: GPIO Direction Register (IODIR - 0xE0028008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 57: UART 0 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 58: UART 0 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 59: UART0 Receiver Buffer Register (U0RBR - 0xE000C000 when DLAB = 0, Read Only). . . . . . . 87 Table 60: UART0 Transmit Holding Register (U0THR - 0xE000C000 when DLAB = 0, Write Only). . . . . . 87 Table 61: UART0 Divisor Latch LSB Register (U0DLL - 0xE000C000 when DLAB = 1). . . . . . . . . . . . . . . 87 Table 62: UART0 Divisor Latch MSB Register (U0DLM - 0xE000C004 when DLAB = 1). . . . . . . . . . . . . . 87 Table 63: UART0 Interrupt Enable Register Bit Descriptions (U0IER - 0xE000C004 when DLAB = 0) . . . 88 Table 64: UART0 Interrupt Identification Register Bit Descriptions (U0IIR - 0xE000C008, Read Only) . . . 88 Table 65: UART0 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 66: UART0 FIFO Control Register Bit Descriptions (U0FCR - 0xE000C008) . . . . . . . . . . . . . . . . . . 90 Table 67: UART0 Line Control Register Bit Descriptions (U0LCR - 0xE000C00C). . . . . . . . . . . . . . . . . . . 91 Table 68: UART0 Line Status Register Bit Descriptions (U0LSR - 0xE000C014, Read Only) . . . . . . . . . . 92 Table 69: UART0 Scratchpad Register (U0SCR - 0xE000C01C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 70: UART1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 71: UART 1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 72: UART1 Receiver Buffer Register (U1RBR - 0xE0010000 when DLAB = 0, Read Only) . . . . . . . 99 Table 73: UART1 Transmit Holding Register (U1THR - 0xE0010000 when DLAB = 0, Write Only) . . . . . . 99 Table 74: UART1 Divisor Latch LSB Register (U1DLL - 0xE0010000 when DLAB = 1) . . . . . . . . . . . . . . . 99 Table 75: UART1 Divisor Latch MSB Register (U1DLM - 0xE0010004 when DLAB = 1) . . . . . . . . . . . . . 100 Table 76: UART1 Interrupt Enable Register Bit Descriptions (U1IER - 0xE0010004 when DLAB = 0) . . . 100 Table 77: UART1 Interrupt Identification Register Bit Descriptions (IIR - 0xE0010008, Read Only) . . . . . 101 Table 78: UART1 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 79: UART1 FCR Bit Descriptions (U1FCR - 0xE0010008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 80: UART1 Line Control Register Bit Descriptions (U1LCR - 0xE001000C) . . . . . . . . . . . . . . . . . . 104 Table 81: UART1 Modem Control Register Bit Descriptions (U1MCR - 0xE0010010) . . . . . . . . . . . . . . . 105 Table 82: UART1 Line Status Register Bit Descriptions (U1LSR - 0xE0010014, Read Only). . . . . . . . . . 106 Table 83: UART1 Modem Status Register Bit Descriptions (U1MSR - 0x0xE0010018) . . . . . . . . . . . . . . 107 Table 84: UART1 Scratchpad Register (U1SCR - 0xE001001C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 85: I2C Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 86: I2C Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 87: I2C Control Set Register (I2CONSET - 0xE001C000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 88: I2C Control Clear Register (I2CONCLR - 0xE001C018) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 89: I2C Status Register (I2STAT - 0xE001C004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 90: I2C Data Register (I2DAT - 0xE001C008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 91: I2C Slave Address Register (I2ADR - 0xE001C00C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 92: I2C SCL High Duty Cycle Register (I2SCLH - 0xE001C010) . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 93: I2C SCL Low Duty Cycle Register (I2SCLL - 0xE001C014) . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 94: I2C Clock Rate Selections for VPB Clock Divider = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 95: I2C Clock Rate Selections for VPB Clock Divider = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 96: I2C Clock Rate Selections for VPB Clock Divider = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 97: SPI Data To Clock Phase Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 98: SPI Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 99: SPI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 100: SPI Control Register (SPCR - 0xE0020000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 101: SPI Status Register (SPSR - 0xE0020004). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 102: SPI Data Register (SPDR - 0xE0020008). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 103: SPI Clock Counter Register (SPCCR - 0xE002000C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 104: SPI Interrupt Register (SPINT - 0xE002001C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 105: Pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 106: Timer 0 and Timer 1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 107: Interrupt Register
(IR: Timer 0 - T0IR: 0xE0004000; Timer 1 - T1IR: 0xE0008000) . . . . . . . . . . . . . . . . . . . . . . . 136 Table 108: Timer Control Register
(TCR: Timer 0 - T0TCR: 0xE0004004; Timer 1 - T1TCR: 0xE0008004) . . . . . . . . . . . . . . . . . . 136 Table 109: Match Control Register
(MCR: Timer 0 - T0MCR: 0xE0004014; Timer 1 - T1MCR: 0xE0008014). . . . . . . . . . . . . . . . . 137
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Table 110: Capture Control Register
(CCR: Timer 0 - T0CCR: 0xE0004028; Timer 1 - T1CCR: 0xE0008028) . . . . . . . . . . . . . . . . . 138 Table 111: External Match Register
(EMR: Timer 0 - T0EMR: 0xE000403C; Timer 1 - T1EMR: 0xE000803C) . . . . . . . . . . . . . . . . 139 Table 112: External Match Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 113: Set and Reset inputs for PWM Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Table 114: Pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Table 115: Pulse Width Modulator Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Table 116: PWM Interrupt Register (PWMIR - 0xE0014000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 117: PWM Timer Control Register (PWMTCR - 0xE0014004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Table 118: PWM Match Control Register (PWMMCR - 0xE0014014) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Table 119: PWM Control Register (PWMPCR - 0xE001404C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 120: PWM Latch Enable Register (PWMLER - 0xE0014050). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 121: Real Time Clock Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Table 122: Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Table 123: Interrupt Location Register Bits (ILR - 0xE0024000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Table 124: Clock Tick Counter Bits (CTC - 0xE0024004). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Table 125: Clock Control Register Bits (CCR - 0xE0024008). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Table 126: Counter Increment Interrupt Register Bits (CIIR - 0xE002400C) . . . . . . . . . . . . . . . . . . . . . . . 162 Table 127: Alarm Mask Register Bits (AMR - 0xE0024010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Table 128: Consolidated Time Register 0 Bits (CTIME0 - 0xE0024014) . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Table 129: Consolidated Time Register 1 Bits (CTIME1 - 0xE0024018) . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Table 130: Consolidated Time Register 2 Bits (CTIME2 - 0xE002401C) . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Table 131: Time Counter Relationships and Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 132: Time Counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 133: Alarm Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Table 134: Reference Clock Divider registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Table 135: Prescaler Integer Register (PREINT - 0xE0024080). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Table 136: Prescaler Fraction Register (PREFRAC - 0xE0024084). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Table 137: Watchdog Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Table 138: Watchdog Mode Register (WDMOD - 0xE0000000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Table 139: Watchdog Feed Register (WDFEED - 0xE0000008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Table 140: Watchdog Timer Value Register (WDTV - 0xE000000C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Table 141: Sectors in a device with 128K bytes of Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Table 142: ISP Command Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Table 143: ISP Unlock command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Table 144: ISP Set Baud Rate command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Table 145: Correlation between possible ISP baudrates and external crystal frequency (in MHz). . . . . . . 185 Table 146: ISP Echo command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Table 147: ISP Write to RAM command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Table 148: ISP Read Memory command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Table 149: ISP Prepare sector(s) for write operation command description. . . . . . . . . . . . . . . . . . . . . . . . 188 Table 150: ISP Copy RAM to Flash command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Table 151: ISP Go command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Table 152: ISP Erase sector command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Table 153: ISP Blank check sector(s) command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Table 154: ISP Read Part ID command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Table 155: ISP Read Boot Code version command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Table 156: ISP Compare command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Table 157: ISP Return Codes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Table 158: IAP Command Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Table 159: IAP Prepare sector(s) for write operation command description. . . . . . . . . . . . . . . . . . . . . . . . 195 Table 160: IAP Copy RAM to Flash command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Table 161: IAP Erase Sector(s) command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Table 162: IAP Blank check sector(s) command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Table 163: IAP Read Part ID command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Table 164: IAP Read Boot Code version command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
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Table 165: IAP Compare command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Table 166: IAP Status Codes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Table 167: EmbeddedICE Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Table 168: EmbeddedICE Logic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Table 169: JTAG Pins Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Table 170: ETM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Table 171: ETM Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Table 172: ETM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Table 173: RealMonitor stack requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
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May, 2003:
• Prototype LPC2106/2105/2104 User Manual created from the design specification.
July, 2003:
•Flash Programming chapter added.
•Memory Accelerator Module chapter added.
•Register names in UARTs and timers updated.
•List of all registers added in the Introduction chapter.
•Pin Configuration chapter added.
August, 2003:
•MAM, VIC, GPIO, and RTC Usage Notes added.
•EmbeddedICE chapter updated.
September, 2003:
•Details on JTAG ports added in the EmbeddedICE chapter.
•Details on crystal oscillator added in the System Control Block chapter.
•List of possible baudrates when ISP is used added in the Flash Memory System and Programming chapter.
•Details on reset timing requirements added in the System Control Block, Reset chapter.
October, 2003:
• Number of Flash erase and write cycel is added in the Introduction chapter.
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•ARM7TDMI-S processor.
•128 kilobyte on-chip Flash Program Memory with In-System Programming (ISP) and In-Application Programming (IAP) capability. Flash programming time is 1 ms for up to a 512 byte line. 10,000 erase and write cycles are guaranteed per 512 byte line. Single sector erase (8 kB) or the whole chip erase is done in 400 ms.
•64/32/16 kilobyte Static RAM (LPC2106/2105/2104).
•Vectored Interrupt Controller.
•Emulation Trace Module supports real-time trace.
•RealMonitor module enables real time debugging.
•Standard ARM Test/Debug interface for compatibility with existing tools.
•Very small package LQFP48 (7x7mm2).
•Two UARTs, one with full modem interface.
•I2C serial interface.
•SPI serial interface.
•Two timers, each with 4 capture/compare channels.
•PWM unit with up to 6 PWM outputs.
•Real Time Clock.
•Watchdog Timer.
•General purpose I/O pins.
•CPU operating range up to 60 MHz.
•Dual power supply.
-CPU operating voltage range of 1.65V to 1.95V (1.8V +/- 8.3%).
-I/O power supply range of 3.0V to 3.6V (3.3V +/- 10%).
•Two low power modes, Idle and Power Down.
•Processor wakeup from Power Down mode via external interrupt.
•Individual enable/disable of peripheral functions for power optimization.
•On-chip crystal oscillator with an operating range of 10 MHz to 25 MHz.
•On-chip PLL allows CPU operation up to the maximum CPU rate. May be used over the entire crystal operating range.
•Internet gateway.
•Serial communications protocol converter.
•Access control.
•Industrial Control.
•Medical equipment.
Introduction |
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The LPC2106/2105/2104 consists of an ARM7TDMI-S CPU with emulation support, the ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced High-performance Bus (AHB) for interface to the interrupt controller, and the VLSI Peripheral Bus (VPB, a compatible superset of ARM’s AMBA Advanced Peripheral Bus) for connection to on-chip peripheral functions. The LPC2106/2105/2104 configures the ARM7TDMI-S processor in little-endian byte order.
AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the 4 gigabyte ARM memory space. Each AHB peripheral is allocated a 16 kilobyte address space within the AHB address space. LPC2106/05/04 peripheral functions (other than the interrupt controller) are connected to the VPB bus. The AHB to VPB bridge interfaces the VPB bus to the AHB bus. VPB peripherals are also allocated a 2 megabyte range of addresses, beginning at the 3.5 gigabyte address point. Each VPB peripheral is allocated a 16 kilobyte address space within the VPB address space.
The connection of on-chip peripherals to device pins is controlled by a Pin Connection Block. This must be configured by software to fit specific application requirements for the use of peripheral functions and pins.
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:
•The standard 32-bit ARM instruction set.
•A 16-bit THUMB instruction set.
The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system.
The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that can be found on official ARM website.
The LPC2106/2105/2104 incorporates a 128K byte Flash memory system. This memory may be used for both code and data storage. Programming of the Flash memory may be accomplished in several ways: over the serial built-in JTAG interface, using In System Programming (ISP) and UART0, or by means of In Application Programming (IAP) capabilities. The application program, using the In Application Programming (IAP) functions, may also erase and/or program the Flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc.
Introduction |
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The LPC2106, LPC2105 and LPC2104 provide a 64K byte, 32K byte and 16K byte static RAM memory respectively that may be used for code and/or data storage. The SRAM supports 8-bit, 16-bit, and 32-bit accesses.
The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls during back-to-back writes. The write-back buffer always holds the last data sent by software to the SRAM. This data is only written to the SRAM when another write is requested by software. If a chip reset occurs, actual SRAM contents will not reflect the most recent write request. Any software that checks SRAM contents after reset must take this into account. A dummy write to an unused location may be appended to any operation in order to guarantee that all data has really been written into the SRAM.
Introduction |
17 |
October 02, 2003 |
Philips Semiconductors |
Preliminary User Manual |
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ARM-based Microcontroller |
LPC2106/2105/2104 |
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1 |
1 |
1 |
1 |
1 |
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TRST |
TMS |
CKT |
TDI |
TDO |
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Xtal1 |
Xtal2 RST Vdd Vss |
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Test/Debug Interface |
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System |
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EmulationTrace Module |
PLL |
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Functions |
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ARM7TDMI-S |
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System |
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Clock |
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AHB Bridge |
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Vectored Interrupt |
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AMBA AHB |
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Controller |
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ARM7 Local Bus |
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(Advanced High-performance Bus) |
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Internal SRAM |
Internal Flash |
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AHB |
Controller |
Controller |
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Decoder |
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64/32/16 kB |
128 kB |
AHB to VPB |
VPB |
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Bridge |
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Divider |
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SRAM |
FLASH |
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VPB (VLSI |
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Peripheral Bus) |
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EINT0 * |
External |
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I2C Serial |
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SCL * |
EINT1 * |
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SDA * |
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EINT2 * |
Interrupts |
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Interface |
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CAP0..2 * |
Capture / |
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SPI Serial |
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SCK * |
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MOSI * |
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Compare |
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MAT0..2 * |
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Interface |
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MISO * |
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Timer 0 |
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SSEL * |
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CAP0..3 * |
Capture / |
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UART0 |
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TxD * |
MAT0..3 * |
Compare |
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RxD * |
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Timer 1 |
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GPIO (22 pins) |
General |
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TxD * |
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UART1 |
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RxD * |
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GPIO (10 pins) |
Purpose I/O |
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Modem Control |
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(6 pins) * |
PWM1..6 * |
PWM0 |
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Watchdog |
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Timer |
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Real Time |
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System |
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Clock |
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Control |
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* Shared with GPIO |
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1 When Test/Debug Interface is used, GPIO/other functions sharing these pins are not available |
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Figure 1: LPC2106/2105/2104 Block Diagram
Introduction |
18 |
October 02, 2003 |
Philips Semiconductors |
Preliminary User Manual |
|
|
ARM-based Microcontroller |
LPC2106/2105/2104 |
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Accesses to registers in LPC2106/2105/2104 is restricted in the following ways:
1)user must NOT attempt to access any register locations not defined.
2)Access to any defined register locations must be strictly for the functions for the registers.
3)Register bits labeled ’-’, ’0’ or ’1’ can ONLY be written and read as follows:
-’-’ MUST be written with ’0’, but can return any value when read (even if it was written with ’0’). It is a reserved bit and may be used in future derivatives.
-’0’ MUST be written with ’0’, and will return a ’0’ when read.
-’1’ MUST be written with ’1’, and will return a ’1’ when read.
The following table shows all registers available in LPC2106/2105/2104 microcontroller sorted according to the address.
Access to the specific one can be categorized as either read/write, read only or write only (R/W, RO and WO respectively).
"Reset Value" field refers to the data stored in used/accessible bits only. It does not include reserved bits content. Some registers may contain undetermined data upon reset. In this case, reset value is categorized as "undefined". Classification as "NA" is used in case reset value is not applicable. Some registers in RTC are not affected by the chip reset. Their reset value is marked as * and these registers must be initialized by software if the RTC is enabled.
Registers in LPC2106/2105/2104 are 8, 16 or 32 bits wide. For 8 bit registers shown in Table 1, bit residing in the MSB (The Most Significant Bit) column corresponds to the bit 7 of that register, while bit in the LSB (The Least Significant Bit) column corresponds to the bit 0 of the same register.
If a register is 16/32 bit wide, the bit residing in the top left corner of its description, is the bit corresponding to the bit 15/31 of the register, while the bit in the bottom right corner corresponds to bit 0 of this register.
Examples: bit "ENA6" in PWMPCR register (address 0xE001404C) represents the bit at position 14 in this register; bits 15, 8, 7 and 0 in the same register are reserved. Bit "Stop on MR6" in PWMMCR register (0xE0014014) corresponds to the bit at position 20; bits 31 to 21 of the same register are reserved.
Unused (reserved) bits are marked with "-" and represented as gray fields. Access to them is restricted as already described.
Table 1: LPC2106/2105/2104 Registers
Address |
Name |
Description |
MSB |
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LSB |
Access |
Reset |
Offset |
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Value |
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WD |
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0xE0000000 |
WD |
Watchdog |
- |
- |
- |
- |
WD |
WD |
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WDRE |
WDEN |
R/W |
0 |
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MOD |
mode register |
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INT |
TOF |
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SET |
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Watchdog |
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0xE0000004 |
WDTC |
timer |
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32 bit data |
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R/W |
0xFF |
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constant |
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register |
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Watchdog |
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0xE0000008 |
WD |
feed |
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8 bit data (0xAA fallowed by 0x55) |
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WO |
NA |
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FEED |
sequence |
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register |
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Introduction |
19 |
October 02, 2003 |
Philips Semiconductors |
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Preliminary User Manual |
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ARM-based Microcontroller |
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LPC2106/2105/2104 |
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Table 1: LPC2106/2105/2104 Registers |
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Address |
Name |
Description |
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MSB |
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LSB |
Access |
Reset |
Offset |
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Value |
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Watchdog |
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0xE000000C |
WDTV |
timer value |
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32 bit data |
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RO |
0xFF |
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register |
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Timer 0 |
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0xE0004000 |
T0IR |
T0 Interrupt |
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- |
CR2 |
CR1 |
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CR0 |
MR3 |
MR2 |
MR1 |
MR0 |
R/W |
0 |
Register |
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Int. |
Int. |
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Int. |
Int. |
Int. |
Int. |
Int. |
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0xE0004004 |
T0TCR |
T0 Control |
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- |
- |
- |
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- |
- |
- |
CTR |
CTR |
R/W |
0 |
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Register |
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Enable |
Reset |
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0xE0004008 |
T0TC |
T0 Counter |
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32 bit data |
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RW |
0 |
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0xE000400C |
T0PR |
T0 Prescale |
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32 bit data |
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R/W |
0 |
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Register |
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0xE0004010 |
T0PC |
T0 Prescale |
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32 bit data |
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R/W |
0 |
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Counter |
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Stop |
Reset |
Int. on |
Stop |
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4 reserved (-) bits |
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on |
on |
on |
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T0 Match |
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MR3 |
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MR3 |
MR3 |
MR2 |
R/W |
0 |
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0xE0004014 |
T0MCR |
Control |
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Register |
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Reset |
Int. on |
Stop |
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Reset |
Int. on |
Stop |
Reset |
Int. on |
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on |
MR2 |
on |
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on |
MR1 |
on |
on |
MR0 |
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MR2 |
MR1 |
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MR1 |
MR0 |
MR0 |
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0xE0004018 |
T0MR0 |
T0 Match |
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32 bit data |
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R/W |
0 |
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Register 0 |
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0xE000401C |
T0MR1 |
T0 Match |
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32 bit data |
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R/W |
0 |
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Register 1 |
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0xE0004020 |
T0MR2 |
T0 Match |
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32 bit data |
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R/W |
0 |
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Register 2 |
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0xE0004024 |
T0MR3 |
T0 Match |
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32 bit data |
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R/W |
0 |
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Register 3 |
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7 reserved (-) bits |
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Int. on |
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T0 Capture |
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Cpt.2 |
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0xE0004028 |
T0CCR |
Control |
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Int. on |
Int. on |
Int. on |
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Int. on |
Int. on |
Int. on |
Int. on |
Int. on |
R/W |
0 |
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Register |
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Cpt.2 |
Cpt.2 |
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Cpt.1 |
Cpt.1 |
Cpt.0 |
Cpt.0 |
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falling |
rising |
Cpt.1 |
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falling |
rising |
Cpt.0 |
falling |
rising |
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0xE000402C |
T0CR0 |
T0 Capture |
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32 bit data |
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RO |
0 |
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Register 0 |
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0xE0004030 |
T0CR1 |
T0 Capture |
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32 bit data |
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RO |
0 |
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Register 1 |
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0xE0004034 |
T0CR2 |
T0 Capture |
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32 bit data |
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RO |
0 |
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Register 2 |
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Introduction |
20 |
October 02, 2003 |
Philips Semiconductors |
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Preliminary User Manual |
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ARM-based Microcontroller |
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LPC2106/2105/2104 |
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Table 1: LPC2106/2105/2104 Registers |
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Address |
Name |
Description |
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MSB |
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LSB |
Access |
Reset |
Offset |
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Value |
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T0 External |
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6 reserved (-) bits |
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External Match |
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Control 2 |
R/W |
0 |
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0xE000403C |
T0EMR |
Match |
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Register |
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External Match |
External Match |
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- |
Ext. |
Ext. |
Ext. |
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Control 1 |
Control 0 |
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Mtch2. |
Mtch.1 |
Mtch.0 |
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Timer 1 |
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0xE0008000 |
T1IR |
T1 Interrupt |
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CR3 |
CR2 |
CR1 |
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CR0 |
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MR3 |
MR2 |
MR1 |
MR0 |
R/W |
0 |
Register |
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Int. |
Int. |
Int. |
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Int. |
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Int. |
Int. |
Int. |
Int. |
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0xE0008004 |
T1TCR |
T1 Control |
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- |
- |
- |
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- |
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- |
- |
CTR |
CTR |
R/W |
0 |
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Register |
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Enable |
Reset |
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0xE0008008 |
T1TC |
T1 Counter |
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32 bit data |
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RW |
0 |
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0xE000800C |
T1PR |
T1 Prescale |
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32 bit data |
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R/W |
0 |
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Register |
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|
0xE0008010 |
T1PC |
T1 Prescale |
|
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
||
Counter |
|
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|
|||||||
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|
|
Stop |
Reset |
Int. on |
Stop |
|
|
|
|
|
|
|
4 reserved (-) bits |
|
|
on |
on |
on |
|
|
|||
|
|
T1 Match |
|
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|
|
MR3 |
|
|
||||||
|
|
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|
|
|
|
|
|
MR3 |
MR3 |
MR2 |
|
|
||
0xE0008014 |
T1MCR |
Control |
|
|
|
|
|
|
|
|
|
|
|
R/W |
0 |
|
|
Register |
|
Reset |
Int. on |
Stop |
|
Reset |
|
Int. on |
Stop |
Reset |
Int. on |
|
|
|
|
|
|
on |
MR2 |
on |
|
on |
|
MR1 |
on |
on |
MR0 |
|
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|
|
|
|
MR2 |
MR1 |
|
MR1 |
|
MR0 |
MR0 |
|
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|||
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|
|||||
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|
|
0xE0008018 |
T1MR0 |
T1 Match |
|
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
||
Register 0 |
|
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|||||||
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|
0xE000801C |
T1MR1 |
T1 Match |
|
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
||
Register 1 |
|
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|
|
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|
|
|
|||||||
|
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|
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|
|
|
0xE0008020 |
T1MR2 |
T1 Match |
|
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
||
Register 2 |
|
|
|
|
|
|
|
|
|||||||
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|
|
0xE0008024 |
T1MR3 |
T1 Match |
|
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
||
Register 3 |
|
|
|
|
|
|
|
|
|||||||
|
|
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|
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|
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|
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|
|
|
|
|
|
|
|
4 reserved (-) bits |
|
|
Int. on |
Int. on |
Int. on |
Int. on |
|
|
||
|
|
|
|
|
|
|
Cpt.3 |
Cpt.3 |
|
|
|||||
|
|
T1 Capture |
|
|
|
|
Cpt.3 |
Cpt.2 |
|
|
|||||
|
|
|
|
|
|
|
|
|
falling |
rising |
R/W |
0 |
|||
0xE0008028 |
T1CCR |
Control |
|
|
|
|
|
|
|
|
|
|
|
||
|
|
Register |
|
Int. on |
Int. on |
Int. on |
|
Int. on |
|
Int. on |
Int. on |
Int. on |
Int. on |
|
|
|
|
|
|
Cpt.2 |
Cpt.2 |
Cpt.1 |
|
Cpt.1 |
|
Cpt.1 |
Cpt.0 |
Cpt.0 |
Cpt.0 |
|
|
|
|
|
|
falling |
rising |
|
falling |
|
rising |
falling |
rising |
|
|
||
|
|
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE000802C |
T1CR0 |
T1 Capture |
|
|
|
|
|
32 bit data |
|
|
|
RO |
0 |
||
Register 0 |
|
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0008030 |
T1CR1 |
T1 Capture |
|
|
|
|
|
32 bit data |
|
|
|
RO |
0 |
||
Register 1 |
|
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0008034 |
T1CR2 |
T1 Capture |
|
|
|
|
|
32 bit data |
|
|
|
RO |
0 |
||
Register 2 |
|
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Introduction |
21 |
October 02, 2003 |
Philips Semiconductors |
|
|
|
|
|
|
|
|
|
|
Preliminary User Manual |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ARM-based Microcontroller |
|
|
|
|
|
|
|
LPC2106/2105/2104 |
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Table 1: LPC2106/2105/2104 Registers |
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Address |
Name |
Description |
|
MSB |
|
|
|
|
|
|
|
LSB |
Access |
Reset |
Offset |
|
|
|
|
|
|
|
|
Value |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0008038 |
T1CR3 |
T1 Capture |
|
|
|
|
|
32 bit data |
|
|
|
RO |
0 |
|
|
|
Register 3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
T1 External |
|
|
4 reserved (-) bits |
|
External Match |
External Match |
|
|
||||
|
|
|
|
|
Control 3 |
Control 2 |
|
|
||||||
0xE000803C |
T1EMR |
Match |
|
|
|
|
|
|
|
|
|
|
R/W |
0 |
|
|
Register |
|
External Match |
External Match |
Ext. |
Ext. |
Ext. |
Ext. |
|
|
|||
|
|
|
|
Control 1 |
Control 0 |
Mtch.3 |
Mtch2. |
Mtch.1 |
Mtch.0 |
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
UART 0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U0RBR |
U0 Receiver |
|
|
|
|
|
|
|
|
|
|
|
un- |
|
Buffer |
|
|
|
|
|
8 bit data |
|
|
|
RO |
|||
|
(DLAB=0) |
Register |
|
|
|
|
|
|
|
|
|
|
|
defined |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE000C000 |
U0THR |
U0 Transmit |
|
|
|
|
|
|
|
|
|
|
|
|
Holding |
|
|
|
|
|
8 bit data |
|
|
|
WO |
NA |
|||
|
(DLAB=0) |
Register |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U0DLL |
U0 Divisor |
|
|
|
|
|
8 bit data |
|
|
|
R/W |
0x01 |
|
|
(DLAB=1) |
Latch LSB |
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U0 Interrupt |
|
|
|
|
|
|
|
En. Rx |
Enable |
En. Rx |
|
|
|
U0IER |
Enable |
|
0 |
0 |
0 |
|
0 |
0 |
Line |
THRE |
Data |
R/W |
0 |
0xE000C004 |
(DLAB=0) |
Register |
|
|
|
|
|
|
|
Status |
Int. |
Av.Int. |
|
|
|
|
|
|
|
|
|
|
Int. |
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U0DLM |
U0 Divisor |
|
|
|
|
|
8 bit data |
|
|
|
R/W |
0 |
|
|
(DLAB=1) |
Latch MSB |
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U0IIR |
U0 Interrupt |
|
FIFOs Enabled |
0 |
|
0 |
IIR3 |
IIR2 |
IIR1 |
IIR0 |
RO |
0x01 |
|
|
ID Register |
|
|
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE000C008 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U0 FIFO |
|
|
|
|
|
|
|
U0 Tx |
U0 Rx |
U0 |
|
|
|
|
U0FCR |
Control |
|
Rx Trigger |
- |
|
- |
- |
FIFO |
FIFO |
FIFO |
WO |
0 |
|
|
|
Register |
|
|
|
|
|
|
|
Reset |
Reset |
Enable |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U0 Line |
|
|
Set |
Stick |
|
Even |
Parity |
Nm. of |
Word Length |
|
|
|
0xE000C00C |
U0LCR |
Control |
|
DLAB |
Break |
Parity |
|
Parity |
Enable |
Stop |
Select |
R/W |
0 |
|
|
|
Register |
|
|
|
|
|
Select |
|
Bits |
|
|
|
|
|
|
U0 Line |
|
Rx |
|
|
|
|
|
|
|
|
|
|
0xE000C014 |
U0LSR |
Status |
|
FIFO |
TEMT |
THRE |
|
BI |
FE |
PE |
OE |
DR |
RO |
0x60 |
|
|
Register |
|
Error |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE000C01C |
U0SCR |
U0 Scratch |
|
|
|
|
|
8 bit data |
|
|
|
R/W |
0 |
|
Pad Register |
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
UART 1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Introduction |
22 |
October 02, 2003 |
Philips Semiconductors |
|
|
|
|
|
|
|
|
|
Preliminary User Manual |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ARM-based Microcontroller |
|
|
|
|
|
|
LPC2106/2105/2104 |
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Table 1: LPC2106/2105/2104 Registers |
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Address |
Name |
Description |
|
MSB |
|
|
|
|
|
|
LSB |
Access |
Reset |
Offset |
|
|
|
|
|
|
|
Value |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U1RBR |
U1 Receiver |
|
|
|
|
|
|
|
|
|
|
un- |
|
Buffer |
|
|
|
|
8 bit data |
|
|
|
RO |
|||
|
(DLAB=0) |
Register |
|
|
|
|
|
|
|
|
|
|
defined |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0010000 |
U1THR |
U1 Transmit |
|
|
|
|
8 bit data |
|
|
|
WO |
NA |
|
|
(DLAB=0) |
Holding |
|
|
|
|
|
|
|
||||
|
Register |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U1DLL |
U1 Divisor |
|
|
|
|
8 bit data |
|
|
|
R/W |
0x01 |
|
|
(DLAB=1) |
Latch LSB |
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U1 Interrupt |
|
|
|
|
|
En. |
En. Rx |
Enable |
En. Rx |
|
|
|
U1IER |
Enable |
|
0 |
0 |
0 |
0 |
Mdem |
Line |
THRE |
Data |
R/W |
0 |
0xE0010004 |
(DLAB=0) |
Register |
|
|
|
|
|
Satus |
Status |
Int. |
Av.Int. |
|
|
|
|
|
|
|
|
Int. |
Int. |
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U1DLM |
U1 Divisor |
|
|
|
|
8 bit data |
|
|
|
R/W |
0 |
|
|
(DLAB=1) |
Latch MSB |
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U1IIR |
U1 Interrupt |
|
FIFOs Enabled |
0 |
0 |
IIR3 |
IIR2 |
IIR1 |
IIR0 |
RO |
0x01 |
|
|
ID Register |
|
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0010008 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U1 FIFO |
|
|
|
|
|
|
U0 Tx |
U0 Rx |
U0 |
|
|
|
|
U1FCR |
Control |
|
Rx Trigger |
- |
- |
- |
FIFO |
FIFO |
FIFO |
WO |
0 |
|
|
|
Register |
|
|
|
|
|
|
Reset |
Reset |
Enable |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE001000C |
U1LCR |
U1 Line |
|
DLAB |
Set |
Stick |
Even |
Parity |
Nm. of |
Word Length |
R/W |
0 |
|
Control |
|
Break |
Parity |
Parity |
Enable |
Stop |
Select |
||||||
|
|
Register |
|
|
Select |
Bits |
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U1 |
U1 Modem |
|
|
|
|
Loop |
|
|
|
|
|
|
0xE0010010 |
Control |
|
0 |
0 |
0 |
0 |
0 |
RTS |
DTR |
R/W |
0 |
||
MCR |
|
Back |
|||||||||||
|
Register |
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U1 Line |
|
Rx |
|
|
|
|
|
|
|
|
|
0xE0010014 |
U1LSR |
Status |
|
FIFO |
TEMT |
THRE |
BI |
FE |
PE |
OE |
DR |
RO |
0x60 |
|
|
Register |
|
Error |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE001001C |
U1SCR |
U1 Scratch |
|
|
|
|
8 bit data |
|
|
|
R/W |
0 |
|
Pad Register |
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0010018 |
U1 |
U1 Modem |
|
DCD |
RI |
DSR |
CTS |
Delta |
Trailing |
Delta |
Delta |
RO |
0 |
MSR |
Status |
|
DCD |
Edge |
DSR |
CTS |
|||||||
|
Register |
|
|
|
|
|
RI |
|
|
||||
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|
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|
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|
|
||
|
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|
|
|
|
|
|
|
PWM |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PWM |
|
- |
- |
- |
- |
- |
MR6 |
MR5 |
MR4 |
|
|
|
PWM |
|
Int. |
Int. |
Int. |
|
|
||||||
0xE0014000 |
|
|
|
|
|
|
R/W |
0 |
|||||
IR |
Interrupt |
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
MR3 |
MR2 |
MR1 |
MR0 |
|||||
|
Register |
|
- |
- |
- |
- |
|
|
|||||
|
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
Int. |
Int. |
Int. |
Int. |
|
|
0xE0014004 |
PWM |
PWM Timer |
|
- |
- |
- |
- |
PWM |
- |
CTR |
CTR |
|
|
Control |
|
R/W |
0 |
||||||||||
TCR |
|
Enable |
Reset |
Enable |
|||||||||
|
Register |
|
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|
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|
||||
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|
|
|
|
|
|
0xE0014008 |
PWM |
PWM Timer |
|
|
|
|
32 bit data |
|
|
|
RW |
0 |
|
TC |
Counter |
|
|
|
|
|
|
|
|||||
|
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||
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|
|
|
|
|
Introduction |
23 |
October 02, 2003 |
Philips Semiconductors |
|
|
|
|
|
|
|
|
|
|
Preliminary User Manual |
|||
|
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|
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|
|
|
ARM-based Microcontroller |
|
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|
|
|
|
LPC2106/2105/2104 |
||||||
|
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|
Table 1: LPC2106/2105/2104 Registers |
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|||
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|
|
Address |
Name |
Description |
|
MSB |
|
|
|
|
|
|
|
LSB |
Access |
Reset |
Offset |
|
|
|
|
|
|
|
|
Value |
|||||
|
|
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|
|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PWM |
PWM |
|
|
|
|
|
|
|
|
|
|
|
|
0xE001400C |
Prescale |
|
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
||
PR |
|
|
|
|
|
|
|
|
||||||
|
Register |
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|
|
|
|
PWM |
PWM |
|
|
|
|
|
|
|
|
|
|
|
|
0xE0014010 |
Prescale |
|
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
||
PC |
|
|
|
|
|
|
|
|
||||||
|
Counter |
|
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|
|
Stop |
Reset |
Int. on |
Stop |
Reset |
|
|
|
|
|
|
11 reserved (-) bits |
on |
on |
on |
on |
|
|
||||
|
|
|
|
MR6 |
|
|
||||||||
|
|
|
|
|
|
|
|
MR6 |
MR6 |
MR5 |
MR5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
PWM Match |
|
|
|
|
|
|
|
|
|
|
|
|
|
PWM |
|
Int. on |
Stop |
|
Reset |
Int. on |
Stop |
Reset |
Int. on |
Stop |
|
|
|
0xE0014014 |
Control |
|
on |
|
on |
on |
on |
on |
R/W |
0 |
||||
MCR |
|
MR5 |
|
MR4 |
MR3 |
|||||||||
|
Register |
|
MR4 |
|
MR4 |
MR3 |
MR3 |
MR2 |
|
|
||||
|
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Reset |
Int. on |
Stop |
Reset |
Int. on |
Stop |
Reset |
Int. on |
|
|
|
|
|
|
|
on |
on |
on |
on |
on |
|
|
||||
|
|
|
|
MR2 |
|
MR1 |
MR0 |
|
|
|||||
|
|
|
|
MR2 |
|
MR1 |
MR1 |
MR0 |
MR0 |
|
|
|||
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0014018 |
PWM |
PWM Match |
|
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
MR0 |
Register 0 |
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE001401C |
PWM |
PWM Match |
|
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
MR1 |
Register 1 |
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0014020 |
PWM |
PWM Match |
|
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
MR2 |
Register 2 |
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0014024 |
PWM |
PWM Match |
|
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
MR3 |
Register 3 |
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0014040 |
PWM |
PWM Match |
|
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
MR4 |
Register 4 |
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0014044 |
PWM |
PWM Match |
|
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
MR5 |
Register 5 |
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0014048 |
PWM |
PWM Match |
|
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
MR6 |
Register 6 |
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE001404C |
PWM |
PWM Control |
|
- |
ENA6 |
|
ENA5 |
ENA4 |
ENA3 |
ENA2 |
ENA1 |
- |
R/W |
0 |
PCR |
Register |
|
- |
SEL6 |
|
SEL5 |
SEL4 |
SEL3 |
SEL2 |
SEL1 |
- |
|||
|
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PWM Latch |
|
|
Ena. |
Ena. |
Ena. |
Ena. |
Ena. |
Ena. |
Ena. |
|
|
|
0xE0014050 |
PWM |
|
- |
PWM |
|
PWM |
PWM |
PWM |
PWM |
PWM |
PWM |
R/W |
0 |
|
Enable |
|
|
||||||||||||
LER |
|
M6 |
|
M5 |
M4 |
M3 |
M2 |
M1 |
M0 |
|||||
|
Register |
|
|
|
|
|
||||||||
|
|
|
|
Latch |
|
Latch |
Latch |
Latch |
Latch |
Latch |
Latch |
|
|
|
|
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
I2C |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE001C000 |
I2CON |
I2C Control |
|
- |
I2EN |
|
STA |
STO |
SI |
AA |
- |
- |
R/W |
0 |
SET |
Set Register |
|
|
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE001C004 |
I2STAT |
I2C Status |
|
|
|
5 bit Status |
|
0 |
0 |
0 |
RO |
0xF8 |
||
Register |
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE001C008 |
I2DAT |
I2C Data |
|
|
|
|
|
8 bit data |
|
|
|
R/W |
0 |
|
Register |
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Introduction |
24 |
October 02, 2003 |
Philips Semiconductors |
|
|
|
|
|
|
|
|
|
|
Preliminary User Manual |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ARM-based Microcontroller |
|
|
|
|
|
|
|
LPC2106/2105/2104 |
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Table 1: LPC2106/2105/2104 Registers |
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
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|
|
|
|
|
|
|
Address |
Name |
Description |
|
MSB |
|
|
|
|
|
|
|
LSB |
Access |
Reset |
Offset |
|
|
|
|
|
|
|
|
Value |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
I2 |
I2C Slave |
|
|
|
|
|
|
|
|
|
|
|
|
0xE001C00C |
Address |
|
|
|
|
7 bit data |
|
|
|
GC |
R/W |
0 |
||
ADR |
|
|
|
|
|
|
|
|||||||
|
Register |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SCL Duty |
|
|
|
|
|
|
|
|
|
|
|
|
0xE001C010 |
I2 |
Cycle |
|
|
|
|
16 bit data |
|
|
|
R/W |
0x04 |
||
SCLH |
Register High |
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
Half Word |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
I2 |
SCL Duty |
|
|
|
|
|
|
|
|
|
|
|
|
0xE001C014 |
Cycle |
|
|
|
|
16 bit data |
|
|
|
R/W |
0x04 |
|||
SCLL |
Register Low |
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
Half Word |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
I2CON |
I2C Control |
|
- |
I2ENC |
STAC |
- |
|
SIC |
AAC |
- |
- |
WO |
NA |
0xE001C018 |
Clear |
|
|
|||||||||||
|
CLR |
Register |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SPI |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0020000 |
SPCR |
SPI Control |
|
SPIE |
LSBF |
MSTR |
CPOL |
|
CPHA |
- |
- |
- |
R/W |
0 |
|
|
Register |
|
|
|
|
|
|
|
|
|
|
|
|
0xE0020004 |
SPSR |
SPI Status |
|
SPIF |
WCOL |
ROVR |
MODF |
|
ABRT |
- |
- |
- |
RO |
0 |
Register |
|
|
||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0020008 |
SPDR |
SPI Data |
|
|
|
|
8 bit data |
|
|
|
R/W |
0 |
||
Register |
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE002000C |
SP |
SPI Clock |
|
|
|
|
|
|
|
|
|
|
|
|
Counter |
|
|
|
|
8 bit data |
|
|
|
R/W |
0 |
||||
CCR |
|
|
|
|
|
|
|
|||||||
|
Register |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE002001C |
SPINT |
SPI Interrupt |
|
- |
- |
- |
- |
|
- |
- |
- |
SPI |
R/W |
0 |
|
|
Flag |
|
|
|
|
|
|
|
|
|
Int. |
|
|
RTC |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Interrupt |
|
- |
- |
- |
- |
|
- |
- |
RTC |
RTC |
R/W |
* |
0xE0024000 |
ILR |
Location |
|
|
||||||||||
|
|
ALF |
CIF |
|||||||||||
|
|
Register |
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0024004 |
CTC |
Clock Tick |
|
|
|
|
15 bit data |
|
|
|
- |
RO |
* |
|
Counter |
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0024008 |
CCR |
Clock Control |
|
- |
- |
- |
- |
|
CTTEST |
CTC |
CLK |
R/W |
* |
|
Register |
|
|
RST |
EN |
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Counter |
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0xE002400C |
CIIR |
Increment |
|
IM |
IM |
IM |
IM |
|
IM |
IM |
IM |
IM |
R/W |
* |
Interrupt |
|
YEAR |
MON |
DOY |
DOW |
|
DOM |
HOUR |
MIN |
SEC |
||||
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|||||||||
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|
Register |
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0xE0024010 |
AMR |
Alarm Mask |
|
AMR |
AMR |
AMR |
AMR |
|
AMR |
AMR |
AMR |
AMR |
R/W |
* |
Register |
|
YEAR |
MON |
DOY |
DOW |
|
DOM |
HOUR |
MIN |
SEC |
||||
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|||||||||
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|
|
Introduction |
25 |
October 02, 2003 |
Philips Semiconductors |
|
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|
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|
|
|
Preliminary User Manual |
|||
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|
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|
ARM-based Microcontroller |
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|
LPC2106/2105/2104 |
||||||
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Table 1: LPC2106/2105/2104 Registers |
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Address |
Name |
Description |
|
MSB |
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LSB |
Access |
Reset |
Offset |
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|
Value |
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- |
- |
- |
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- |
- |
|
3 bit Day of Week |
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0xE0024014 |
|
Consolidated |
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- |
- |
- |
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5 bit Hours |
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CTIME0 |
Time |
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RO |
* |
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- |
- |
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6 bit Minutes |
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Register 0 |
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- |
- |
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6 bit Seconds |
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- |
- |
- |
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- |
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Consolidated |
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0xE0024018 |
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12 bit Year |
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RO |
* |
||
CTIME1 |
Time |
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|||
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Register 1 |
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- |
- |
- |
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- |
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4 bit Month |
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||
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- |
- |
- |
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|
5 bit Day of Month |
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||||
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0xE002401C |
|
Consolidated |
|
|
reserved (-) 20 bits |
|
|
12 bit Day of Year |
RO |
* |
|||||
CTIME2 |
Time |
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||||||||||
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|
Register 2 |
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0xE0024020 |
SEC |
Seconds |
|
- |
- |
|
|
|
6 bit data |
R/W |
* |
||||
Register |
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|||||||||||
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0xE0024024 |
MIN |
Minutes |
|
- |
- |
|
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|
6 bit data |
R/W |
* |
||||
Register |
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0xE0024028 |
HOUR |
Hours |
|
- |
- |
- |
|
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|
|
5 bit data |
R/W |
* |
||
|
|
Register |
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|
0xE002402C |
DOM |
Day of Month |
|
- |
- |
- |
|
|
|
|
5 bit data |
R/W |
* |
||
Register |
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||||||||||
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|
0xE0024030 |
DOW |
Day of Week |
|
- |
- |
- |
|
- |
- |
|
|
3 bit data |
R/W |
* |
|
Register |
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|||||||||||
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Day of Year |
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|
0xE0024034 |
DOY |
|
|
reserved (-) 7 bits |
|
|
|
9 bit data |
R/W |
* |
|||||
Register |
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||||||||||
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0xE0024038 |
MONTH |
Months |
|
- |
- |
- |
|
- |
|
|
4 bit data |
R/W |
* |
||
Register |
|
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|
|
|||||||||||
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|
0xE002403C |
YEAR |
Year Register |
|
reserved (-) 4 bits |
|
|
|
12 bit data |
R/W |
* |
|||||
|
|
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|
|
|
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|
|
|
|
0xE0024060 |
AL |
Alarm value |
|
- |
- |
|
|
|
6 bit data |
R/W |
* |
||||
SEC |
for Seconds |
|
|
|
|
||||||||||
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||
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0xE0024064 |
AL |
Alarm value |
|
- |
- |
|
|
|
6 bit data |
R/W |
* |
||||
MIN |
for Minutes |
|
|
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||||||||||
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|
0xE0024068 |
AL |
Alarm value |
|
- |
- |
- |
|
|
|
|
5 bit data |
R/W |
* |
||
HOUR |
for Hours |
|
|
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|||||||||
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||
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|
0xE002406C |
AL |
Alarm value |
|
- |
- |
- |
|
|
|
|
5 bit data |
R/W |
* |
||
for Day of |
|
|
|
|
|
||||||||||
DOM |
|
|
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|
|
||||||||||
|
Month |
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|
0xE0024070 |
AL |
Alarm value |
|
- |
- |
- |
|
- |
- |
|
|
3 bit data |
R/W |
* |
|
for Day of |
|
|
|
|
|||||||||||
DOW |
|
|
|
|
|||||||||||
|
Week |
|
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|
|
|
Introduction |
26 |
October 02, 2003 |
Philips Semiconductors |
|
|
|
|
|
|
|
|
|
|
Preliminary User Manual |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ARM-based Microcontroller |
|
|
|
|
|
|
|
LPC2106/2105/2104 |
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Table 1: LPC2106/2105/2104 Registers |
|
|
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|
|
|
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|||
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|
|
Address |
Name |
Description |
|
MSB |
|
|
|
|
|
|
|
LSB |
Access |
Reset |
Offset |
|
|
|
|
|
|
|
|
|
|
|
|
|
Value |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AL |
Alarm value |
|
|
|
|
|
|
|
|
|
|
|
|
0xE0024074 |
for Day of |
|
reserved (-) 7 bits |
|
|
|
9 bit data |
R/W |
* |
|||||
DOY |
|
|
|
|
||||||||||
|
Year |
|
|
|
|
|
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|
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|
0xE0024078 |
AL |
Alarm value |
|
- |
- |
- |
- |
|
|
4 bit data |
R/W |
* |
||
MON |
for Months |
|
|
|
||||||||||
|
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|
|
|
|
|
||
|
|
|
|
|
|
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|
|
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|
|
|
|
|
0xE002407C |
AL |
Alarm value |
|
reserved |
|
|
|
12 bit data |
|
|
R/W |
* |
||
YEAR |
for Year |
|
(-) 4 bits |
|
|
|
|
|
||||||
|
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|
||||
|
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|
|
|
|
|
|
|
0xE0024080 |
PRE |
Prescale |
|
reserved |
|
|
|
13 bit data |
|
|
R/W |
0 |
||
value, integer |
|
|
|
|
|
|
||||||||
INT |
|
(-) 3 bits |
|
|
|
|
|
|||||||
|
portion |
|
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|||
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|
|
PRE |
Prescale |
|
|
|
|
|
|
|
|
|
|
|
|
0xE0024084 |
value, |
|
- |
|
|
|
15 bit data |
|
|
R/W |
0 |
|||
FRAC |
fractional |
|
|
|
|
|
|
|||||||
|
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||
|
|
portion |
|
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|
GPIO |
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|
0xE0028000 |
IOPIN |
GPIO Pin |
|
|
|
|
32 bit data |
|
|
|
RO |
NA |
||
value register |
|
|
|
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|||||||
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|
GPIO 0 |
|
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|
|
0xE0028004 |
IOSET |
Output set |
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
||
|
|
register |
|
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|
GPIO 0 |
|
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|
|
0xE0028008 |
IODIR |
Direction |
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
||
control |
|
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|
|
|
|
|
|||||||
|
|
register |
|
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|
GPIO 0 |
|
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|
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|
|
|
|
0xE002800C |
IOCLR |
Output clear |
|
|
|
|
32 bit data |
|
|
|
WO |
0 |
||
|
|
register |
|
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|
Pin Connet Block |
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PIN |
Pin function |
|
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|
0xE002C000 |
select |
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|||
SEL0 |
|
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|||||||
|
register 0 |
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|
PIN |
Pin function |
|
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|
|
0xE002C004 |
select |
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|||
SEL1 |
|
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|
|
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|
|||||||
|
register 1 |
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System Control Block |
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|
|
|
0xE01FC000 |
MAM |
MAM control |
|
- |
- |
- |
- |
|
- |
- |
2 bit data |
R/W |
0 |
|
CR |
register |
|
|
|||||||||||
|
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|
||
|
|
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|
|
|
|
|
0xE01FC004 |
MAM |
MAM timing |
|
- |
- |
- |
- |
|
- |
|
3 bit data |
R/W |
0x07 |
|
TIM |
control |
|
|
|
||||||||||
|
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||
|
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|
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|
|
|
|
|
|
|
Introduction |
27 |
October 02, 2003 |
Philips Semiconductors |
|
|
|
|
|
|
|
|
|
|
|
Preliminary User Manual |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ARM-based Microcontroller |
|
|
|
|
|
|
|
|
LPC2106/2105/2104 |
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Table 1: LPC2106/2105/2104 Registers |
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
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|
|
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Address |
Name |
Description |
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MSB |
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LSB |
Access |
Reset |
Offset |
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Value |
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MEM |
Memory |
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0xE01FC040 |
mapping |
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- |
- |
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- |
- |
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- |
- |
2 bit data |
R/W |
0 |
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MAP |
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control |
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0xE01FC080 |
PLL |
PLL control |
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- |
- |
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- |
- |
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- |
- |
PLLC |
PLLE |
R/W |
0 |
CON |
register |
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PLL |
PLL |
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0xE01FC084 |
configuration |
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- |
2bit data PSEL |
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5 bit data MSEL |
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R/W |
0 |
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CFG |
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register |
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0xE01FC088 |
PLL |
PLL status |
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- |
- |
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- |
- |
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- |
PLOCK |
PLLC |
PLLE |
RO |
0 |
STAT |
register |
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- |
2bit data PSEL |
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5 bit data MSEL |
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0xE01FC08C |
PLL |
PLL feed |
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8 bit data |
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WO |
NA |
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FEED |
register |
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0xE01FC0C0 |
PCON |
Power control |
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- |
- |
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- |
- |
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- |
- |
PD |
IDL |
R/W |
0 |
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register |
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Power control |
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reserved (-) 22 bits |
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PC |
PC |
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RTC |
SPI |
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0xE01FC0C4 |
PCONP |
for |
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R/W |
0x3BE |
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peripherals |
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PC |
- |
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PC |
PC |
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PC |
PC |
PC |
- |
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I2C |
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PWM0 |
URT1 |
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URT0 |
TIM1 |
TIM0 |
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0xE01FC100 |
VPB |
VPB divider |
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- |
- |
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- |
- |
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- |
- |
2 bit data |
R/W |
0 |
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DIV |
control |
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0xE01FC140 |
EXT |
External |
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- |
- |
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- |
- |
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- |
EINT2 |
EINT1 |
EINT0 |
R/W |
0 |
interrupt flag |
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INT |
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register |
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External |
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EXT |
EXT |
EXT |
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EXT |
interrupt |
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0xE01FC144 |
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- |
- |
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- |
- |
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- |
WAKE |
WAKE |
WAKE |
R/W |
0 |
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WAKE |
wakeup |
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2 |
1 |
0 |
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register |
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Introduction |
28 |
October 02, 2003 |
Philips Semiconductors |
Preliminary User Manual |
|
|
ARM-based Microcontroller |
LPC2106/2105/2104 |
|
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The LPC2106/2105/2104 incorporates several distinct memory regions, shown in the following figures. Figure 2 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping, which is described later in this section.
4.0GB
3.75GB
3.5GB
3.0 GB
2.0 GB
1.0 GB
0.0 GB
AHB Peripherals
VPB Peripherals
Reserved for
External Memory
Boot Block
(re-mapped from On-Chip Flash memory)
Reserved for
On-Chip Memory
On-Chip Static RAM
128 kB On-Chip Non-Volatile Memory
0xFFFF FFFF
0xF000 0000
0xE000 0000
0xC000 0000
0x8000 0000
0x4000 FFFF: LPC2106 (64 kB)
0x4000 7FFF: LPC2105 (32 kB)
0x4000 3FFF: LPC2104 (16 kB)
0x4000 0000
0x0002 0000
0x0001 FFFF
0x0000 0000
Figure 2: System Memory Map
LPC2106/2105/2104 Memory Addressing |
29 |
October 02, 2003 |
Philips Semiconductors |
Preliminary User Manual |
|
|
ARM-based Microcontroller |
LPC2106/2105/2104 |
|
|
4.0 GB |
|
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0xFFFF FFFF |
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AHB Peripherals |
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4.0 GB - 2 MB |
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0xFFE0 0000 |
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0xFFDF FFFF |
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Notes:
- AHB section is 128 x 16 kB blocks (totaling 2 MB).
Reserved
- VPB section is 128 x 16 kB blocks (totaling 2 MB).
3.75 GB |
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0xF000 0000 |
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0xEFFF FFFF |
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Reserved
3.5 GB + 2 MB |
|
0xE020 0000 |
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0xE01F FFFF |
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VPB Peripherals |
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3.5 GB |
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0xE000 0000 |
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Figure 3: Peripheral Memory Map
Figures 3 through 5 show different views of the peripheral address space. Both the AHB and VPB peripheral areas are 2 megabyte spaces which are divided up into 128 peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the address decoding for each peripheral. All peripheral register addresses are word aligned (to 32-bit boundaries) regardless of their size. This eliminates the need for byte lane mapping hardware that would be required to allow byte (8-bit) or half-word (16bit) accesses to occur at smaller boundaries. An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possible to read or write the upper byte of a word register separately.
LPC2106/2105/2104 Memory Addressing |
30 |
October 02, 2003 |