Philips LPC2106, LPC2105, LPC2104 User Guide

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INTEGRATED CIRCUITS

LPC2106/2105/2104 USER MANUAL

Preliminary Supersedes data of 2003 Sep 17

 

2003 Oct 02

Philips Semiconductors Preliminary User Manual

LPC2106/2105//2104ARM-based Microc ontroller

2 October 02, 2003

Philips Semiconductors Preliminary User Manual

LPC2106/2105/2104ARM-based Microcontroller

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

ARM7TDMI-S Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

On-Chip Flash Memory System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

On-Chip Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

LPC2106/2105/2104 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

LPC2106/2105/2104 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

LPC2106/2105/2104 Memory Re-mapping and Boot Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Prefetch Abort and Data Abort Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

System Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Summary of System Control Block Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

External Interrupt Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Memory Mapping Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

PLL (Phase Locked Loop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

VPB Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Wakeup Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Memory Accelerator Module (MAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Memory Accelerator Module Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

MAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

MAM Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Vectored Interrupt Controller (VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

VIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

VIC Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

LPC2106/2105/2104 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

LPC2106/2105/2104 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Pin Description for LPC2106/2105/2104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3 October 02, 2003

Philips Semiconductors Preliminary User Manual

LPC2106/2105/2104ARM-based Microcontroller

Pin Connect Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

GPIO Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

UART 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

UART 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Example Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Pulse Width Modulator (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

4 October 02, 2003

Philips Semiconductors Preliminary User Manual

LPC2106/2105/2104ARM-based Microcontroller

Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

RTC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Miscellaneous Register Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Consolidated Time Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Time Counter Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Alarm Register Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

RTC Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Reference Clock Divider (Prescaler) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Flash Memory System and Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Flash Memory System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Flash boot Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Boot process FlowChart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Sector Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

JTAG FLASH Programming interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

EmbeddedICE Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Embedded Trace Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

How to Enable RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

RealMonitor build options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

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List of Figures

Figure 1: LPC2106/2105/2104 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 2: System Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 3: Peripheral Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 4: AHB Peripheral Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 5: VPB Peripheral Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 6: Map of lower memory is showing re-mapped and re-mappable areas. . . . . . . . . . . . . . . . . . . . 35

Figure 7: Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation,

c) external crystal model used for CX1/X2 evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 8: External Interrupt Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 9: PLL Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 10: Reset Block Diagram including Wakeup Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 11: VPB Divider Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 12: Simplified Block Diagram of the Memory Accelerator Module . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 13: Block Diagram of the Vectored Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 14: LPC2106/2105/2104 48-pin package (LQFP48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 15: UART0 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 16: UART1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 17: I2C Bus Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 18: Slave Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 19: Format in the master transmitter mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 20: Format of master receiver mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 21: A master receiver switch to master transmitter after sending repeated START. . . . . . . . . . . . 114

Figure 22: Slave Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 23: Format of slave receiver mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 24: Format of slave transmitter mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 25: I2C Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 26: SPI Data Transfer Format (CPHA = 0 and CPHA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 27: SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 28: A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled.. . . 140

Figure 29: A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled. . . . 140

Figure 30: Timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 31: PWM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 32: Sample PWM waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 33: RTC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 34: RTC Prescaler block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 35: Watchdog Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 36: Flash Sector Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 37: Map of lower memory after any reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Figure 38: Boot Process flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 39: IAP Parameter passing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Figure 40: EmbeddedICE Debug Environment Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 41: Waveforms for normal operation (not in debug mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Figure 42: Waveforms for Debug mode using the primary JTAG pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Figure 43: ETM Debug Environment Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 44: RealMonitor components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Figure 45: RealMonitor as a state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Figure 46: Exception Handlers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

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List of Tables

Table 1: LPC2106/2105/2104 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 2: ARM Exception Vector Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 3: LPC2106/2105/2104 Memory Mapping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 4: Pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 5: Summary of System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 6: Recommended values for CX1/X2 when oscillation mode is used . . . . . . . . . . . . . . . . . . . . . . . 39

Table 7: External Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 8: External Interrupt Flag Register (EXTINT - 0xE01FC140). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 9: External Interrupt Wakeup Register (EXTWAKE - 0xE01FC144) . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 10: MEMMAP Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 11: Memory Mapping Control Register (MEMMAP - 0xE01FC040). . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 12: PLL Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 13: PLL Control Register (PLLCON - 0xE01FC080) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 14: PLL Configuration Register (PLLCFG - 0xE01FC084) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 15: PLL Status Register (PLLSTAT - 0xE01FC088) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 16: PLL Control Bit Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 17: PLL Feed Register (PLLFEED - 0xE01FC08C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 18: PLL Divider Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 19: PLL Multiplier Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 20: Power Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 21: Power Control Register (PCON - 0xE01FC0C0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 22: Power Control for Peripherals Register (PCONP - 0xE01FC0C4). . . . . . . . . . . . . . . . . . . . . . . . 50

Table 23: VPBDIV Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 24: VPB Divider Register (VPBDIV - 0xE01FC100). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 25: MAM Responses to Program Accesses of Various Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 26: MAM Responses to Data and DMA Accesses of Various Types. . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 27: Summary of System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 28: MAM Control Register (MAMCR - 0xE01FC000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 29: MAM Timing Register (MAMTIM - 0xE01FC004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 30: VIC Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 31: Software Interrupt Register (VICSoftInt - 0xFFFFF018, Read/Write) . . . . . . . . . . . . . . . . . . . . . 64

Table 32: Software Interrupt Clear Register (VICSoftIntClear - 0xFFFFF01C, Write Only). . . . . . . . . . . . . 64

Table 33: Raw Interrupt Status Register (VICRawIntr - 0xFFFFF008, Read-Only). . . . . . . . . . . . . . . . . . . 64

Table 34: Interrupt Enable Register (VICINtEnable - 0xFFFFF010, Read/Write) . . . . . . . . . . . . . . . . . . . . 65

Table 35: Software Interrupt Clear Register (VICIntEnClear - 0xFFFFF014, Write Only) . . . . . . . . . . . . . . 65

Table 36: Interrupt Select Register (VICIntSelect - 0xFFFFF00C, Read/Write) . . . . . . . . . . . . . . . . . . . . . 65

Table 37: IRQ Status Register (VICIRQStatus - 0xFFFFF000, Read-Only) . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 38: IRQ Status Register (VICFIQStatus - 0xFFFFF004, Read-Only) . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 39: Vector Control Registers (VICVectCntl0-15 - 0xFFFFF200-23C, Read/Write) . . . . . . . . . . . . . . 66

Table 40: Vector Address Registers (VICVectAddr0-15 - 0xFFFFF100-13C, Read/Write) . . . . . . . . . . . . . 66

Table 41: Default Vector Address Register (VICDefVectAddr - 0xFFFFF034, Read/Write) . . . . . . . . . . . . 66

Table 42: Vector Address Register (VICVectAddr - 0xFFFFF030, Read/Write). . . . . . . . . . . . . . . . . . . . . 67

Table 43: Protection Enable Register (VICProtection - 0xFFFFF020, Read/Write). . . . . . . . . . . . . . . . . . . 67

Table 44: Connection of Interrupt Sources to the Vectored Interrupt Controller . . . . . . . . . . . . . . . . . . . . . 68

Table 45: Pin description for LPC2106/2105/2104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 46: Pin description and corresponding functions for LPC2106/2105/2104 . . . . . . . . . . . . . . . . . . . . 73

Table 47: Pin Connect Block Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 48: Pin Function Select Register 0 (PINSEL0 - 0xE002C000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 49: Pin Function Select Register 1 (PINSEL1 - 0xE002C004). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 50: Pin Function Select Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 51: GPIO Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 52: GPIO Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 53: GPIO Pin Value Register (IOPIN - 0xE0028000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 54: GPIO Output Set Register (IOSET - 0xE0028004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 55: GPIO Output Clear Register (IOCLR - 0xE002800C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

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Table 56: GPIO Direction Register (IODIR - 0xE0028008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 57: UART 0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 58: UART 0 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 59: UART0 Receiver Buffer Register (U0RBR - 0xE000C000 when DLAB = 0, Read Only). . . . . . . 87

Table 60: UART0 Transmit Holding Register (U0THR - 0xE000C000 when DLAB = 0, Write Only). . . . . . 87

Table 61: UART0 Divisor Latch LSB Register (U0DLL - 0xE000C000 when DLAB = 1). . . . . . . . . . . . . . . 87

Table 62: UART0 Divisor Latch MSB Register (U0DLM - 0xE000C004 when DLAB = 1). . . . . . . . . . . . . . 87

Table 63: UART0 Interrupt Enable Register Bit Descriptions (U0IER - 0xE000C004 when DLAB = 0) . . . 88 Table 64: UART0 Interrupt Identification Register Bit Descriptions (U0IIR - 0xE000C008, Read Only) . . . 88

Table 65: UART0 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 66: UART0 FIFO Control Register Bit Descriptions (U0FCR - 0xE000C008) . . . . . . . . . . . . . . . . . . 90

Table 67: UART0 Line Control Register Bit Descriptions (U0LCR - 0xE000C00C). . . . . . . . . . . . . . . . . . . 91

Table 68: UART0 Line Status Register Bit Descriptions (U0LSR - 0xE000C014, Read Only) . . . . . . . . . . 92

Table 69: UART0 Scratchpad Register (U0SCR - 0xE000C01C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 70: UART1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 71: UART 1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 72: UART1 Receiver Buffer Register (U1RBR - 0xE0010000 when DLAB = 0, Read Only). . . . . . . 99

Table 73: UART1 Transmit Holding Register (U1THR - 0xE0010000 when DLAB = 0, Write Only). . . . . . 99

Table 74: UART1 Divisor Latch LSB Register (U1DLL - 0xE0010000 when DLAB = 1). . . . . . . . . . . . . . . 99

Table 75: UART1 Divisor Latch MSB Register (U1DLM - 0xE0010004 when DLAB = 1). . . . . . . . . . . . . 100

Table 76: UART1 Interrupt Enable Register Bit Descriptions (U1IER - 0xE0010004 when DLAB = 0). . . 100

Table 77: UART1 Interrupt Identification Register Bit Descriptions (IIR - 0xE0010008, Read Only). . . . . 101

Table 78: UART1 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 79: UART1 FCR Bit Descriptions (U1FCR - 0xE0010008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 80: UART1 Line Control Register Bit Descriptions (U1LCR - 0xE001000C). . . . . . . . . . . . . . . . . . 104

Table 81: UART1 Modem Control Register Bit Descriptions (U1MCR - 0xE0010010) . . . . . . . . . . . . . . . 105

Table 82: UART1 Line Status Register Bit Descriptions (U1LSR - 0xE0010014, Read Only). . . . . . . . . . 106

Table 83: UART1 Modem Status Register Bit Descriptions (U1MSR - 0x0xE0010018) . . . . . . . . . . . . . . 107

Table 84: UART1 Scratchpad Register (U1SCR - 0xE001001C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 85: I2C Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 86: I2C Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 87: I2C Control Set Register (I2CONSET - 0xE001C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 88: I2C Control Clear Register (I2CONCLR - 0xE001C018) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 89: I2C Status Register (I2STAT - 0xE001C004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 90: I2C Data Register (I2DAT - 0xE001C008). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 91: I2C Slave Address Register (I2ADR - 0xE001C00C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 92: I2C SCL High Duty Cycle Register (I2SCLH - 0xE001C010) . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 93: I2C SCL Low Duty Cycle Register (I2SCLL - 0xE001C014) . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 94: I2C Clock Rate Selections for VPB Clock Divider = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 95: I2C Clock Rate Selections for VPB Clock Divider = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 96: I2C Clock Rate Selections for VPB Clock Divider = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 97: SPI Data To Clock Phase Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 98: SPI Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 99: SPI Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 100: SPI Control Register (SPCR - 0xE0020000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 101: SPI Status Register (SPSR - 0xE0020004). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 102: SPI Data Register (SPDR - 0xE0020008). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 103: SPI Clock Counter Register (SPCCR - 0xE002000C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 104: SPI Interrupt Register (SPINT - 0xE002001C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 105: Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 106: Timer 0 and Timer 1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 107: Interrupt Register

(IR: Timer 0 - T0IR: 0xE0004000; Timer 1 - T1IR: 0xE0008000) . . . . . . . . . . . . . . . . . . . . . . . 136

Table 108: Timer Control Register

(TCR: Timer 0 - T0TCR: 0xE0004004; Timer 1 - T1TCR: 0xE0008004). . . . . . . . . . . . . . . . . . 136

Table 109: Match Control Register

(MCR: Timer 0 - T0MCR: 0xE0004014; Timer 1 - T1MCR: 0xE0008014). . . . . . . . . . . . . . . . . 137

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Table 110: Capture Control Register

(CCR: Timer 0 - T0CCR: 0xE0004028; Timer 1 - T1CCR: 0xE0008028) . . . . . . . . . . . . . . . . . 138

Table 111: External Match Register

(EMR: Timer 0 - T0EMR: 0xE000403C; Timer 1 - T1EMR: 0xE000803C) . . . . . . . . . . . . . . . . 139

Table 112: External Match Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 113: Set and Reset inputs for PWM Flip-Flops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 114: Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 115: Pulse Width Modulator Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 116: PWM Interrupt Register (PWMIR - 0xE0014000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 117: PWM Timer Control Register (PWMTCR - 0xE0014004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 118: PWM Match Control Register (PWMMCR - 0xE0014014) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 119: PWM Control Register (PWMPCR - 0xE001404C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 120: PWM Latch Enable Register (PWMLER - 0xE0014050). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 121: Real Time Clock Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 122: Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 123: Interrupt Location Register Bits (ILR - 0xE0024000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 124: Clock Tick Counter Bits (CTC - 0xE0024004). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 125: Clock Control Register Bits (CCR - 0xE0024008). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 126: Counter Increment Interrupt Register Bits (CIIR - 0xE002400C) . . . . . . . . . . . . . . . . . . . . . . . 162

Table 127: Alarm Mask Register Bits (AMR - 0xE0024010). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 128: Consolidated Time Register 0 Bits (CTIME0 - 0xE0024014) . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 129: Consolidated Time Register 1 Bits (CTIME1 - 0xE0024018) . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 130: Consolidated Time Register 2 Bits (CTIME2 - 0xE002401C) . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 131: Time Counter Relationships and Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 132: Time Counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 133: Alarm Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 134: Reference Clock Divider registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 135: Prescaler Integer Register (PREINT - 0xE0024080). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 136: Prescaler Fraction Register (PREFRAC - 0xE0024084). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 137: Watchdog Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 138: Watchdog Mode Register (WDMOD - 0xE0000000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 139: Watchdog Feed Register (WDFEED - 0xE0000008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 140: Watchdog Timer Value Register (WDTV - 0xE000000C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 141: Sectors in a device with 128K bytes of Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 142: ISP Command Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 143: ISP Unlock command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 144: ISP Set Baud Rate command description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 145: Correlation between possible ISP baudrates and external crystal frequency (in MHz). . . . . . . 185

Table 146: ISP Echo command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 147: ISP Write to RAM command description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Table 148: ISP Read Memory command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Table 149: ISP Prepare sector(s) for write operation command description. . . . . . . . . . . . . . . . . . . . . . . . 188

Table 150: ISP Copy RAM to Flash command description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 151: ISP Go command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 152: ISP Erase sector command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 153: ISP Blank check sector(s) command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 154: ISP Read Part ID command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 155: ISP Read Boot Code version command description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 156: ISP Compare command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Table 157: ISP Return Codes Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 158: IAP Command Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table 159: IAP Prepare sector(s) for write operation command description. . . . . . . . . . . . . . . . . . . . . . . . 195

Table 160: IAP Copy RAM to Flash command description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 161: IAP Erase Sector(s) command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 162: IAP Blank check sector(s) command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 163: IAP Read Part ID command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 164: IAP Read Boot Code version command description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

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Table 165: IAP Compare command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 166: IAP Status Codes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 167: EmbeddedICE Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 168: EmbeddedICE Logic Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 169: JTAG Pins Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Table 170: ETM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Table 171: ETM Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Table 172: ETM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 173: RealMonitor stack requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

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DOCUMENT REVISION HISTORY

May, 2003:

• Prototype LPC2106/2105/2104 User Manual created from the design specification.

July, 2003:

• Flash Programming chapter added.

• Memory Accelerator Module chapter added.

• Register names in UARTs and timers updated.

• List of all registers added in the Introduction chapter.

• Pin Configuration chapter added.

August, 2003:

• MAM, VIC, GPIO, and RTC Usage Notes added.

• EmbeddedICE chapter updated.

September, 2003:

• Details on JTAG ports added in the EmbeddedICE chapter.

• Details on crystal oscillator added in the System Control Block chapter.

• List of possible baudrates when ISP is used added in the Flash Memory System and Programming chapter.

• Details on reset timing requirem en ts add ed in the Sys tem Control Block, Reset chapter.

October, 2003:

• Number of Flash erase and write cycel is added in the Introduction chapter.

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1. INTRODUCTION

FEATURES

• ARM7TDMI-S processor.

• 128 kilobyte on-chip Flash Program Memory with In-System Programming (ISP) and In-Application Programming (IAP) capability. Flash programming time is 1 ms for up to a 512 byte line. 10,000 erase and write cycles are guaranteed per 512 byte line. Single sector erase (8 kB) or the whole chip erase is done in 400 ms.

• 64/32/16 kilobyte Static RAM (LPC2106/2105/2104).

• Vectored Interrupt Controller.

• Emulation Trace Module supports real-time trace.

• RealMonitor module enables real time debugging.

• Standard ARM Test/Debug interface for compatibility with existing tools.

• Very small package LQFP48 (7x7mm

• Two UARTs, one with full modem interface.

•I2C serial interface.

• SPI serial interface.

• Two timers, each with 4 capture/compare channels.

• PWM unit with up to 6 PWM outputs.

• Real Time C lock.

• Watchdog Timer.

• General purpose I/O pins.

• CPU operating range up to 60 MHz.

• Dual power supply.

- CPU operating voltage range of 1.65V to 1.95V (1.8V +/- 8.3%).

- I/O power supply range of 3.0V to 3.6V (3.3V +/- 10%).

• Two low power modes, Idle and Power Down.

• Processor wakeup from Power Down mode via external interrupt.

• Individual enable/disable of peripheral functions for power optimization.

• On-chip crystal oscillator with an operating range of 10 MHz to 25 MHz.

• On-chip PLL allows CPU operation up to the maximum CPU rate. May be used over the entire crystal operating range.

APPLICATIONS

• Internet gateway.

• Serial communications protocol converter.

• Access control.

• Industrial Control.

• Medical equipment.

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ARCHITECTURAL OVERVIEW

The LPC2106/2105/2104 consists of an ARM7TDM I-S CPU with emulatio n support, the ARM7 Lo cal Bus for interface to on -chip memory controllers, the AMBA Advanced High-performance Bus (AHB) for interface to the interrupt controller, and the VLSI Peripheral Bus (VPB, a compatible superset of ARM’s AMBA Advanced Peripheral Bus) for connection to on-chip peripheral functions. The LPC2106/2105/2104 configures the ARM7TDMI-S processor in little-endian byte order.

AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the 4 gigabyte ARM memory space. Each AHB peripheral is allocated a 16 kilobyte address space within the AHB address space. LPC2106/05/04 peripheral functions (other than the interrupt controller) are connected to the VPB bus. The AHB to VPB bridge interfaces the VPB bus to the AHB bus. VPB peripherals are also allocated a 2 megabyte range of addresses, beginning at the 3.5 gigabyte address point. Each VPB peripheral is allocated a 16 kilobyte address space within the VPB address space.

The connection of on-chip pe ripherals to d evice pins i s controlled by a Pin Conne ction Block. This must be configured by software to fit specific application requirements for the use of peripheral functions and pins.

ARM7TDMI-S PROCESSOR

The ARM7TDMI-S is a general purpose 32-bit microproce ssor, which offers high perfo rmance and very low pow er consumption . The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are em plo ye d so tha t all parts of the processing and memory systems can operat e con tinuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue.

The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM instruction set.

• A 16-bit TH UMB instruction set.

The THUMB set’s 16-bit ins truc tion length allows it to approach twic e th e de ns ity of s tan dard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code.

THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system.

The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that can be found on official ARM website.

ON-CHIP FLASH MEMORY SYSTEM

The LPC2106/2105/2104 incorporates a 128K byte Flash memory system. This memory may be used for both code and data storage. Programming o f the Fl ash m emory ma y be a ccom plish ed in sev eral w ays: over t he seri al bui lt-in JT AG interfa ce, us ing In System Programming (ISP) and UART0, or by means of In Application Programming (IAP) capabilities. The application program, using the In Application Programming (IAP) functions, may also erase and/or program the Flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc.

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ON-CHIP STATIC RAM

The LPC2106, LPC210 5 and LPC 2104 prov ide a 64K byte, 32K b yte and 16 K byte sta tic RAM me mory r espectivel y that may be used for code and/or data storage. The SRAM supports 8-bit, 16-bit, and 32-bit accesses.

The SRAM controller incorpo r ate s a wri te-b ac k bu ffer i n ord er to p rev ent CPU s tal ls d urin g ba ck -to-back writes. The write-back buffer always holds the last data sent by software to the SRAM. This data is only written to the SRAM when another write is requested by software. If a ch ip res et occurs , actu al SRAM cont ent s w ill not refl ec t the mo st recen t wr ite req ue st. Any sof tw are that checks SRAM contents after reset must take this into account. A dummy write to an unused location may be appended to any operation in order to guarantee that all data has really been written into the SRAM.

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BLOCK DIAGRAM

Internal SRAM

Controller

64/32/16 kB

SRAM

EINT0 * EINT1 * EINT2 *

CAP0..2 *

MAT0..2 *

ARM7 Local Bus

Internal Flash

External

Interrupts

Capture / Compare

Timer 0

Controller

128 kB

FLASH

TMS

TRST

Test/Debug Interface

TDI

TCK

TDO

ARM7TDMI-S

AHB Bridg e

AHB to VPB

Bridge

VPB (VLSI Peripheral Bus)

PLL

System

Module

Emulation Trace

(Advanced High-performance Bus)

Clock

AMBA AHB

VPB

Divider

I2C Serial

Interface

SPI Serial

Interface

Vss

Vdd

RST

Xtal2

Xtal1

System

Functions

Vectored Interrupt

Controller

AHB

Decoder

SCL * SDA *

SCK * MOSI * MISO * SSEL *

CAP0..3 *

MAT0..3 *

GPIO (22 pins)

Capture / Compare

Timer 1

General

GPIO (10 pins)

PWM1..6 *

Purpose I/O

PWM0

Real Time

Clock

* Shared with GPIO

When Test/Debug Interface is used, GPIO/other functions sharing these pins are not available

Figure 1: LPC2106/2105/2104 Block Diagram

UART0

UART1

Watchdog

Timer

System Control

TxD *

RxD *

TxD *

RxD *

Modem Control

(6 pins) *

Introduction 18 October 02, 2003

Philips Semiconductors Preliminary User Manual

LPC2106/2105/2104ARM-based Microcontroller

LPC2106/2105/2104 REGISTERS

Accesses to registers in LPC2106/2105/2104 is restricted in the following ways:

1) user must NOT attempt to access any register locations not defined.

2) Access to any defined register locations must be stri ctly for the functions for the registers.

3) Register bits labeled ’-’, ’0’ or ’1’ can ONLY be written and read as follows:

- ’-’ MUST be written with ’0’, but can return any value when read (even if it was written with ’0’). It is a reserved bit and may be used in future derivatives.

- ’0’ MUST be written with ’0’, and will return a ’0’ when read.

- ’1’ MUST be written with ’1’, and will return a ’1’ when read.

The following table shows all registers available in LPC2106/2105/2104 microcontroller sorted according to the address. Access to the specific one can be categorized as either read/write, read only or write only (R/W, RO and WO respectively). "Reset Value" field refe rs to the data stored in us ed/accessible bit s only. It does not inc lude reserved bits cont ent. Some registers

may contain undeterm ined data up on reset. In thi s case, reset value is ca tegorized as "un defined". Classificati on as "NA" is u sed in case reset value is not applicable. Some registers in RTC are not affected by the chip reset. Their reset value is marked as * and these registers must be initialized by software if the RTC is enabled.

Registers in LPC210 6/2105/2104 are 8, 16 or 3 2 bits wi de. For 8 bit registers show n in Table 1, bit resi ding in the MSB (The Most Significant Bit) col umn corresponds to the bit 7 o f that register, while bit in t he LSB (The Leas t Significant B it) column corr esponds to the bit 0 of the same register.

If a register is 1 6/3 2 bit wide, the b it res iding in t he top left corne r of i ts d escrip tion, is th e bit corre spond ing to the bit 1 5/31 o f the register, while the bit in the bottom right corner corresponds to bit 0 of this register.

Examples: bit "EN A6" in PWM P CR reg ist er ( add res s 0 xE0 014 04 C) rep res ents t he bit at pos iti on 14 in this register; bits 15, 8, 7 and 0 in the same register are reserved. Bit "Stop on MR6" in PWMMCR register (0xE001 4014) corresponds to the bit at positi on 20; bits 31 to 21 of the same register are reserved.

Unused (reserved) bits are marked with "-" and represented as gray fields. Access to them is restricted as already described.

Table 1: LPC2106/2105/2104 Registers

Address

Offset

0xE0000000

0xE0000004 WDTC

Name Description MSB LSB Access

MOD

Watchdog mode register

Watchdog timer constant register

- - - -

WD INTWDTOF

32 bit data R/W 0xFF

WDRE

SET

WDEN R/W 0

Reset Value

Watchdog

0xE0000008

FEED

feed sequence register

8 bit data (0xAA fallowed by 0x55) WO NA

Introduction 19 October 02, 2003

Philips Semiconductors Preliminary User Manual

LPC2106/2105/2104ARM-based Microcontroller

Table 1: LPC2106/2105/2104 Registers

Address

Offset

0xE000000C WDTV

Timer 0

0xE0004000 T0IR

0xE0004004 T0TCR

0xE0004008 T0TC T0 Counter 32 bit data RW 0

0xE000400C T0PR

0xE0004010 T0PC

0xE0004014 T0MCR

Name Description MSB LSB Access

Watchdog timer value register

T0 Interrupt Register

T0 Control Register

T0 Prescale Register

T0 Prescale Counter

T0 Match Control Register

CR2

Int.

- - - - - -

4 reserved (-) bits

Reset

MR2

Int. on

MR2

CR1

Int.

Stop

MR1

32 bit data RO 0xFF

CR0

Int.

Reset

MR1

MR3

Int.

32 bit data R/W 0

Stop

MR3

Int. on

MR1

MR2

Int.

Reset

MR3 Stop

MR0

MR1

Int.

CTR

Enable

Int. on

MR3

Reset

MR0

Int.

CTR

Reset

Stop

MR2

Int. on

MR0

R/W 0

Reset Value

0xE0004018 T0MR0

0xE000401C T0MR1

0xE0004020 T0MR2

0xE0004024 T0MR3

0xE0004028 T0CCR

0xE000402C T0CR0

0xE0004030 T0CR1

0xE0004034 T0CR2

T0 Match Register 0

T0 Match Register 1

T0 Match Register 2

T0 Match Register 3

T0 Capture Control Register

T0 Capture Register 0

T0 Capture Register 1

T0 Capture Register 2

Int. on

Cpt.2

falling

Int. on

Cpt.2 rising

32 bit data R/W 0

7 reserved (-) bits

Int. on

Cpt.1

Int. on

Cpt.1

falling

32 bit data RO 0

Int. on

Cpt.1 rising

Int. on

Cpt.0

Int. on

Cpt.0

falling

Int. on

Cpt.2

Int. on

Cpt.0 rising

R/W 0

Introduction 20 October 02, 2003

Philips Semiconductors Preliminary User Manual

LPC2106/2105/2104ARM-based Microcontroller

Table 1: LPC2106/2105/2104 Registers

Address

Offset

0xE000403C T0EMR

Timer 1

0xE0008000 T1IR

0xE0008004 T1TCR

0xE0008008 T1TC T1 Counter 32 bit data RW 0

0xE000800C T1PR

0xE0008010 T1PC

0xE0008014 T1MCR

Name Description MSB LSB Access

Ext.

Int.

External Match

Control 2

Ext.

Mtch.1

MR1

Int.

CTR

Enable

Int. on

MR3

Reset

MR0

Ext.

Mtch.0

MR0

Int.

CTR

Reset

Stop

MR2

Int. on

MR0

R/W 0

T0 External Match Register

T1 Interrupt Register

T1 Control Register

T1 Prescale Register

T1 Prescale Counter

T1 Match Control Register

6 reserved (-) bits

External Match

Control 1

CR3

Int.

Reset

MR2

CR2

- - - - - -

4 reserved (-) bits

Int. on

MR2

Int.

External Match

Control 0

CR1

Int.

Stop

MR1

CR0

Int.

32 bit data R/W 0

Reset

MR1

MR3

Int.

Stop

MR3

Int. on

MR1

Mtch2.

MR2

Reset

MR3 Stop

MR0

Reset Value

0xE0008018 T1MR0

0xE000801C T1MR1

0xE0008020 T1MR2

0xE0008024 T1MR3

0xE0008028 T1CCR

0xE000802C T1CR0

0xE0008030 T1CR1

0xE0008034 T1CR2

T1 Match Register 0

T1 Match Register 1

T1 Match Register 2

T1 Match Register 3

T1 Capture Control Register

T1 Capture Register 0

T1 Capture Register 1

T1 Capture Register 2

4 reserved (-) bits

Int. on

Cpt.2

falling

Int. on

Cpt.2 rising

Int. on

Cpt.1

32 bit data R/W 0

Int. on

Cpt.3

Int. on

Cpt.1

falling

Int. on

Cpt.1 rising

32 bit data RO 0

Int. on

Cpt.3

falling

Int. on

Cpt.0

Int. on

Cpt.3 rising

Int. on

Cpt.0

falling

Int. on

Cpt.2

R/W 0

Int. on

Cpt.0 rising

Introduction 21 October 02, 2003

Philips Semiconductors Preliminary User Manual

LPC2106/2105/2104ARM-based Microcontroller

Table 1: LPC2106/2105/2104 Registers

Address

Offset

Name Description MSB LSB Access

0xE0008038 T1CR3

0xE000803C T1EMR

UART 0

U0RBR

(DLAB=0)

0xE000C000

U0THR

(DLAB=0)

U0DLL

(DLAB=1)

U0IER

0xE000C004

(DLAB=0)

T1 Capture Register 3

T1 External Match Register

U0 Receiver Buffer Register

U0 Transmit Holding Register

U0 Divisor Latch LSB

U0 Interrupt Enable Register

32 bit data RO 0

4 reserved (-) bits

External Match

Control 1

External Match

Control 0

External Match

Control 3

Ext.

Mtch.3

8 bit data RO

8 bit data WO NA

8 bit data R/W 0x01

00000

Ext.

Mtch2.

En. Rx

Line

Status

Int.

External Match

Control 2

Ext.

Mtch.1

Enable

THRE

Int.

Ext.

Mtch.0

En. Rx

Data

Av.Int.

Reset Value

R/W 0

un-

defined

R/W 0

U0DLM

(DLAB=1)

U0IIR

0xE000C008

U0FCR

0xE000C00C U0LCR

0xE000C014 U0LSR

0xE000C01C U0SCR

UART 1

U0 Divisor Latch MSB

U0 Interrupt ID Register

U0 FIFO Control Register

U0 Line Control Register

U0 Line Status Register

U0 Scratch Pad Register

8 bit data R/W 0

FIFOs Enabled 0 0 IIR3 IIR2 IIR1 IIR0 RO 0x01

Rx Trigger

DLAB

Set

Break

- - -

Stick

Parity

Even

Parity

Select

Parity

Enable

U0 Tx

FIFO

Reset Nm. of

Stop

Bits

U0 Rx

FIFO

Reset

FIFO

Enable

Word Length

Select

WO 0

R/W 0

FIFO

TEMT THRE BI FE PE OE DR RO 0x60

Error

8 bit data R/W 0

Introduction 22 October 02, 2003

Philips Semiconductors Preliminary User Manual

LPC2106/2105/2104ARM-based Microcontroller

Table 1: LPC2106/2105/2104 Registers

Address

Offset

Name Description MSB LSB Access

U1RBR

(DLAB=0)

0xE0010000

U1THR

(DLAB=0)

U1DLL

(DLAB=1)

U1IER

0xE0010004

(DLAB=0)

U1DLM

(DLAB=1)

U1IIR

0xE0010008

U1FCR

0xE001000C U1LCR

0xE0010010

MCR

0xE0010014 U1LSR

U1 Receiver Buffer Register

U1 Transmit Holding Register

U1 Divisor Latch LSB

U1 Interrupt Enable Register

U1 Divisor Latch MSB

U1 Interrupt ID Register

U1 FIFO Control Register

U1 Line Control Register

U1 Modem Control Register

U1 Line Status Register

Reset Value

8 bit data RO

un-

defined

8 bit data WO NA

8 bit data R/W 0x01

En.

0000

Mdem

Satus

En. Rx

Status

Int.

Line

Int.

Enable

THRE

Int.

En. Rx

Data

Av.Int.

R/W 0

8 bit data R/W 0

FIFOs Enabled 0 0 IIR3 IIR2 IIR1 IIR0 RO 0x01

Rx Trigger

DLAB

Set

Break

- - -

Stick

Parity

000

Even

Parity

Select

Loop Back

U0 Tx

FIFO

Reset

Parity

Enable

Nm. of

Stop

0 0 RTS DTR R/W 0

Bits

U0 Rx

FIFO

Reset

FIFO

Enable

Word Length

Select

WO 0

R/W 0

FIFO

TEMT THRE BI FE PE OE DR RO 0x60

Error

U1 Scratch Pad Register

U1 Modem Status Register

8 bit data R/W 0

DCD RI DSR CTS

Delta

DCD

Trailing

Edge

Delta

DSR

Delta

CTS

RO 0

0xE001001C U1SCR

0xE0010018

MSR

PWM

0xE0014000

0xE0014004

0xE0014008

PWM Interrupt Register

PWM Timer Control Register

PWM

TCR

PWMTCPWM Timer

Counter

- - - - -

- - - -

MR3

PWM

Enable

32 bit data RW 0

Int.

MR6

Int.

MR2

Int.

MR5

Int.

MR4

Int.

R/W 0

MR1

Int.

CTR

Reset

MR0

Int.

CTR

Enable

R/W 0

Introduction 23 October 02, 2003

Philips Semiconductors Preliminary User Manual

LPC2106/2105/2104ARM-based Microcontroller

Table 1: LPC2106/2105/2104 Registers

Address

Offset

0xE001400C

0xE0014010

0xE0014014

0xE0014018

0xE001401C

0xE0014020

Name Description MSB LSB Access

PWM Prescale Register

PWM Prescale Counter

PWM Match Control Register

PWM Match Register 0

PWM Match Register 1

PWM Match Register 2

11 reserved (-) bits

Int. on

MR5

Reset

MR2

Stop

MR4

Int. on

MR2

Reset

MR4 Stop

MR1

32 bit data R/W 0

Stop

MR6

Int. on

MR4

Reset

MR1

Reset

MR6

Stop

MR3

Int. on

MR1

Int. on

MR6

Reset

MR3 Stop

MR0

Stop

MR5

Int. on

MR3

Reset

MR0

Reset

MR5 Stop

MR2

Int. on

MR0

R/W 0

32 bit data R/W 0

PWM

MCR

PWM

MR0

PWM

MR1

PWM

MR2

Reset Value

0xE0014024

0xE0014040

0xE0014044

0xE0014048

0xE001404C

0xE0014050

0xE001C000

PWM

MR3

PWM

MR4

PWM

MR5

PWM

MR6

PWM

PCR

PWM

LER

I2CON

SET

0xE001C004 I2STAT

0xE001C008 I2DAT

PWM Match Register 3

PWM Match Register 4

PWM Match Register 5

PWM Match Register 6

PWM Control Register

PWM Latch Enable Register

C Control

I Set Register

C Status

I Register

C Data

I Register

32 bit data R/W 0

- ENA6 ENA5 ENA4 ENA3 ENA2 ENA1 R/W 0

- SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 -

Ena.

PWM

Latch

Ena.

PWM

Latch

Ena.

PWM

Latch

Ena.

PWM

Latch

Ena.

PWM

Latch

Ena.

PWM

Latch

Ena.

PWM

Latch

R/W 0

-I2ENSTASTOSIAA - -R/W0

5 bit Status 0 0 0 RO 0xF8

8 bit data R/W 0

Introduction 24 October 02, 2003

Philips Semiconductors Preliminary User Manual

LPC2106/2105/2104ARM-based Microcontroller

Table 1: LPC2106/2105/2104 Registers

Address

Offset

0xE001C00C

0xE001C010

0xE001C014

0xE001C018

Name Description MSB LSB Access

ADR

SCLH

SCLL

I2CON

CLR

SPI

0xE0020000 SPCR

0xE0020004 SPSR

0xE0020008 SPDR

0xE002000C

CCR

0xE002001C SPINT

C Slave

I Address Register

SCL Duty Cycle Register High Half Word

SCL Duty Cycle Register Low Half Word

C Control

I Clear Register

SPI Control Register

SPI Status Register

SPI Data Register

SPI Clock Counter Register

SPI Interrupt Flag

Reset Value

7 bit data GC R/W 0

16 bit data R/W 0x04

- I2ENC STAC - SIC AAC - -WONA

SPIE LSBF MSTR CPOL CPHA

SPIF WCOL ROVR MODF ABRT

- - -R/W0

- - -RO0

8 bit data R/W 0

- - - - - - -

SPI

Int.

R/W 0

RTC

0xE0024000 ILR

0xE0024004 CTC

0xE0024008 CCR

Interrupt Location Register

Clock Tick Counter

Clock Control Register

- - - - - -

15 bit data

- - - - CTTEST

RTC

ALF

CTC RST

RTC

CIF

R/W *

-RO*

CLK

R/W *

Counter

0xE002400C CIIR

Increment Interrupt

YEARIMMONIMDOYIMDOWIMDOMIMHOURIMMINIMSEC

R/W *

0xE0024010 AMR

Alarm Mask Register

AMR

YEAR

AMR

MON

AMR

DOY

AMR

DOW

AMR

DOM

AMR

HOUR

AMR

MIN

AMR SEC

R/W *

Introduction 25 October 02, 2003

Philips Semiconductors Preliminary User Manual

LPC2106/2105/2104ARM-based Microcontroller

Table 1: LPC2106/2105/2104 Registers

Address

Offset

0xE0024014

0xE0024018

0xE002401C

Name Description MSB LSB Access

CTIME0

CTIME1

CTIME2

0xE0024020 SEC

0xE0024024 MIN

0xE0024028 HOUR

0xE002402C DOM

0xE0024030 DOW

Consolidated Time Register 0

Consolidated Time Register 1

Consolidated Time Register 2

Seconds Register

Minutes Register

Hours Register

Day of Month Register

Day of Week Register

Reset Value

- - - - - 3 bit Day of Week

- - - 5 bit Hours

RO *

- - 6 bit Minutes

- - 6 bit Seconds

- - - -

12 bit Year

RO *

- - - - 4 bit Month

- - - 5 bit Day of Month

reserved (-) 20 bits 12 bit Day of Year RO *

- - 6 bit data R/W *

- - - 5 bit data R/W *

- - - - - 3 bit data R/W *

0xE0024034 DOY

0xE0024038

MONTH

Day of Year Register

Months Register

0xE002403C YEAR Year Register

Alarm value for Seconds

Alarm value for Minutes

Alarm value for Hours

Alarm value for Day of Month

Alarm value for Day of Week

0xE0024060

0xE0024064

0xE0024068

0xE002406C

0xE0024070

SEC

MIN

HOUR

DOM

DOW

reserved (-) 7 bits 9 bit data R/W *

- - - - 4 bit data R/W *

reserved (-) 4 bits 12 bit data R/W *

- - 6 bit data R/W *

- - - 5 bit data R/W *

- - - - - 3 bit data R/W *

Introduction 26 October 02, 2003

Philips Semiconductors Preliminary User Manual

LPC2106/2105/2104ARM-based Microcontroller

Table 1: LPC2106/2105/2104 Registers

Address

Offset

0xE0024074

0xE0024078

0xE002407C

0xE0024080

0xE0024084

GPIO

0xE0028000 IOPIN

0xE0028004 IOSET

Name Description MSB LSB Access

DOY

MON

YEAR

PRE

INT

PRE

FRAC

Alarm value for Day of Year

Alarm value for Months

Alarm value for Year

Prescale value, integer portion

Prescale value, fractional portion

GPIO Pin value regi ster

GPIO 0 Output set register

Reset Value

reserved (-) 7 bits 9 bit data R/W *

- - - - 4 bit data R/W *

reserved

(-) 4 bits

reserved

(-) 3 bits

- 15 bit data R/W 0

32 bit data RO NA

32 bit data R/W 0

12 bit data R/W *

13 bit data R/W 0

0xE0028008 IODIR

0xE002800C IOCLR

Pin Connet Block

0xE002C000

0xE002C004

System Control Block

0xE01FC000

0xE01FC004

SEL0

SEL1

MAMCRMAM control

MAM

TIM

GPIO 0 Direction control register

GPIO 0 Output clear register

Pin funct i on select register 0

Pin funct i on select register 1

control

32 bit data R/W 0

32 bit data WO 0

32 bit data R/W 0

- - - - - - 2 bit data R/W 0

- - - - - 3 bit data R/W 0x07

Introduction 27 October 02, 2003

Philips Semiconductors Preliminary User Manual

LPC2106/2105/2104ARM-based Microcontroller

Table 1: LPC2106/2105/2104 Registers

Address

Offset

0xE01FC040

0xE01FC080

0xE01FC084

0xE01FC088

0xE01FC08C

0xE01FC0C0 PCON

0xE01FC0C4 PCONP

0xE01FC100

Name Description MSB LSB Access

MEM

MAP

PLL

CON

PLL

CFG

PLL

STAT

PLL

FEED

VPB

DIV

Memory mapping control

PLL control register

PLL configuration register

PLL status register

PLL feed register

Power control register

Power control for peripherals

VPB divider control

- - - - - - 2 bit data R/W 0

- - - - - - PLLC PLLE R/W 0

- 2bit data PSEL 5 bit data MSEL R/W 0

- - - - -

- 2bit data PSEL 5 bit data MSEL

8 bit data WO NA

- - - - - - PD IDL R/W 0

reserved (-) 22 bits

I2C

- - - - - - 2 bit data R/W 0

PWM0PCURT1PCURT0PCTIM1PCTIM0

PLOCK

PLLC PLLE

RO 0

RTCPCSPI

R/W 0x3BE

Reset Value

0xE01FC140

0xE01FC144

EXT

INT

EXT

WAKE

External interrupt flag register

External interrupt wakeup register

- - - - - EINT2 EINT1 EINT0 R/W 0

- - - - -

EXT

WAKE

EXT

WAKE

EXT

WAKE0R/W 0

Introduction 28 October 02, 2003

Philips Semiconductors Preliminary User Manual

LPC2106/2105/2104ARM-based Microcontroller

2. LPC2106/2105/2104 MEMORY ADDRESSING

MEMORY MAPS

The LPC2106/2105 /2104 incorporates several distinct memory r egions, shown in t he following figures. Figure 2 shows the overall map of the entire addr ess sp ace from th e user p rogram v iewpoi nt follo wing res et. The i nterrupt v ector a rea sup ports ad dress remapping, which is described later in this section.

4.0 GB

3.75 GB

3.5 GB

3.0 GB

2.0 GB

1.0 GB

AHB Peripherals

VPB Peripherals

Reserved for

External Memory

(re-mapped from On-Chip Flash memory)

Boot Block

Reserved for

On-Chip Memory

On-Chip Static RAM

0xFFFF FFFF 0xF000 0000

0xE000 0000

0xC000 0000

0x8000 0000

0x4000 FFFF: LPC2106 (64 kB) 0x4000 7FFF: LPC2105 (32 kB) 0x4000 3FFF: LPC2104 (16 kB)

0x4000 0000

0x0002 0000

128 kB On-Chip Non-Volatile Memory

0.0 GB

Figure 2: System Memory Map

0x0001 FFFF 0x0000 0000

LPC2106/2105/2104 Memory Addressing 29 October 02, 2003

Philips Semiconductors Preliminary User Manual

LPC2106/2105/2104ARM-based Microcontroller

Notes:

- AHB section is 128 x 16 kB blocks (totaling 2 MB).

- VPB section is 128 x 16 kB blocks (totaling 2 MB).

4.0 GB

4.0 GB - 2 MB

3.75 GB

AHB Peripherals

0xFFFF FFFF 0xFFE0 0000

0xFFDF FFFF

Reserved

0xF000 0000 0xEFFF FFFF

Reserved

3.5 GB + 2 MB VPB Peripherals

3.5 GB

Figure 3: Peripheral Memory Map

Figures 3 through 5 show different views of the peripheral address space. Both the AHB and VPB peripheral areas are 2 megabyte spaces whic h are divided up into 128 periph erals. Each peripheral space is 16 kilobytes in size . This allows simplify ing the address decod ing for ea ch perip heral. All periphera l registe r addresses are wor d aligned (to 32-bi t boundar ies) regard less of their size. This eliminates the need for byte lane mapping hardwa re tha t w oul d be requi red to all ow by te (8-bit) or half-word (16bit) accesses to occur at smaller boundaries. An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possible to read or write the upper byte of a word register separately.

0xE020 0000 0xE01F FFFF

0xE000 0000

LPC2106/2105/2104 Memory Addressing 30 October 02, 2003

Philips Semiconductors Preliminary User Manual

LPC2106/2105/2104ARM-based Microcontroller

Vectored Interrupt Controller

(AHB peripheral #126)

(AHB peripheral #125)

(AHB peripheral #124)

(AHB peripheral #3)

(AHB peripheral #2)

0xFFFF F000 (4G - 4K)

0xFFFF C000

0xFFFF 8000

0xFFFF 4000

0xFFFF 0000

0xFFE1 000 0

0xFFE0 C000

(AHB peripheral #1)

(AHB peripheral #0)

Figure 4: AHB Peripheral Map

0xFFE0 800 0

0xFFE0 400 0

0xFFE0 000 0

LPC2106/2105/2104 Memory Addressing 31 October 02, 2003

Philips Semiconductors Preliminary User Manual

LPC2106/2105/2104ARM-based Microcontroller

System Control Block

(VPB peripheral #127) (VPB peripheral #126)

(VPB peripheral #16)

(VPB peripheral #15)

(VPB peripheral #14)

(VPB peripheral #13)

(VPB peripheral #12)

Pin Connect Block

(VPB peripheral #11)

GPIO

(VPB peripheral #10)

RTC

(VPB peripheral #9)

SPI

(VPB peripheral #8)

(VPB peripheral #7)

0xE01F FFFF 0xE01F C000

0xE01F 8000

0xE004 4000

0xE004 0000

0xE003 C000

0xE003 8000

0xE003 4000

0xE003 0000

0xE002 C000

0xE002 8000

0xE002 4000

0xE002 0000

0xE001 C000

(VPB peripheral #6)

PWM0

(VPB peripheral #5)

UART1

(VPB peripheral #4)

UART0

(VPB peripheral #3)

Timer1

(VPB peripheral #2)

Timer0

(VPB peripheral #1)

Watchdog Timer

(VPB peripheral #0)

Figure 5: VPB Peripheral Map

0xE001 8000

0xE001 4000

0xE001 0000

0xE000 C000

0xE000 8000

0xE000 4000

0xE000 0000

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LPC2106/2105/2104 MEMORY RE-MAPPING AND BOOT BLOCK

Memory Map Concepts and Operating Modes

The basic concept on the LPC21 06/2105/2 104 is t hat each mem ory area ha s a "natural " locatio n in the me mory map . This is th e address range for which code residing in that area is written. The bulk of each memory space remains permanently fixed in the same location, eliminating the need to have portions of the code designed to run in different address ranges.

Because of the location of the interrupt vectors on the ARM7 processor (at addresses 0x0000 0000 through 0x0000 001C, as shown in Table 2 below), a sma ll portion of the Boot Block and SRAM spa ces need to be re-ma pped in order to al low alternati ve uses of interrupts in the different operating modes described in Table 3. Re-mapping of the interrupts is accomplished via the Memory Mapping Control feature described in the System Control Block section.

Table 2: ARM Exception Vector Locations

Address Exception 0x0000 0000 Reset 0x0000 0004 Undefined Instruction 0x0000 0008 Software Interrupt 0x0000 000C Prefetch Abort (instruction fetch memory fault) 0x0000 0010 Data Abort (data access memory fault) 0x0000 0014 Reserved * 0x0000 0018 IRQ 0x0000 001C FIQ

*: Identified as reserved in ARM documentation, this location is used by the Boot Loader as the Valid User Program key.

Table 3: LPC2106/2105/2104 Memory Mapping Modes

Mode Activation Usage

Boot Loader

mode

User Flash

mode

User RAM

mode

Hardware activation

by any Reset

Software activation

by Boot code

Software activation

by User program

The Boot Loader always mapped to the bottom of memory to allow handling exceptions and using interrupts during the Boot Loading process.

Activated by Boot Loader w hen a valid User Progra m Signature is recogni zed in memory and Boot Loader operation is not forced. Interrupt vectors are not re-mapped and are found in the bottom of the Flash memory.

Activated by a User Program as de sir ed. In terru pt vectors are re-mapped to the bottom of the Static RAM.

executes after any reset. The Boot Block interrupt vectors are

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Memory Re-Mapping

In order to allo w for com patibili ty with future der ivativ es, the en tire Boot Block i s mapped to the top o f the on -chip mem ory space. In this manner, the use of larger or smaller flash modules will not require changing the location of the Boot Block (which would require changing the Boot Loader code itself ) or changing the mappin g of the Boot Block interru pt vectors. Memo ry spaces other than the interrupt vectors remain in fixed locations. Figure 6 shows the on-chip memory mapping in the modes defined above.

The portion of memory that is re-mapped to allow interrupt processing in different modes includes the interrupt vector area (32 bytes) and an addition al 32 bytes, for a total of 64 bytes. The re-mapped code locations ove rlay addresses 0x0000 0000 throu gh 0x0000 003F. A typical u ser progra m in th e Flash memory c an plac e the e ntire FIQ handler at addre ss 0x0000 001C without a ny need to consider memory boundaries. The vector contained in the SRAM, external memory, and Boot Block must contain branches to the actual interrupt handlers, or to other instructions that accomplish the branch to the interrupt handlers.

There are three reasons this configuration was chosen:

1. To give the FIQ handler in the Flash memory the advantage of not having to take a memory boundary caused by the remapping into account.

2. Minimize the need to for the SRAM and Bo ot Blo ck vec tors to deal with arbitrary boundaries in th e mi ddl e of code space.

3. To provide space to store constants for jumping beyond the range of single word branch instructions.

Re-mapped memory are as, includin g the Boot Block and interr upt vectors, con tinue to appear in their original loc ation in addition to the re-mapped address.

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0x8000 0000

2.0 GB

2.0 GB - 8K

8K byte Boot Block

(re-mapped from top of Flash memory)

(Boot Block interrupt vectors)

Reserved for

On-Chip Memory

0x7FFF FFFF

1.0 GB

On-Chip SRAM LPC2106: 64K byte (0x4000 FFFF) LPC2105: 32K byte (0x4000 7FFF) LPC2104: 16K byte (0x4000 3FFF)

(SRAM interrupt vectors)

(8k byte Boot Block re-Mapped to higher address range)

128K byte Flash Memory

0x4000 FFFF

0x4000 0000 0x3FFF FFFF

0x0001 FFFF

0.0 GB

Note: memory regions are not drawn to scale.

Active interrupt vectors (from Flash, SRAM, or Boot Block)

0x0000 0000

Figure 6: Map of lower memory is showing re-mapped and re-mappable areas.

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PREFETCH ABORT AND DATA ABORT EXCEPTIONS

The LPC2106/2105/2104 generates the ap propria te bus cycle abort exception if an access is attempte d for an address tha t is in a reserved or unassigned address region. The regions are:

• Areas of the memory map that are not implemented for a specific ARM derivative. For the LPC2106/2105/2104, this is:

- Address space betwee n On-Chip N on-V ol atile Memory and the Spec ial regist ers. Labelled "Reserved for On-Chip M emory" in Figure 2 and Figure 6.

- Address space between On-Chip Static RAM and External Memory. Labelled "Reserved for On-Chip Memory" in Figure 2.

- External Memory (since no external bus interface is implemented on the LPC2106/2105/2104).

- Reserved regions of the AHB and VPB spaces. See Figure 3.

• Unassigned AHB peripheral spaces. See Figure 4.

• Unassigned VPB peripheral spaces. See Figure 5. For these areas, both atte mpted data acc ess and inst ruction fetch gen erate an excep tion. In additi on, a Prefetch Abort exceptio n

is generated for any instruction fetch that maps to an AHB or VPB peripheral address. Within the addres s spa ce of an ex is tin g VPB peri pheral, a data abort exception is not ge nera t ed in res po ns e to an ac ce ss to an

undefined address. Address decoding within each peripheral is li mit ed to that needed to distinguish defined regist ers within the peripheral itself. Fo r example, an access to address 0xE0 00D000 (a n undefine d address wit hin the UART0 space) may result in an access to the register defined at address 0xE000C000. Details of such address aliasing within a peripheral space are not defined in the LPC2106/2105/2104 documentation and are not a supported feature.

Note that the ARM core stores the Prefetch Abort flag along with the associated instruction (which will be meaningless) in the pipeline and processes the abort only if an attempt is made to execute the instruction fetched from the illegal address. This prevents acciden tal abort s that co uld be ca used by prefetc hes tha t occur whe n co de is exec uted ve ry near a me mo ry boun dary.

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3. SYSTEM CONTROL BLOCK

SUMMARY OF SYSTEM CONTROL BLOCK FUNCTIONS

The System Control Block includes several system features and control registers for a number of functions that are not related to specific peripheral devices. These include:

• Crystal Oscillator.

• External Interrupt Inputs.

• Memory Mapping Control.

•PLL.

• Power Control.

•Reset.

• VPB Divider.

• Wakeup Timer. Each type of fu nction has it s own reg ister(s) if any are required and unnee ded bits a re define d as reserved i n order to allow future

expansion. Unrelated f unctions never share the same register addresses.

PIN DESCRIPTION

Table 4 shows pins that are associated with System Control block functions.

Table 4: Pin summary

Pin name Pin direction Pin Description

X1 Input Crystal Oscillator Input- Input to the oscillator and internal clock generator circuits. X2 Output Crystal Oscillator Output- Output from the oscillator amplifier.

External Interrupt Input 0- An ac tive low gene ral purpose interru pt input. This pin may be used to wake up the processor from Idle or Power down modes.

EINT0 Input

EINT1 EINT2 Input External Interrupt Input 2- See the EINT0 description above.

RST

Input External Interrupt Input 1- See the EINT0 description above.

Input

LOW level on this pin immediately after reset is considered as an external hardware request to start the ISP command ha ndler. More de tails on ISP and Flash memory can be found in "Flash Memory System and Programming" chapter.

External Reset input- A low on this pin resets the chi p, causing I/O ports and periphe rals to take on their default states, and the processor to begin execution at address 0.

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REGISTER DESCRIPTION

All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function.

Table 5: Summary of System Control Registers

Address Name Description Access

External Interrupts

0xE01FC140 EXTINT External interrupt flag register. R/W 0 0xE01FC144 EXTWAKE External interrupt wakeup register. R/W 0

Memory Mapping Control

0xE01FC040 MEMMAP Memory mappi ng con trol . R/W 0

Phase Locked Loop

0xE01FC080 PLLCON PLL control register. R/W 0 0xE01FC084 PLLCFG PLL configuration register. R/W 0 0xE01FC088 PLLSTAT PLL status register. RO 0

0xE01FC08C PLLFEED PLL feed register. WO NA

Power Control

0xE01FC0C0 PCON Power control register. R/W 0 0xE01FC0C4 PCONP Power control for peripherals. R/W 0x3BE

VPB Divider

0xE01FC100 VPBDIV VPB divider control. R/W 0

Reset

Value*

*Reset Value refers to the data stored in used bits only. It does not include reserved bits content.

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CRYSTAL OSCILLATOR

The oscillator supports crystals in the range of 10 MHz to 25 MHz. The oscillator output frequency is called F processor clock frequency is referred to as cclk for purposes of rate equations, etc. elsewhere in this document. F

and the ARM

osc

and cclk

osc

are the same value unless the PLL is running and connected. Refer to the PLL description in this chapter for details. Onboard oscillator in LPC2106/2105/2104 can operate in one of two modes: slave mode and oscillation mode. In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Cc in Figure 7, drawing a), with an

amplitude of at least 200 mVrms. X2 pin in this configuration can be left not connected. External components and models used in oscillation mode are shown in Figure 7, drawings b and c, and in Table 6. Since the

feedback resistance is integrated on chip, only a crystal and the capacitances C case of fundamental mode oscillati on (the fun damen tal freque ncy is repres ented by L, C drawing c, represents the par all el pa ck age capacitance and should not be larger than 7 pF. Para me ters F

and CX2 need to be connected externally in

and RS). Capacitance Cp in Figure 7,

, CL, RS and CP are

supplied by the crystal manufa ctu rer.

LPC2106/2105/2104

X1 X2

Clock

LPC2106/2105/2104

X1 X2

Xtal

<=>

a) b) c)

Figure 7: Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation,

c) external crystal model used for C

Table 6: Recommended values for C

Fundamental Oscillation

Frequency F

Capacitance C

10 - 15 MHz

15 - 20 MHz

20 - 25 MHz

when oscillation mode is used

X1/X2

Crystal Load

Max. Crystal Series

Resistence R

10 pF < 300 Ω 18 pF, 18 pF 20 pF < 220 Ω 38 pF, 38 pF 30 pF < 140 Ω 58 pF, 58 pF 10 pF < 220 Ω 18 pF, 18 pF 20 pF < 140 Ω 38 pF, 38 pF 30 pF < 80 Ω 58 pF, 58 pF 10 pF < 160 Ω 18 pF, 18 pF 20 pF < 90 Ω 38 pF, 38 pF 30 pF < 50 Ω 58 pF, 58 pF

X1/X2

evaluation

External Load

Capacitors C

, C

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EXTERNAL INTERRUPT INPUTS

The LPC2106/2105/2104 includes three External Interrupt Inputs as selectable pin functions. The External Interrupt Inputs can optionally be used to wake up the processor from Power Down mode.

Register Description

The external interrupt function has two registers associated with it. The EXTINT register contains the interrupt flags, and the EXTWAKEUP register contains bits that enable individual external interrupts to wake up the LPC2106/2105/2104 from Power Down mode.

Table 7: External Interrupt Registers

Address Name Description Access

0xE01FC140 EXTINT

0xE01FC144 EXTWAKE

The External Interrupt Flag reg ister contains interrupt fl ags for EINT0, EINT1, and EINT2. Se e Table 8.

The External Interrupt Wakeup register contains three enable bits that control whether each external inte rrupt will cause the processor to wake u p fro m Powe r Down mode. See Table 9.

R/W

EXTINT Register (EXTINT - 0xE01FC140)

When an external inte rrupt is mapped to its re lated pin, the prese nce of a logic zero on th at pin will set the co rresponding interrupt flag in the EXTINT register. This will cause the VIC to respond appropriately if that interrupt is enabled. Once the logic level on external interrupt pin(s) is set to 1, software may clear the flag(s) by writing a 1 to the corresponding bit(s) in EXTINT. Every attempt to reset EINT bit is futile as long as signal level on associated pin is 0.

Table 8: External Interrupt Flag Register (EXTINT - 0xE01FC140)

EXTINT Function Description

0EINT0

1EINT1

2EINT2

Set when external the EINT0 pin goes low and EINT0 is mapped to its related pin. Can be cleared by writing a 1 to this bi t after the log ic 1 appe ars on the relate d pin.

Set when external the EINT1 pin goes low and EINT1 is mapped to its related pin. Can be cleared by writing a 1 to this bi t after the log ic 1 appe ars on the relate d pin.

Set when external the EINT2 pin goes low and EINT2 is mapped to its related pin. Can be cleared by writing a 1 to this bi t after the log ic 1 appe ars on the relate d pin.

Reset Value

7:3 Reserved

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

EXTWAKE Register (EXTWAKE - 0xE01FC144)

Enable bits in the EXTWAKE register allow the external interrupts to wake up the processor if it is in Power Down mode. The related EINTn function must be mapped to the pin in order for the wakeup process to take place. It is not necessary for the interrupt to be enabled in the Vectored Interrupt Controller for a wakeup to take place. This arrangement allows additional capabilities, such as having an external interrupt input wake up the processor from Power Down mode without causing an interrupt (simply resuming operation), or allowing an interrupt to be enabled during Power Down without waking the processor up if it is asserted (eliminating the need to disable the interrupt if the wakeup feature is not desirable in the application).

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Table 9: External Interrupt Wakeup Register (EXTWAKE - 0xE01FC144)

EXTWAKE Function Description

0 EXTWAKE0 When one, assertion of EI NT0 1 EXTWAKE1 When one, assertion of EI NT1 2 EXTWAKE2 When one, assertion of EI NT2

7:3 Reserved

VPB Bus Data

EINTi

Reset

Write "1" fr om

VPB Bus Interface

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Wakeup Enable

(one bit of EXTWAKE)

pclk

will wake up the processor from Power Down mode. 0 will wake up the processor from Power Down mode. 0 will wake up the processor from Power Down mode. 0

VPB Read of EXTWAKE

Wakeup Timer

pclk pclk

EINTi to

(Figure 10)

Interrupt Flag

(one bit of EXTINT)

Reset Value

to VIC

VPB Read of EXTINT

Figure 8: External Interrupt Logic

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MEMORY MAPPING CONTROL

The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x00000000. This allows code running in different memory spaces to have control of the interrupts.

Memory Mapping Control Register (MEMMAP - 0xE01FC040)

Table 10: MEMMAP Register

Address Name Description Access

0xE01FC040 MEMMAP

Table 11: Memory Mapping Control Register (MEMMAP - 0xE01FC040)

MEMMAP Function Description

1:0 MAP1:0

7:2 Reserved

*: The hardware reset value of the MAP bits is 00 for LPC2106/2105/2104 parts. The ap parent reset va lue that the user will see will be altered by the Boot Loader code, which always runs initially at reset. User documentation will reflect this difference.

Memory mapping control. Selects whether the ARM interrupt vectors are read from the Flash Boot Block, User Flash or RAM.

00: Boot Loader Mode. Interrupt vectors are re-mapped to Boot Block. 01: User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. 10: User RAM Mode. Interrupt vectors are re-mapped to Static RAM. 11: Reserved. Should not be used.

Warning: Improper set tin g of t his v alue may result in inco rrect o perati on of the devi ce. Reserved, user software shou ld not write ones to reserved b its. The value rea d from a

reserved bit is not defined.

R/W

Reset

Value*

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PLL (PHASE LOCKED LOOP)

The PLL accepts a n inpu t clock frequen cy in the ran ge of 1 0 MH z to 2 5 MHz. The in put freq uen cy is m ultipl ied up into th e rang e of 10 MHz to 60 MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier val ue c ann ot be higher than 6 on the LPC 21 06/ 2105/2104 due to the upper fr equ enc y li mi t o f t he C PU ). T he C CO operates in the range of 156 MH z to 320 MHz, s o the re is an add iti onal divider in the loop to keep the CCO within its frequ enc y range while the PLL is pro viding the de sired output freq uency. The ou tput divider ma y be set to divi de by 2, 4, 8, or 16 t o produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50% duty cycle. A block diagram of the PLL is shown in Figure 9.

PLL activation is con trolled via the PLLC ON register. The PLL mu ltiplier and divider v alues are controlle d by the PLLCFG register. These two registers are protected in order to prevent accidental alteration of PLL parameters or deactivation of the PLL. Since all chip operations, including the Watchdog Timer, are dependent on the PLL when it is providing the chip clock, accidental changes to the PLL setup could result in unexpected behavior of the microcontroller. The protection is accomplished by a feed sequence similar to that of the Watchdog Timer. Details are provided in the description of the PLLFEED register.

The PLL is turned off and bypassed fol lowing a chip Reset and when by entering pow er Down mode. PLL is enabled by software only. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source.

Register Description

The PLL is controlled by the registers shown in Table 12. More detailed descriptions follow.

Warning: Improper setting of PLL values may result in incorrect operation of the device.

Table 12: PLL Registers

Address Name Description Access

0xE01FC080 PLLCON

0xE01FC084 PLLCFG

0xE01FC088 PLLSTAT

0xE01FC08C PLLFEED

Holding register for updati ng PLL control bits. Val ues written to this register d o not take effect until a valid PLL feed sequence has taken place.

Holding register for updating PLL configuration values. Values written to this register do not take effect until a valid PLL feed sequence has taken place.

Read-back register for PLL control and configuration information. If PLLCON or PLLCFG have been written to, but a PLL feed sequence has not yet occurred, they will not reflect th e current PLL state. Readi ng this register provides the actual values controlling the PLL, as well as the status of the PLL.

This register enables loading of the PLL control and configuration information from the PLLCON and PLLCFG registers into the shadow registers that actuall y affect PLL operation.

R/W

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PLLC

PLLE

OSC

PSEL[1:0]

PLOCK

MSEL[4:0]

Direct

pd Bypass

Phase-

Frequency

Detector

fout

CCO

Div-by-M

msel<4:0>

Clock

Synchronization

CCO

/2P

cclk

Figure 9: PLL Block Diagram

PLLCON Register (PLLCON - 0xE01FC080)

The PLLCON register contains the bits that enable and connect the PLL. Enabling the PLL allows it to attempt to lock to the current settings of th e m ul tipl ier and divider values. Conn ect ing the PLL ca us es the processor and all chip functions to run from the PLL output clock. Changes to the PLLCO N register d o not take effect until a co rrect PLL fee d sequen ce has be en given (se e PLLFEED Register (PLLFEED - 0xE01FC08C) description).

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Table 13: PLL Control Register (PLLCON - 0xE01FC080)

PLLCON Function Description

0 PLLE

1 PLLC

7:2 Reserved

The PLL must be set up, enabled, and Lock established before it may be used as a clock source. When switching from the oscillator clock to the PLL output or vice versa, internal circuitry synchronizes the operation in order to ensure that glitches are not generated. Hardw are does not insu re that the PLL is lo cked bef ore it is c onnected or autom atically di sconnec t the PLL i f lock is lost during opera tion. In the event of l oss of PLL lock, it i s likely that the o scillator clock has become uns table and disconnecting the PLL will not remedy the situation.

PLL Enable. When one, and after a valid PLL feed, this bit will activate the PLL and allow it to lock to the requested frequency. See PLLSTAT register, Table 15.

PLL Connect. When PLLC and PLLE are both set to one, and after a valid PLL feed, connects the PLL as the clock source for the LPC2106/2105/2104. Otherwise, the oscillator clock is used directly by the LPC2106/2105/2104. See PLLSTAT register, Table 15.

Reserved, user software shou ld not write ones to reserved b its. The value rea d from a reserved bit is not defined.

Reset Value

PLLCFG Register (PLLCFG - 0xE01FC084)

The PLLCFG register contains the PLL multiplier and divider values. Changes to the PLLCFG register do not take effect until a correct PLL feed sequence ha s been given (see PLLFEED Reg ister (PLLFEED - 0xE01FC08C) de scription). Calculati ons for the PLL frequency, and multiplier and divider values are found in the PLL Frequency Calculation section.

Table 14: PLL Configuration Register (PLLCFG - 0xE01FC084)

PLLCFG Function Description

4:0 MSEL4:0 PLL Multiplier value. Supplies the value "M" in the PLL frequency calculations. 0 6:5 PSEL1:0 PLL Divider value. Supplies the value "P" in the PLL frequency calculations. 0

7 Reserved

Reserved, user software shou ld not write ones to reserved b its. The value rea d from a reserved bit is not defined.

Reset Value

PLLSTAT Register (PLLSTAT - 0xE01FC088)

The read-only PLLSTAT register provides the actual PLL parameters that are in effect at the time it is read, as well as the PLL status. PLLSTAT may disa gree with values foun d in PLLCON and PLLCFG beca use changes to those re gisters do not take effe ct until a proper PLL feed has occurred (see PLLFEED Register (PLLFEED - 0xE01FC08C) description).

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Table 15: PLL Status Register (PLLSTAT - 0xE01FC088)

PLLSTAT Function Description

4:0 MSEL4:0 Read-back for the PLL Multiplier value. This is the value currently used by the PLL. 0 6:5 PSEL1:0 Read-back for the PLL Divider value. This is the value currently used by the PLL. 0

7 Reserved

8 PLLE

9 PLLC

10 PLOCK

15:11 Reserved

PLL Interrupt

The PLOCK bit in the PLLSTAT register is connected to the interrupt controller. This allows for software to turn on the PLL and continue with other fun ctions without having to wait for the PLL to ach ieve lock. Wh en the interru pt occurs (PLOCK = 1), the PLL may be connected, and the interrupt disabled.

Reserved, user software shou ld not write ones to reserved bits. The value rea d from a reserved bit is not defined.

Read-back for the PLL Enable bit. When one, the PLL is currently activated. When zero, the PLL is turne d off. This bit is aut omatically cleared w hen Power Do wn mode is activated.

Read-back for the PLL Conne ct bit. W hen PLLC an d PLL E are b oth one , the PLL is connected as the clock source for the LPC2106/2105/2104. When zero, the PLL is bypassed and the oscillator clock is used directly by the LPC2106/2105/2104. This bit is automatically cleared when Power Down mode is activated.

Reflects the PLL Lock status . When zero , the PLL is no t locked. Wh en one, the PLL is locked onto the requested frequency.

Reserved, user software shou ld not write ones to reserved bits. The value rea d from a reserved bit is not defined.

Reset Value

PLL Modes

The combinations of PLLE and PLLC are shown in Table 16.

Table 16: PLL Control Bit Combinations

PLLC PLLE PLL Function

0 0 PLL is turned off and disconnected. The system runs from the unmodified clock input. 0 1 The PLL is active, but not yet connected. The PLL can be connected after PLOCK is asserted.

1 1 The PLL is active and has been connected as the system clock source.

Same as 0 0 combination. This preven ts the possibility of the PLL bei ng connected without als o being enabled.

PLLFEED Register (PLLFEED - 0xE01FC08C)

A correct feed sequence mus t be written to the PLLFEED regi ster in o rder for chang es to the PLLCO N and PLLCFG reg isters to take effect. The feed sequence is:

1. Write the value 0xAA to PLLF EED

2. Write the value 0x55 to PLLFEED.

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The two writes must be in the correct sequence, and must be consecutive VPB bus cycles. The latter requirement implies that interrupts must be disabled for the duration of the PLL feed operation. If either of the feed values is incorrect, or one of the previously mentioned conditions is not met, any changes to the PLLCON or PLLCFG register will not become effective.

Table 17: PLL Feed Register (PLLFEED - 0xE01FC08C)

PLLFEED Function Description

7:0 PLLFEED

The PLL feed sequence must be written to this register in order for PLL configuration and control register changes to take effect.

Reset Value

undefined

PLL and Power Down Mode

Power Down mode automatically turns off and disconnects the PLL. Wakeup from Power Down mode does not automatically restore the PLL settings, this must be done in software. Typically, a routine to activate the PLL, wait for lock, and then connect the PLL can be called at the begin nin g of any i nterrupt service ro utin e that migh t be cal led due to the w akeup . It is import ant not to attempt to restart the PLL by simply feeding it when execution resumes after a wakeup from Power Down mode. This would enable and connect the PLL at the same time, before PLL lock is established.

PLL Frequency Calculation

The PLL equations use the following parameters: F

OSC

CCO

cclk the PLL output frequency (also the processor clock frequency) M PLL Multiplier value from the MSEL bits in the PLLCFG register P PLL Divider value from the PSEL bits in the PLLCFG register

the frequency from the crystal oscillator the frequency of the PLL current controlled oscillator

The PLL output frequency (when the PLL is both active and connected) is given by: F

cclk = M * F

or cclk = ———

osc

cco

2 * P

The CCO frequency can be computed as: F

= cclk * 2 * P or F

cco

= F

* M * 2 * P

osc

The PLL inputs and settings must meet the following:

•F

is in the range of 10 MHz to 25 MHz.

osc

• cclk is in the range of 10 MHz to F is in the range of 156 MHz to 320 MHz.

•F

cco

(the maximum allowed frequency for the LPC2106/2105/2104).

max

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Procedure for Determining PLL Settings

If a particular application uses the PLL, its configuration may be determined as follows:

1. Choose the desired processor operating frequency (cclk). This may be based on processor throughput requirements, need to support a spec ific set o f UART baud rates, etc. Be ar i n mind that periph eral d evices ma y be runnin g from a low er clock than the processor (see the VPB Divider description in this chapter).

2. Choose an oscillator frequency (F

3. Calculate the value of M to configure the MSEL bits. M = cclk / F to the MSEL bits in PLLCFG is M - 1 (see Table 19).

4. Find a value for P to config ure the PSEL b its , suc h t hat F the equation given abov e. P must have on e of the valu es 1, 2, 4, or 8. Th e value writt en to the PSEL bits in PL LCFG is 00

). cclk must be an even multiple of F

osc

is within its defined frequency lim its. F

cco

. M must be in the rang e of 1 to 32 . Th e va lue w ritte n

for P = 1; 01 for P = 2; 10 for P = 4; 11 for P = 8 (see Table 18).

Table 18: PLL Divider Values

osc

is calculated us ing

cco

PSEL Bits

(PLLCFG bits 6:5)

00 1 01 2 10 4 11 8

Table 19: PLL Multiplier Values

MSEL Bits

(PLLCFG bits 4:0)

00000 1 00001 2 00010 3 00011 4

... ...

11110 31 11111 32

Value of P

Value of M

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POWER CONTROL

The LPC2106/2105/2104 supports two reduced power modes: Idle mode and Power Down mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses.

In Power Down mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power Down mode and the logic levels of chip pins remain static. The Power Down mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power Down mode reduces chip power consumption to nearly zero.

Wakeup from Power Down or I dle modes via an interru pt re sumes pr ogram execu tion in suc h a way that no instruc tions are l ost, incomplete, or repeated. Wake up from Power Down mode is discussed further in the description of the Wakeup Timer later in this chapter.

A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings.

Register Description

The Power Control function contains two registers, as shown in Table 20. More detailed descriptions follow.

Table 20: Power Control Registers

Address Name Description Access

0xE01FC0C0 PCON

0xE01FC0C4 PCONP

Power Control Register. This register contains control bits that enable the two reduced power operating modes of the LPC2106/2105/2104. See Table 21.

Power Control for Peripherals Register. This register contains control bits that enable and disable indiv idual pe riphera l functi ons, Allo wing elim inati on of pow er consumption by peripherals that are not needed. See Table 22.

R/W

PCON Register (PCON - 0xE01FC0C0)

The PCON register contai ns two bits. Writin g a one to the corres ponding bit ca uses entry to eithe r the Power Down or Idle mode. If both bits are set, Power Down mode is entered.

Table 21: Power Control Register (PCON - 0xE01FC0C0)

PCON Function Description

Idle mode - when set, this bit causes the processor clock to be stopped, while on-chip

0IDL

peripherals remain activ e. Any enabled interrupt from a peripheral or an ex ternal interrupt source will cause the processor to resume execution.

Reset Value

Power Down mode - when set, th is bit c au ses the osc il lat or an d al l on-chip clocks to be

1PD

7:2 Reserved

stopped. A wakeup condition from an external interrupt can cause the oscillator to restart, the PD bit to be cleared, and the processor to resume execution.

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

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Power Control for Peripherals Register (PCONP - 0xE01FC0C4)

The PCONP register all ows turn ing off selec ted pe riphera l func tions for the p urpose of sa ving pow er. A few p eriphe ral fun ctions cannot be turned off (i.e. the Watchdog timer, GPI O, the Pin Connect block, and the System Control block). Each bit in PCO NP controls one periphe ral as shown in Ta ble 22. The b it numbers corre spond to the rela ted peripheral number as shown in the VPB peripheral map in the LPC2106/2105/2104 Memory Addressing section.

Table 22: Power Control for Peripherals Register (PCONP - 0xE01FC0C4)

PCONP Function Description

0 Reserved

1 PCTIM0 When 1, Timer 0 is enabled. When 0, Timer 0 is disabled to conserve power. 1 2 PCTIM1 When 1, Timer 1 is enabled. When 0, Timer 1 is disabled to conserve power. 1 3 PCURT0 When 1, UART 0 is enabled. When 0, UART 0 is disabled to conserve power. 1 4 PCURT1 When 1, UART 1 is enabled. When 0, UART 1 is disabled to conserve power. 1 5 PCPWM0 When 1, PWM 0 is enabled. When 0, PWM 0 is disabled to conserve power. 1

6 Reserved

7PCI2C

8 PCSPI

9 PCRTC When 1, the RTC is enabled. When 0, the RTC is disabled to conserve power. 1

31:10 Reserved

Reserved, user software shou ld not write ones to reserved b its. The value rea d from a reserved bit is not defined.

User software should not write ones to reserved bits. The value read from a reserved bit is not defined.

When 1, the I power.

When 1, the SPI int erface is enabled . When 0, the SP I interface is disabled to cons erve power.

Reserved, user software shou ld not write ones to reserved b its. The value rea d from a reserved bit is not defined.

C interface is enable d. When 0, the I2C interface is disabl ed to conserve

Reset Value

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RESET

Reset has t wo sourc es on the LP C2106/2105 /2104: t he RS T pin and Wat chdog Reset. The RST pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip Reset by any source starts the Wakeup Timer (see Wakeup Timer description later in this chapter), causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the Flash controller has completed its initialization. The relationship between Reset, the oscillator, and the Wakeup Timer are shown in Figure 10.

The Reset glitch fi lter al lows th e proce ssor t o igno re exte rnal res et pul ses that a re very short , and al so de termin es the minim um duration of RST crystal oscillator is fully running and an adequate signal is present on the X1 pin of the LPC2104/2105/2106. Assuming that an external crystal is used in the crystal oscillator subsystem, after power on, the RST subsequent resets when crysta l osil lator is already runnin g and sta ble si gnal is on the X1 pi n, the R ST for 300 ns only.

When the internal Rese t is remo ve d, the proces sor beg ins ex ecuti ng at addr ess 0, w hich is the Res et vect or. At that p oint, al l of the processor and peripheral registers have been initialized to predetermined values.

External and internal Resets have some small differences. An external Reset causes the value of certain pins to be latched to configure the part. External circuitry cannot determine when an internal Reset occurs in order to allow setting up those special pins, so those latches are not reloaded during an internal Reset. Pins that are examined during an external Reset for various purposes ar e: DBGSEL, RT CK, and EINT0.

that must be asserted in ord er to gu arantee a chi p rese t. Once a sserted, R ST pin c an be d eass erted on ly whe n

pin should be asserted for 10 ms. For all

pin needs to be asserted

It is possible for a chip Reset to occur during a Flash programming or erase operation. The Flash memory will interrupt the ongoing operation and hold off the completion of Reset to the CPU until internal Flash high voltages have settled.

External

Reset

Reset to

Flash

Memory

Reset to

PCON.PD

Wakeup Timer

Start Count 2

Write "1"

from VPB

Reset

VPB Read

of PDbit

in PCON

OSC

CPU

Watchdog

Reset

Power Down

EINT0 Wakeup EINT1 Wakeup EINT2 Wakeup

Oscillator

Output (F

OSC

)

PLL

Figure 10: Reset Block Diagram including Wakeup Timer

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VPB DIVIDER

The VPB Divider determines the relationshi p between the processor cl ock (cclk) and the clock used by peripheral devices (pcl k). The VPB Divider serves t wo purpo ses. The fi rst is to p rovides peripheral s with desi red pclk v ia VPB bus so that th ey can operate at the speed c hosen for the ARM p roces sor. In order to ac hieve this, the VP B bu s ma y be slowed d own to one ha lf or one fo urth of the processor clock ra te. Beca use the VPB bu s must work prope rly at po wer up (an d its ti ming can not be a ltered i f it doe s not work since the VPB divider control registers reside on the VPB bus), the default condition at reset is for the VPB bus to run at one quarter speed. The se co nd p urpo se of the VPB Div ide r is to all ow p ower sav in gs when an app lic at ion do es not require any peripherals to run at the full processor rate.

The connection of the VPB Divider relative to the oscillator and the processor clock is shown in Figure 11. Because the VPB Divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode.

VPBDIV Register (VPBDIV - 0xE01FC100)

The VPB Divider register contains two bits, allowing three divider values, as shown in Table 24.

Table 23: VPBDIV Register Map

Address Name Description Access

0xE01FC100 VPBDIV Controls the rate of the VPB clock in relation to the processor clock. R/W

Table 24: VPB Divider Register (VPBDIV - 0xE01FC100)

VPBDIV Function Description

The rate of the VPB clock is as follows: 0 0: VPB bus clock is one fourth of the processor clock. 0 1: VPB bus clock is the same as the processor clock.

1:0 VPBDIV

7:2 Reserved

1 0: VPB bus clock is one half of the processor clock. 1 1: Reserved. If this value is written to the VPBDIV register, it has no effect (the previous setting is retained).

Reserved, user software shou ld not write ones to reserved b its. The value rea d from a reserved bit is not defined.

Reset Value

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Crystal Oscillator

External Clock Source

)

osc

PLL

Processor Clock

(cclk)

VPB Divider

Figure 11: VPB Divider Connections

VPB Clock

(pclk)

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WAKEUP TIMER

The purpose of the wakeup timer is to ensure that the oscillator and other analog functions required for chip operation are fully functional before the pr ocessor is allowed to e xecute instructi ons. This is important at power on, all types of R eset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power Down mode, any wakeup of the processor from Power Down mode makes use of the Wakeup Timer.

The Wakeup Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or som e event ca used th e chip to exit Pow er down mode, som e time i s requir ed for the o scillato r to produce a signal of su fficie nt amplitud e to dr ive the c lock logi c. The am ount of tim e depe nds on m any fac tors, inclu din g the rate of Vdd ramp (in the cas e o f po w er on ), th e ty pe of c ry sta l a nd i ts ele ctri ca l characteristics (if a quartz crystal is us ed), as well as any other external circuit ry (e.g. cap acitor s), and the c haracte ristics of th e oscil lator its elf unde r the exis ting ambien t conditions.

Once a clock is detected, the Wakeup Timer counts 4096 clocks, then enables the Flash memory to initialize. When the Flash memory initialization is complete, the processor is released to execute instructions if the external Reset has been de-asserted. In the case where an external clock source is used in the system (as opposed to a crystal connected to the oscillator pins), the possibility that there could be l ittle or no d elay for oscilla tor start-up m ust be consi dered. The Wake up Timer desi gn then ensures that any other required chip functions will be operational prior to the beginning of program execution.

The LPC2106/2105/2104 does not contain any analog function such as comparators that operate without clocks or any independent clo ck source such as a dedica ted Watchdog o scillator. The on ly remaining functions that can operate i n the absence of a clock source are the exter nal interru pts, EINT 0, EIN T1, and EINT2 . If the extern al int errupt i s ena bled to cause wake up and becomes active (is driven low externally), an oscillator wakeup must be initiated. If the interrupt is also enabled in the Vectored Interrupt Controller, the completion of interrupt processing is postponed until the wakeup timer expires.

To summarize: on th e LPC2106/2105/210 4, the Wakeup Time r enforces a minimum res et duration based o n the crystal oscill ator, and is activated whenever there is a wakeup from Power Down mode or any type of Reset.

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4. MEMORY ACCELERATOR MODULE (MAM)

INTRODUCTION

Simply put, the Memory Accelerator Module (MAM) attempts to have the next ARM instruction that will be needed in its latches in time to prevent CPU fetch stal ls. The me thod used is to split the Flash memory into two banks, eac h cap abl e of ind ep endent accesses. Each of the two Flas h bank s has i ts own pref etch Buff er and Bran ch Trail Buffe r. The Branch Tra il Buffers for the two banks capture two 128-b it l ine s of Fl as h da ta whe n an In struction Fetch is not satisfied by either the Prefetch buffer nor Branch Trail buffer for its bank, and for which a prefetch has not been initiated. Each prefetch buffer captures one 128-bit line of instructions from its Flash bank, at the conclusion of a prefetch cycle initiated speculatively by the MAM.

Each 128 bit value includes four 32-bit ARM instructions or eight 16-bit Thumb instructions. During sequential code execution, typically one Flash bank contains or is fetching the current instruction and the entire Flash line that contains it. The other bank contains or is prefetching the next sequential code line. After a code line delivers its last instruction, the bank that contained it begins to fetch the next line in that bank.

Timing of Flash read operations is programmable and is described later in this section as well as in the System Control Block section.

Branches and othe r pro gram f low c ha nges cause a break in the seq uential flow of instruction fe tch es de sc rib ed a bo ve. When a backward branch occurs, there is a distinct possibility that a loop is being executed. In this case the Branch Trail Buffers may already contain the target instruction. If so, execution continues without the need for a Flash read cycle. For a forward branch, there is also a chance that the new addres s is alre ady contai ned in one of the Pref etch Buff ers. If it is, t he branch is again taken with no delay.

When a branch outsi de the c onten ts of the Branch Trail an d Prefetc h buffe rs is ta ken, one Fl ash Acces s cy cle is neede d to loa d the Branch Trail buffers . Subseq uently , there w ill typic ally b e no furthe r fetch de lays until ano ther suc h “Instr uction Miss ” occurs.

The Flash memory controller detects data accesses to the Flash memory and uses a separate buffer to store the results in a manner similar to that us ed during code fetches . This allows faster acces s to data if it is accessed sequ entially. A single li ne buffer is provided for data accesses, as opposed to the two buffers per Flash bank that are provided for code accesses. There is no prefetch function for data accesses.

Memory Accelerator Module Blocks

The Memory Accelerator Module is divided into several functional blocks:

• A Flash Address Latch for each bank. An Incrementer function is associated with the Bank 0 Flash Address latch.

• Two Flash Memory Banks.

• Instruction Latches, Data Latches, Address Comparison latches.

•Wait logic Figure 12 shows a simplified block diagram of the Memory Accelerator Module data paths.

In the following de scription s, the term “fe tch” appl ies to an explicit Fl ash read request fro m the ARM. “ prefetch” i s used to denote a Flash read of instructions beyond the current processor fetch address.

Flash Memory Banks

There are two banks of Flash memory in order to allow two parallel accesses and eliminate delays for sequential accesses.

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Flash programming oper ations are not con trolled by the Me mory Ac celera tor Modu le, but are handle d as a sep arate fun ction. A “boot block” sector contains Flash programming algorithms that may be called as part of the application program, and a loader that may be run to allow serial programming of the Flash memory.

The Flash memories are wired so that each sector exists in both banks, such that a sector erase operation acts on part of both banks simultaneously. In effect, the existence of two banks is transparent to the programming functions.

Memory Address

Flash Memory

ARM Local Bus

Figure 12: Simplified Block Diagram of the Memory Accelerator Module

Bus

Interface

Bank 0

Selection

Memory Data

Flash Memory

Bank 1

Bank

Instruction Latches and Data Latches

Code and Data accesses are treated separately by the Memory Accelerator Module. There are two sets of 128-bit Instruction Latches and 12 -bit Com parison Address Latches assoc iated with each Flash Bank . On e o f the two sets, called the Branch Trail Buffer, holds the data and comparison address for that bank from the last Instruction miss. The other set, called the Prefetch Buffer, holds the data and comparison address from prefetches undertaken speculatively by the MAM. Each Instruction Latch holds 4 words of code (4 ARM instructions, or 8 Thumb instructions).

Similarly there i s a 1 28-bit Data La tch and 1 3-bit Data Addr ess latch, tha t are u sed d uring D ata cycl es. This sing le se t of latches is shared by bot h Flas h bank s. Eac h Data a cces s that is not in the Data latch caus es a F lash f etch o f 4 wo rds of data, wh ich ar e captured in the Data latch. This speeds up sequential Data operations, but has little or no effect on random accesses.

Flash Programming Issues

Since the Flash memory does not al low accesses durin g programming and erase op erations, it is necessar y for the MAM to force the CPU to wait if a memory access to a Flash address is requested while the Flash module is busy. (This is accomplished by asserting the ARM7 TDMI-S local bu s signal CLKEN. ) Under some cond itions, this de lay could resu lt in a Watchdog time-out. The user will need to be a ware of this pos sibilit y and take s teps to insu re that an unw anted Watc hdog reset d oes not cau se a system failure while programming or erasing the Flash memory.

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In order to preclude the possibility of stale data being read from the Flash memory, the MAM holding latches are automatically invalidated at the be ginning of any Fl ash programming o r erase operation . Any subsequen t read from a Flash ad dress will cause a new fetch to be initiated after the Flash operation has completed.

MEMORY ACCELERATOR MODULE OPERATING MODES

Three modes of operation are defined for the MAM, trading off performance for ease of predictability:

0) MAM off. All memory requests result in a Flash read operation (see note 2 below). There are no instruction prefetches.

1) MAM partially ena bl ed. Sequential instruction acc ess es a r e fu lfi lle d f r om the ho ld ing la tches if the data is present. In st ruction prefetch is enabled. Non-sequential instruction accesses initiate Flash read operations (see note 2 below). This means that all branches cause mem ory fe tches . All dat a opera tions c ause a Flash rea d b ecause bu ffe red data acce ss timin g is ha rd to pre dict and is very situation dependent.

2) MAM fully enabled . Any memory request (code or data) for a value that is contai ned in one of the correspondi ng holding latches is fulfilled from the latch. Instruction prefetch is enabled. Flash read operations are initiated for instruction prefetch and code or data values not available in the corresponding holding latches.

Table 25: MAM Responses to Program Accesses of Various Types

Program Memory Request Type

MAM Mode

012

Sequential access, data in MAM latches Initiate Fetch

Use Latched Data Sequential access, data not in MAM latches Initiate Fetch Initiate Fetch Non-Sequential access, data in MAM latches Initiate Fetch

Initiate Fetch

Non-Sequential access, data not in MAM latches Initiate Fetch Initiate Fetch

1, 2

Use Latched Data

Initiate Fetch

Use Latched Data

Initiate Fetch

Table 26: MAM Responses to Data and DMA Accesses of Various Types

MAM Mode

Data Memory Request Type

012

Sequential access, data in MAM latches Initiate Fetch

Initiate Fetch

Use Latched Data Sequential access, data not in MAM latches Initiate Fetch Initiate Fetch Initiate Fetch Non-Sequential access, data in MAM latches Initiate Fetch

Initiate Fetch

Use Latched Data Non-Sequential access, data not in MAM latches Initiate Fetch Initiate Fetch Initiate Fetch

1. Instruction prefetch is enabled in modes 1 and 2.

2. The MAM actually uses latch ed data if it i s availa ble, but mimics the t iming of a F lash read o peratio n. This saves power whil e resulting in the same execution timing. The MAM can truly be turned off by setting the fetch timing value in MAMTIM to one clock.

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MAM CONFIGURATION

After reset the MAM defaults to the disabled state. Software can turn memory access acceleration on or off at any time. This allows most of an application to be run at the highest possible performance, while certain functions can be run at a somewhat slower but more predictable rate if more precise timing is required.

REGISTER DESCRIPTION

All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function.

Table 27: Summary of System Control Registers

Address Name Description Access

MAM

Memory Accelerator Module Control Register. Determines the MAM

0xE01FC000 MAMCR

0xE01FC004 MAMTIM

*Reset Value refers to the data stored in used bits only. It does not include reserved bits content.

functional mode, that is, to what extent the MAM performance enhancements are enabled. See Table 28.

Memory Accelerator Module Timing control. Determines the number of clocks used for Flash memory fetches (1 to 7 processor clocks).

Reset

Value*

R/W 0

R/W 0x07

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MAM Control Register (MAMCR - 0xE01FC000)

Two configuration bits select the three MAM operating modes, as shown in Table 28. Following Reset, MAM functions are disabled. Changing the MAM operating mode causes the MAM to invalidate all of the holding latches, resulting in new reads of Flash information as required.

Table 28: MAM Control Register (MAMCR - 0xE01FC000)

MAMCR Function Description

These bits determine the operating mode of the MAM as follows:

1:0

7:2 Reserved

MAM mode

control

0 0 - MAM functions disabled. 0 1 - MAM functions partially enabled. 1 0 - MAM functions fully enabled. 1 1 - reserved

Reserved, user software shou ld not write ones to reserved b its. The value rea d from a reserved bit is not defined.

Reset Value

MAM Timing Register (MAMTIM - 0xE01FC004)

The MAM Timing regis ter determines how many cclk cycles are used to acces s the Flash memory. This al lows tuning MAM timing to match the processor operating frequency. Flash access times from 1 clock to 7 clocks are possible. Single clock Flash accesses would esse ntially remove the MAM from timing c alc ul ations. In this case the MAM mode may be se lected to optimize power usage.

Table 29: MAM Timing Register (MAMTIM - 0xE01FC004)

MAMTIM Function Description

These bits set the duration of MAM Flash fetch operations as follows: 0 0 0 = 0 - Reserved. 0 0 1 = 1 - MAM fetch cycles are 1 processor clock (cclk) in duration. 0 1 0 = 2 - MAM fetch cycles are 2 processor clocks (cclks) in duration. 0 1 1 = 3 - MAM fetch cycles are 3 processor clocks (cclks) in duration. 1 0 0 = 4 - MAM fetch cycles are 4 processor clocks (cclks) in duration. 1 0 1 = 5 - MAM fetch cycles are 5 processor clocks (cclks) in duration. 1 1 0 = 6 - MAM fetch cycles are 6 processor clocks (cclks) in duration. 1 1 1 = 7 - MAM fetch cycles are 7 processor clocks (cclks) in duration.

2:0

MAM Fetch

Cycle timing

Reset Value

0x07

Warning: Improper set tin g of t his v alue may result in inco rrect o perati on of the devi ce.

7:3 Reserved

Reserved, user software shou ld not write ones to reserved b its. The value rea d from a reserved bit is not defined.

MAM USAGE NOTES

When changing M AM timing, the MAM must first be turned off by writing a zero to M A MCR . A ne w va lue ma y then be written to MAMTIM. Finally, the MAM may be turned on again by writing a value (1 or 2) corresponding to the desired operating mode to MAMCR.

For system cloc k sl ower than 2 0 MH z, MA MTIM c an be 0 01. For s ystem clock betw een 20 M Hz and 40 M Hz , Flas h ac cess ti me is suggested to be 2 CCLKs, while in systems with system clock faster than 40 MHz, 3 CCLKs are proposed.

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5. VECTORED INTERRUPT CONTROLLER (VIC)

FEATURES

• ARM PrimeCell™ Vectored Interrupt Controller

• 32 interrupt request inputs

• 16 vectored IRQ interrupts

• 16 priority levels dynamically assigned to interrupt requests

• Software interrupt generation

DESCRIPTION

The Vectored Interrupt Con troller (VIC) takes 32 interrupt reque st inputs and p rogrammably assig ns them into 3 cate gories, FIQ, vectored IRQ, and non-vectored IR Q. The program mable assig nment sche me means that priorities of interrupts from the v arious peripherals can be dynamically assigned and adjusted.

Fast Interrupt reQuest (FIQ) requests have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, be caus e then the FIQ service rout ine can si mply start de aling with that de vice . But if m ore th an one requ est is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs hav e the midd le priorit y. Sixt een of the 32 reques ts can be as signe d to th is ca tegory. Any of the 32 reques ts ca n be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority. The VIC ORs the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The

IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are requesting, the VIC provides the address of the highe st-priority requesting IR Qs service routine, otherwis e it provides the address of a default routine that is shared by al l the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active.

All registers in the VIC are word registers. Byte and halfword reads and write are not supported. Additional information on the Vectored Interrupt Controller is available in the ARM PrimeCell™ Vectored Interrupt Controller

(PL190) documentation.

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REGISTER DESCRIPTION

The VIC implements the registers shown in Table 30. More detailed descriptions follow.

Table 30: VIC Register Map

Address Name Description Access

0xFFFF F000 VICIRQStatus

0xFFFF F004 VICFIQStatus

0xFFFF F008 VICRawIntr

0xFFFF F00C VICIntSelect

0xFFFF F010 VICIntEnable

0xFFFF F014 VICIntEnClr

0xFFFF F018 VICSoftInt

0xFFFF F01C VICSoftIntClear

0xFFFF F020 VICProtection

IRQ Status Register. This register reads out the state of those interrupt requests that are enabled and classified as IRQ.

FIQ Status Requests. This register reads out the state of those interrupt requests that are enabled and classified as FIQ.

Raw Interrupt Status Register. This register reads out the sta te of the 32 interrupt requests / software interrupts, regardless of enabling or classification.

Interrupt Select Registe r. This regis ter classifi es each of the 32 interrupt requests as contributing to FIQ or IRQ.

Interrupt Enable Register. This register controls which of the 32 interrupt requests and software interrupts are enabled to contribute to FIQ or IRQ.

Interrupt Enable Clear Register. This register allows software to clear one or more bits in the Interrupt Enable register.

Software Interrupt Register . The co ntents of this register are ORed with the 32 interrupt requests from various peripheral functions.

Software Interrupt Clear Regis ter. Thi s regis ter all ows sof tware to c lear one or more bits in the Software Interrupt register.

Protection enable register. This registe r allows limiting access to the VIC registers by software running in privileged mode.

Reset

Value*

RO 0

R/W 0

0xFFFF F030 VICVectAddr

0xFFFF F034 VICDefVectAddr

0xFFFF F100 VICVectAddr0

0xFFFF F104 VICVectAddr1 Vector address 1 register R/W 0 0xFFFF F108 VICVectAddr2 Vector address 2 register R/W 0

0xFFFF F10C VICVectAddr3 Vector address 3 register R/W 0

0xFFFF F110 VICVectAddr4 Vector address 4 register R/W 0 0xFFFF F114 VICVectAddr5 Vector address 5 register R/W 0 0xFFFF F118 VICVectAddr6 Vector address 6 register R/W 0

0xFFFF F11C VICVectAddr7 Vector address 7 register R/W 0

0xFFFF F120 VICVectAddr8 Vector address 8 register R/W 0 0xFFFF F124 VICVectAddr9 Vector address 9 register R/W 0

Vector Address Register. When an IRQ interrupt occurs, the IRQ service routine can read this register and jump to the value read.

Default Vector Add res s Register. This register holds the address of the Interrupt Service routine (ISR) for non-vectored IRQs.

Vector address 0 register. Vector Address Registers 0-15 hold the addresses of the Interrupt Service routines (ISRs) for the 16 vectored IRQ slots.

R/W 0

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Table 30: VIC Register Map

Address Name Description Access

0xFFFF F128 VICVectAddr10 Vector address 10 register R/W 0

0xFFFF F12C VICVectAddr11 Vector address 11 register R/W 0

0xFFFF F130 VICVectAddr12 Vector address 12 register R/W 0 0xFFFF F134 VICVectAddr13 Vector address 13 register R/W 0 0xFFFF F138 VICVectAddr14 Vector address 14 register R/W 0

0xFFFF F13C VICVectAddr15 Vector address 15 register R/W 0

Vector control 0 re gister. Vector Control Registers 0-15 eac h control one

0xFFFF F200 VICVectCntl0

0xFFFF F204 VICVectCntl1 Vector control 1 register R/W 0 0xFFFF F208 VICVectCntl2 Vector control 2 register R/W 0

0xFFFF F20C VICVectCntl3 Vector control 3 register R/W 0

0xFFFF F210 VICVectCntl4 Vector control 4 register R/W 0 0xFFFF F214 VICVectCntl5 Vector control 5 register R/W 0 0xFFFF F218 VICVectCntl6 Vector control 6 register R/W 0

0xFFFF F21C VICVectCntl7 Vector control 7 register R/W 0

0xFFFF F220 VICVectCntl8 Vector control 8 register R/W 0

of the 16 vectored IRQ slots. Slot 0 has the highest priority and slot 15 the lowest.

R/W 0

Reset

Value*

0xFFFF F224 VICVectCntl9 Vector control 9 register R/W 0 0xFFFF F228 VICVectCntl10 Vector control 10 register R/W 0

0xFFFF F22C VICVectCntl11 Vector control 11 register R/W 0

0xFFFF F230 VICVectCntl12 Vector control 12 register R/W 0 0xFFFF F234 VICVectCntl13 Vector control 13 register R/W 0 0xFFFF F238 VICVectCntl14 Vector control 14 register R/W 0

0xFFFF F23C VICVectCntl15 Vector control 15 register R/W 0

*Reset Value refers to the data stored in used bits only. It does not include reserved bits content.

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VIC REGISTERS

This section describes the VIC registers in the order in which they are used in the VIC logic, from those closest to the interrupt request inputs to tho se most abstracted for us e by software. For most p eople, this is also th e best order to read about the registers when learning the VIC.

Software Interrupt Register (VICSoftInt - 0xFFFFF018, Read/Write)

The contents of this register are ORed with the 32 interrupt requests from the various peripherals, before any other logic is applied.

Table 31: Software Interrupt Register (VICSoftInt - 0xFFFFF018, Read/Write)

VICSoftInt Function Reset Value

1:force the interrupt request with this bit number.

31:0

0: do not force the inte rrupt request w ith this bi t number. Writ ing zeroes to bits in VICS oftInt has no effect, see VICSoftIntClear.

Software Interrupt Clear Register (VICSoftIntClear - 0xFFFFF01C, Write Only)

This register allows software to clear one or more bits in the Software Interrupt register, without having to first read it.

Table 32: Software Interrupt Clear Register (VICSoftIntClear - 0xFFFFF01C, Write Only)

VICSoftIntClear Function Reset Value

1: writing a 1 clears the corresponding bit in the Software Interrupt register, thus releasing

31:0

the forcing of this request. 0: writing a 0 leaves the corresponding bit in VICSoftInt unchanged.

Raw Interrupt Status Register (VICRawIntr - 0xFFFFF008, Read Only)

This register reads out the state of the 32 interrupt requests and software interrupts, regardless of enabling or classification.

Table 33: Raw Interrupt Status Register (VICRawIntr - 0xFFFFF008, Read-Only)

VICRawIntr Function Reset Value

31:0

1: the interrupt request or software interrupt with this bit number is asserted. 0: the interrupt request or software interrupt with this bit number is negated.

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Interrupt Enable Register (VICIntEnable - 0xFFFFF010, Read/Write)

This register controls which of the 32 interrupt requests and software interrupts contribute to FIQ or IRQ.

Table 34: Interrupt Enable Register (VICINtEnable - 0xFFFFF010, Read/Write)

VICIntEnable Function Reset Value

When this register is read, 1s indicate interrupt requests or software interrupts that are

31:0

Interrupt Enable Clear Register (VICIntEnClear - 0xFFFFF014, Write Only)

This register allows software to clear one or more bits in the Interrupt Enable register, without having to first read it.

Table 35: Software Interrupt Clear Register (VICIntEnClear - 0xFFFFF014, Write Only)

VICIntEnClear Function Reset Value

enabled to contribute to FIQ or IRQ. When this register is writt en, ones enable in terrupt requests or software interrupts to contribu te to FIQ or IRQ, zeroes have no effe ct. See the VICIntEnClear register (Table 46 below), for how to disable interrupts.

1: writing a 1 clears the corresponding bit in the Interrupt Enable register, thus disabling

31:0

interrupts for this request. 0: writing a 0 leaves the corresponding bit in VICIntEnable unchanged.

Interrupt Select Register (VICIntSelect - 0xFFFFF00C, Read/Write)

This register classifies each of the 32 interrupt requests as contributing to FIQ or IRQ.

Table 36: Interrupt Select Register (VICIntSelect - 0xFFFFF00C, Read/Write)

VICIntSelect Function Reset Value

31:0

1: the interrupt request with this bit number is assigned to the FIQ category. 0: the interrupt request with this bit number is assigned to the IRQ category.

IRQ Status Register (VICIRQStatus - 0xFFFFF000, Read Only)

This register reads out the state of those interrupt requests that are enabled and classified as IRQ. It does not differentiate between vectored and non-vectored IRQs.

Table 37: IRQ Status Register (VICIRQStatus - 0xFFFFF000, Read-Only)

VICIRQStatus Function Reset Value

31:0 1: the interrupt request with this bit number is enabled, cla ssifi ed as IRQ, and asserte d. 0

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FIQ Status Register (VICFIQStatus - 0xFFFFF004, Read Only)

This register reads out the state of those interrupt requests that are enabled and classified as FIQ. If more than one request is classified as FIQ, the FIQ service routine can read this register to see which request(s) is (are) active.

Table 38: IRQ Status Register (VICFIQStatus - 0xFFFFF004, Read-Only)

VICFIQStatus Function Reset Value

31:0 1: the interrupt request with this bit number is enabled, cla ssifi ed as FIQ, and ass ert ed. 0

Vector Control Registers 0-15 (VICVectCntl0-15 - 0xFFFFF200-23C, Read/Write)

Each of these registers con trols one of the 16 vectored IRQ slots . Slot 0 has the hi ghest priori ty and slot 1 5 the lowest. N ote that disabling a vectored IRQ slot in one of the VICVectCntl registers does not disable the interrupt itself, the interrupt is simply changed to the non-vectored form.

Table 39: Vector Control Registers (VICVectCntl0-15 - 0xFFFFF200-23C, Read/Write)

VICVectCntl0-15 Function Reset Value

4:0

1: this vectored IRQ slot is enabled, and can produce a unique ISR address when its assigned interrupt request or software interrupt is enabled, classified as IRQ, and asserted.

The number of the interrupt request or software interrupt assigned to this vectored IRQ slot. As a matter of good programming practice, software should not assign the same interrupt number to more than one enabled vectored IRQ slot. But if this does occur, the lowernumbered slot will be used when the interrupt request or software interrupt is enabled, classified as IRQ, and asserted.

Vector Address Registers 0-15 (VICVectAddr0-15 - 0xFFFFF100-13 C, Read/Write)

These registers hold the addresses of the Interrupt Service routines (ISRs) for the 16 vectored IRQ slots.

Table 40: Vector Address Registers (VICVectAddr0-15 - 0xFFFFF100-13C, Read/Write)

VICVectAddr0-15 Function Reset Value

When one or more in terrupt req uest or s oftware int errupt is (are) enab led, class ified as IR Q,

31:0

asserted, and assign ed to a n e nabled vectored IRQ slot, the valu e from this register for the highest-priority such slot will be provided when the IRQ service routine reads the Vector Address register (VICVectAddr).

Default Vector Address Register (VICDefVectAddr - 0xFFFFF034, Read/Write)

This register holds the address of the Interrupt Service routine (ISR) for non-vectored IRQs.

Table 41: Default Vector Address Register (VICDefVectAddr - 0xFFFFF034, Read/Write)

VICDefVectAddr Function Reset Value

31:0

When an IRQ service routin e reads the Vec tor Address register (VIC VectAddr), and no IR Q slot responds as described above, this address is returned.

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Vector Address Register (VICVectAddr - 0xFFFFF030, Read/Write)

When an IRQ interrupt occurs, the IRQ service routine can read this register and jump to the value read.

Table 42: Vector Address Register (VICVectAddr - 0xFFFFF030, Read/Write)

VICVectAddr Function Reset Value

If any of the inter rupt requests or software in terrupts that a re assigned to a vecto red IRQ slot is (are) enabled, classified as IRQ, and asserted, reading from this register returns the address in the Vector A ddress Register for the h ighest-priority such slot. Otherwise it returns

31:0

Protection Enable Register (VICProtection - 0xFFFFF020, Read/Write)

This one-bit register controls access to the VIC registers by software running in User mode.

the address in the Default Vector Address Register. Writing to this register does not set the value for future reads from it. Rather, this register

should be written near the end of an ISR, to update the priority hardware.

Table 43: Protection Enable Register (VICProtection - 0xFFFFF020, Read/Write)

VICProtection Function Reset Value

1: the VIC registers can only be accessed in privileged mode. 0: VIC registers can be accessed in User or privileged mode.

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INTERRUPT SOURCES

Table 37 lists the interrupt sources for each peripheral function. Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.

Table 44: Connection of Interrupt Sources to the Vectored Interrupt Controller

Block Flag(s) VIC Channel #

WDT Watchdog Interrupt (WDINT) 0

- Reserved for software interrupts only 1 ARM Core Embedded ICE, DbgCommRx 2 ARM Core Embedded ICE, DbgCommTx 3

Timer 0

Timer 1

Match 0 - 3 (MR0, MR1, MR2, MR3) Capture 0 - 3 (CR0, CR1, CR2, CR3)

Rx Line Status (RLS)

UART 0

Transmit Holding Register empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI)

Rx Line Status (RLS) Transmit Holding Register empty (THRE)

UART 1

Rx Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI)

PWM0

Match 0 - 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)

Capture 0 - 3 (CR0, CR1, CR2, CR3) I2C SI (state change) 9 SPI SPIF, MODF 10

- reserved 11

PLL PLL Lock (PLOCK) 12

RTC RTCCIF (Counter Increment), RTCALF (Alarm) 13

System

Control

System

Control

External Interrupt 0 (EINT0) 14

External Interrupt 1 (EINT1) 15

System

Control

External Interrupt 2 (EINT2) 16

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nVICFIQIN

VICINT

SOURCE

[31:0]

Interrupt Request, Masking, and Selection

SoftIntClear

[31:0]

SoftInt

[31:0]

RawInterrupt

[31:0]

Vector Interrupt 0

Source Enable

VectorCntl[5:0]

Vector Interrupt 1 Priority 1

IntEnableClear

[31:0]

IntEnable

[31:0]

IntSelect

[31:0]

Priority 0

VectorAddr

Priority 2

[31:0]

FIQStatus

[31:0]

IRQStatus

[31:0]

VectIRQ0

VectAddr0[31:0]

VectIRQ1 VectAddr1[31:0]

Non-vectored FIQ Interrupt Logic

FIQStatus

[31:0]

Non-vectored IRQ Interrupt Logic

Priority

Logic

IRQ

Address Select for Highest Priority Interrupt

IRQStatus

[31:0]

Interrupt Priority Logic

Hardware

NonVectIRQ

VectorAddr

[31:0]

nVICFIQ

nVICIRQ

VICVECT

ADDROUT

[31:0]

Vector Interrupt 15 Priority 14

Priority 15

VectIRQ15 VectAddr15[31:0]

VICVECTADDRIN[31:0]nVICIRQIN

Default

VectorAddr

[31:0]

Figure 13: Block Diagram of the Vectored Interrupt Controller

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VIC USAGE NOTES

If user’s code is runing from the on-chip RAM and an aplication uses interrupts, interrupt vectors must be re-mapped to flash address 0x0. This is nece ssary because all the except ion vectors are located at addre sses 0x0 and above. This is easily achieved by configuring MEMM AP registe r (locat ed in Sys tem Con trol Bloc k) to User R AM mod e. App licat ion co de shou ld be li nked s uch that at 0x4000 0000 the Interrupt Vector Tabe (IVT) will reside.

Although multiple sources can be selected (VICIntSelect) to generate FIQ request, only one interrupt service routine should be dedicated to service al l avail able/p resent FIQ reque st(s). Th erefore, i f more than one inte rrupt sou rces are classifi ed as FIQ the FIQ interrupt service rout ine must read VICFIQSta tus to decide based on thi s content what to do and how to process the interrupt request. However, it is recommended that only one interrupt source should be classified as FIQ. Classifying more than one interrupt sources as FIQ will increase the interrupt latency.

Following the compl etion of the desired interrupt service routine, clea ring of the interrupt flag on the peripheral level will propagate to corresponding bits in VIC registers (VICRawIntr, VICFIQStatus and VICIRQStatus). Also, before the next interrupt can be serviced, it is necessary that write is performed into the VICVectAddr register before the return from interrupt is executed. This write will clear the respective interrupt flag in the internal interrupt priority hardware.

In order to disable the interrupt at the VIC you need to clear corresponding bit in the VICIntEnClr register, which in turn clears the related bit in the VICIntEnable register. This also applies to the VICSoftInt and VICSoftIntClear in which VICS oftIn tCle ar will clear the respective bits in VICSoftInt. For example, if VICSoftInt=0x0000 0005 and bit 0 has to be cleared, VICSoftIntClear=0x0000 0001 will acom plish this. Be fore the new cl ear operatio n on the sam e bit in VICSof tInt using writin g into VICSoftIntClear is performed in the future, VICSoftIntClear= 0x0000 0000 must be assi gned. Therefore writing 1 to any bit in Clear register will have one-time-effect in the destination register.

If the watchdog is enable d for interru pt on unde rflow or in vali d feed seq uence only then there is no way of c learing the interrupt. The only way you could perform return from interrupt is by disabling the interrupt at the VIC(using VICIntEnClr).

Example: Assuming that UART 0 and SPI are generating interrupt requests that are classified as vectored IRQs (UART0 being on the

higher level than SPI), while UART1 and I setup:

VICIntSelect = 0x0000 0000(SPI, I2C, UART1 and UART0 are IRQ => bit10, bit9, bit7 and bit6=0) VICIntEnable = 0x0000 06C0(SPI, I2C, UART1 and UART0 are enabled interrupts => bit10, bit9, bit 7 and bit6=1) VICDefVectAddr = 0x… (holds address at what routine for servicing non-vectored IRQs (i.e. UART1 and I2C) starts) VICVectAddr0 = 0x… (holds address where UART0 IRQ service routine starts) VICVectAddr1 = 0x… (holds address where SPI IRQ service routine starts) VICVectCntl0 = 0x0000 0026(interrupt source with index 6 (UART0) is enabled as the one with priority 0 (the highest)) VICVectCntl1 = 0x0000 002A(interrupt source with index 10 (SPI) is enabled as the one with priority 1)

After any of IRQ requests (SPI, I2C, UART0 or UART1) is made, microcontroller will redirect code execution to the address specified at location 0x00000018. For vectored and non-vectored IRQ’s the following instruction could be placed at 0x18:

LDR pc,[pc,#-0xFF0]

This instruction loads PC with the address that is present in VICVectAddr register. In case UART0 request has been made, VICVectAddr will be identical to VICVectAddr0, while in case SPI request has been

made value from VICVectAddr1 will be found here. If neithe r UART0 nor SPI have generated IR Q request but UART1 and /or I were the reason, content of VICVectAddr will be identical to VICDefVectAddr.

C are generating non-vectored IRQs, the following could be one possibility for VIC

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6. PIN CONFIGURATION

LPC2106/2105/2104 PINOUT

P0.18 / CAP1.3 / TMS

P0.17 / CAP1.2 / TRST

P0.16 / EINT0 / MAT0.2

P0.15 / RI1 / EINT2

P0.14 / DCD1 / EINT1

Vss4

P0.13 / DTR1 / MAT1.1

Vdd3-1 (I/O)

P0.26 / TRACESYNC

P0.25 / PIPESTAT2

P0.12 / DSR1 / MAT1.0

P0.19 / MAT1.2 / TCK

P0.20 / MAT1.3 / TDI P0.21 / PWM5 / TDO

Vdd1.8 (core)

RST

Vss1

P0.27 / TRACEPKT0 / TRST

P0.28 / TRACEPKT1 / TMS

P0.29 / TRACEPKT2 / TCK

X1 X2

10 11 12

1 2 3 4 5 6 7 8 9

Vss2

Vdd3-2 (I/O)

P0.11 / CTS1 / CAP1.1

P0.10 / RTS1 / CAP1.0

P0.24 / PIPESTAT1

P0.23 / PIPESTAT0

P0.22 / TRACECLK

Vss3

P0.9 / RxD1 / PWM6

P0.8 / TxD1 / PWM4

P0.7 / SSEL / PWM2

DBGSEL

RTCK

P0.0 / TxD0 / PWM1

P0.1 / RxD0 / PWM3

Figure 14: LPC2106/2105/2104 48-pin package (LQFP48)

P0.31 / EXTIN0 / TDO

P0.30 / TRACEPKT3 / TDI

P0.2 / SCL / CAP0.0

P0.3 / SDA / MAT0.0

P0.4 / SCK / CAP0.1

P0.5 / MISO / MAT0.1

P0.6 / MOSI / CAP0.2

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LPC2106/2105/2104 PIN FUNCTIONS

Table 45: Pin description for LPC2106/2105/2104

Function Group

Vdd - Vdd1.8 - - 5

Vss - Vss1 - - 7

Oscillator - X1 - - 11

Reset - RST

UART0 - P0.0 TxD0 PWM1 13

I2C - P0.2 SCL CAP0.0 (Timer 0) 18

SPI - P0.4 SCK CAP0.1 (Timer 0) 22

UART1 - P0.8 TxD1 PWM4 29

EXT INT - P0.16 EINT0 MAT0.2 (Timer 0) 46

JTAG TRST P0.17 CAP1.2 (Timer 1) - 47

DEBUG -

JTAG -

ETM TRACECLK P0.22 - - 32

Vss - Vss4 - - 43

Vdd - Vdd3-2 - - 17

DBGSEL and RTCK Override

- Vdd3-1 - - 40

-Vss2--19

-X2--12

-P0.1RxD0PWM314

- P0.3 SDA MAT0.0 (Timer 0) 21

- P0.5 MISO MAT0.1 (Timer 0) 23

- P0.6 MOSI CAP0.2 (Timer 0) 24

- P0 .7 SSEL PWM2 28

-P0.9RxD1PWM630

- P0.10 RTS1 CAP1.0 (Timer 1) 35

- P0.11 CTS1 CAP1.1 (Timer 1) 36

- P0.12 DSR1 MAT1.0 (Timer 1) 37

- P0.13 DTR1 MAT1.1 (Timer 1) 41

- P0.14 DCD1 EINT1 44

- P0.15 RI1 EINT2 45

TMS P0.18 CAP1.3 (Timer 1) - 48

TCK P0.19 MAT1.2 (Timer 1) - 1

TDI P0.20 MAT1.3 (Timer 1) - 2

TDO P0.21 PWM5 - 3

-Vss3--31

PIPESTAT0 P0.23 - - 33 PIPESTAT1 P0.24 - - 34 PIPESTAT2 P0.25 - - 38

TRACESYNC P0.26 - - 39

TRACEPKT0 P0.27 TRST - 8 TRACEPKT1 P0.28 TMS - 9 TRACEPKT2 P0.29 TCK - 10 TRACEPKT3 P0.30 TDI - 15

EXTIN0 P0.31 TDO - 16

Pin Name (Default Function2)

DBGSEL

RTCK

Alternate Function 1 Alternate Function 2 Pin No.

--6

--27

--26

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1. There must be a low level at the DBGSEL input for normal operation. The DBGSEL pin has a built-in p ulldown that will provide this if the pin is left unconnected in the application. Details of Debug mode may be found in "EmbeddedICE Logic" chapter.

2. This column shows the default functionality of each pin during debug mode with the primary JTAG port.

3. RTCK is an extra signal added to the JTAG port. Multi-ICE (Development system from ARM) uses this signal to maintain synchronization with targets having slow or widely varying clock frequency. For details refer to "Multi-ICE System Design considerations Application Note 72 (ARM DAI 0072A)". RTCK is used as an input when enabling debug mode to choose debug port options. Details of Debug mode may be found later in "EmbeddedICE Logic" chapter.

PIN DESCRIPTION FOR LPC2106/2105 /2104

Pin description for LPC2106/2105/2104 and a brief of corresponding functions are shown in the following table.

Table 46: Pin description and corresponding functions for LPC2106/2105/2104

Name

P0.0

P0.31

LQFP 48

Pin #

Type Description

I/O Port 0: Port 0 is a 32-bit bi-directional I/O port with individual direction controls for each bit. The

operation of port 0 pins depends upon the pin function selected via the Pin Connect Block.

O O

I/O

P0.0 TxD0 Transmitter output for UART 0.

PWM1 Pulse Width Modulator output 1.

P0.1 RxD0 Receiver input for UART 0.

PWM3 Pulse Width Modulator output 3.

P0.2 SCL I

P0.3 SDA I

P0.4 SCK Serial Clock. SPI clock output from master or input to slave.

P0.5 MISO Master In Slave Out. Data input to SPI master or data output from SPI

CAP0.0 Capture input for Timer 0, channel 0.

MAT0.0 Match output for Timer 0, channel 0.

CAP0.1 Capture input for Timer 0, channel 1.

MAT0.1 Match output for Timer 0, channel 1.

C clock input/output. Open drain output (for I2C compliance).

C data input/output. Open drain output (for I2C compliance).

slave.

I/O

O O

P0.6 MOSI Master Out Slave In. Data output from SPI master or data input to SPI

slave.

P0.7 SSEL Slave Select. Selects the SPI interface as a slave.

P0.8 TxD1 Transmitter output for UART 1.

P0.9 RxD1 Receiver input for UART 1.

CAP0.2 Capture input for Timer 0, channel 2.

PWM2 Pulse Width Modulator output 2.

PWM4 Pulse Width Modulator output 4.

PWM6 Pulse Width Modulator output 6.

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Table 46: Pin description and corresponding functions for LPC2106/2105/2104

Name

LQFP 48

Pin #

Type Description

O O

P0.10 RTS1 Request to Send output for UART 1.

P0.11 CTS1 Clear to Send input for UART 1.

P0.12 DSR1 Data Set Ready input for UART 1.

P0.13 DTR1 Data Terminal Ready output for UART 1.

P0.14 DCD1 Data Carrier Detect input for UART 1.

P0.15 RI1 Ring Indicator input for UART 1.

P0.16 EINT0 External interrupt 0 input.

P0.17 CAP1.2 Capture input for Timer 1, channel 2.

CAP1.0 Capture input for Timer 1, channel 0.

CAP1.1 Capture input for Timer 1, channel 1.

MAT1.0 Match output for Timer 1, channel 0.

MAT1.1 Match output for Timer 1, channel 1.

EINT1 External interrupt 1 input.

EINT2 External interrupt 2 input.

MAT0.2 Match output for Timer 0, channel 2.

TRST Test Reset for JTAG interface, primary JTAG pin group.

32 O

33 O

34 O

38 O

39 O

P0.18 CAP1.3 Capture input for Timer 1, channel 3.

O O

P0.19 MAT1.2 Match output for Timer 1, channel 2.

P0.20 MAT1.3 Match output for Timer 1, channel 3.

P0.21 PWM5 Pulse Width Modulator output 5.

P0.22 TRACECLK Trace Clock. Standard I/O port with internal pullup.

P0.23 PIPESTAT0 Pipeline Statu s, bit 0. Standard I/O port with internal pull up.

P0.24 PIPESTAT1 Pipeline Statu s, bit 1. Standard I/O port with internal pull up.

P0.25 PIPESTAT2 Pipeline Statu s, bit 2. Standard I/O port with internal pull up.

P0.26 TRACESYNCTrace Synchronization Standard I/O port with internal pullup.

TMS Test Mode Select for JTAG interface, primary JTAG pin group.

TCK Test Cl ock for JTAG interface, p rimary JTAG pin group.

TDI Test Data In for JTAG interface, primary JTAG pin group.

TDO Test Data Out for JTAG interface, primary JTAG pin group.

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Table 46: Pin description and corresponding functions for LPC2106/2105/2104

Name

LQFP 48

Pin #

Type Description

P0.27 TRACEPKT0Trace Packet, bit 0. Standard I/O port with internal pullup.

TRST Test Reset for JTAG interface, secondary JTAG pin group.

P0.28 TRACEPKT1Trace Packet, bit 1. Standard I/O port with internal pullup.

TMS Test Mode Select for JTAG interface, secondary JTAG pin group.

P0.29 TRACEPKT2Trace Packet, bit 2. Standard I/O port with internal pullup.

TCK Test Clock for JTAG interface, secondary JTAG pin group.

P0.30 TRACEPKT3Trace Packet, bit 3. Standard I/O port with internal pullup.

P0.31 EXTIN0 External Trigger Input. Standard I/O port with internal pullup.

TDI Test Data In for JTAG interface, secondary JTAG pin group.

TDO Test Data Out for JTAG interface, secondary JTAG pin group.

Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger

RTCK 26 I/O

synchronization when process or frequency v aries. Als o used d uring debu g mode entry to enable primary JTAG pins. Bi-directional pin with internal pullup.

DBGSEL 27 I

RST

Debug Select. When low, the part operates normally. When high, debug mode is entered. Input pin with internal pulldown.

External Reset input. A lo w on this pin resets th e device, causi ng I/O ports and peri pherals to take

on their default states, and processor execution to begin at address 0. X1 11 I Input to the oscillator circuit and internal clock generator circuits. X2 12 O Output from the oscillator amplif ier.

DD1.8

DD3

7, 19, 31,

5I1.8V Core Power Supply: This is the power supply voltage for internal circuitry.

17, 40 I 3.3V Pad Power Supply: This is the power supply voltage for the I/O ports.

4, 20, 25,

I Ground: 0V reference.

- Not Connected: These pins are not connected.

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7. PIN CONNECT BLOCK

FEATURES

• Allows individual pin configuration

APPLICATIONS

The purpose of the Pin Connect Block is to configure the microcontroller pins to the desired functions.

DESCRIPTION

The pin connect blo ck allows sele cted pi ns of the mi crocontroller to have more than one fu nction. Con figuration register s control the multiplexers to allow connection between the pin and the on chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined.

REGISTER DESCRIPTION

The Pin Control Module contains 2 registers as shown in Table 47. below.

Table 47: Pin Connect Block Register Map

Address Name Description Access

0xE002C000 PINSEL0 Pin function select register 0 Read/Write 0xE002C004 PINSEL1 Pin function select register 1 Read/Write

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Pin Function Select Register 0 (PINSEL0 - 0xE002C000)

The PINSEL0 register con trols the functio ns of the pins as per the settings l isted in Table 50. Th e direction cont rol bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically.

Table 48: Pin Function Select Register 0 (PINSEL0 - 0xE002C000)

PINSEL0

1:0 P0.0 GPIO Port 0.0 TxD (UART 0) PWM1 Reserved 0 3:2 P0.1 GPIO Port 0.1 RxD (UART 0) PWM3 Reserved 0 5:4 P0.2 GPIO Port 0.2 SCL (I 7:6 P0.3 GPIO Port 0.3 SDA (I

9:8 P0.4 GPIO Port 0.4 SCK (SPI) Capture 0.1 (Timer 0) Reserved 0 11:10 P0.5 GPIO Port 0.5 MISO (SPI) Match 0.1 (Timer 0) Reserved 0 13:12 P0.6 GPIO Port 0.6 MOSI (SPI) Capture 0.2 (Timer 0) Reserved 0 15:14 P0.7 GPIO Port 0.7 SSEL (SPI) PWM2 Reserved 0 17:16 P0.8 GPIO Por t 0.8 TxD UART 1 PWM4 Reserved 0 19:18 P0.9 GPIO Port 0.9 RxD (UART 1) PWM6 Reserved 0 21:20 P0.10 GPIO Port 0.10 RTS (UART1) Capture 1.0 (Timer 1) Reserved 0 23:22 P0.11 GPIO Port 0.11 CTS (UART1) Capture 1.1 (Timer 1) Reserved 0 25:24 P0.12 GPIO Port 0.12 DSR (UART1) Match 1.0 (Timer 1) Reserved 0 27:26 P0.13 GPIO Port 0.13 DTR (UART 1) Match 1.1 (Timer 1) Reserved 0 29:28 P0.14 GPIO Port 0.14 CD (UART 1) EINT1 Reserved 0 31:30 P0 .15 GPIO Port 0.15 RI (UART1) EINT2 Reserved 0

Name

Function when 00 Function when 01 Function when 10 Function when 11

C) Capture 0.0 (Timer 0) Reserved 0

C) Match 0.0 (Timer 0) Reserved 0

Reset Value

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Pin Function Select Register 1 (PINSEL1 - 0xE002C004)

The PINSEL1 register con trols the functio ns of the pins as per the settings l isted in Table 49. Th e direction cont rol bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically. Function control for the pins P0.17 - P0.31 is effective only when the DBGSEL input is pulled LOW during RESET.

Table 49: Pin Function Select Register 1 (PINSEL1 - 0xE002C004)

PINSEL1 Pin Name Function when 00 Function when 01 Function when 10 Function when 11

1:0 P0.16 GPIO Port 0.16 EINT0 Match 0.2 (Timer 0) Reserved 0 3:2 P0.17 GPIO Port 0.17 Capture 1.2 (Timer 1) Reserved Reserved 0 5:4 P0.18 GPIO Port 0.18 Capture 1.3 (Timer 1) Reserved Reserved 0 7:6 P0.19 GPIO Port 0.19 Match 1.2 (Timer 1) Reserved Reserved 0

9:8 P0.20 GPIO Port 0.20 Match 1.3 (Timer 1) Reserved Reserved 0 11:10 P0.21 GPIO Port 0.21 PWM5 Reserved Reserved 0 13:12 P0.22 GPIO Port 0.22 Reserved Reserved Reserved 0 15:14 P0.23 GPIO Port 0.23 Reserved Reserved Reserved 0 17:16 P0.24 GPIO Port 0.24 Reserved Reserved Reserved 0 19:18 P0.25 GPIO Port 0.25 Reserved Reserved Reserved 0 21:20 P0.26 GPIO Port 0.26 Reserved Reserved Reserved 0 23:22 P0.27 GPIO Port 0.27 TRST Reserved Reserved 0 25:24 P0.28 GPIO Port 0.28 TMS Reserved Reserved 0 27:26 P0.29 GPIO Port 0.29 TCK Reserved Reserved 0 29:28 P0.30 GPIO Port 0.30 TDI Reserved Reserved 0 31:30 P0.31 GPIO Port 0.31 TDO Reserved Reserved 0

Reset Value

Pin Function Select Register Values

The PINSEL registers c ontrol t he functions of dev ice p ins a s shown below. Pairs o f bi ts in t hese re giste rs corre spond to sp ecific device pins.

Table 50: Pin Function Select Register Bits

Pinsel0 and Pinsel1 Values Function Value after Reset

0 0 Primary (default) function, typically GPIO Port 0 1 First alternate function 1 0 Second alternate function 11Reserved

The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Each derivative typically has a different pinout and therefore a different set of functions possible for each pin. Details for a specific derivative may be found in the appropriate data sheet.

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8. GPIO

FEATURES

• Direction control of individual bits

• Separate control of output set and clear

• All I/O default to inputs after reset

APPLICATIONS

• General purpose I/O

• Driving LEDs, or other indicators

• Controlling off-chip devices

• Sensing digital inputs

PIN DESCRIPTION

Table 51: GPIO Pin Description

Pin Name Type Description

P0.0 - P0.31

Input/

Output

General purpose in put/output. The number of GP IO s ac tua lly a va ila ble d epe nds on the use of alternate functions.

REGISTER DESCRIPTION

The GPIO contains 4 registers as shown in Table 52.

Table 52: GPIO Register Map

Address Name Description Access

0xE0028000 IOPIN

0xE0028004 IOSET

0xE0028008 IODIR

0xE002800C IOCLR

GPIO Pin value register. The c urre nt sta te of the port pins can always be read from this register, regardless of pin direction and mode.

GPIO 0 Output set register. This register controls the state of output pins in conjunction with the IOCLR register. Writing ones produces highs at the corresponding port pins. Writing zeroes has no effect.

GPIO 0 Direction co ntrol register. This re gister individual ly controls the direct ion of each port pin.

GPIO 0 Output clear register. This register controls the state of output pins. Writing ones produces lows at the corresponding port pins and clears the corresponding bits in the IOSET register. Writing zeroes has no effect.

Read Only

Read/Set

Read/Write

Clear Only

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GPIO Pin Value Register (IOPIN - 0xE0028000)

This register provides the value of the GPIO pins. This value reflects any outside world influence on the pins. Note: for test purposes, writi ng to this registe r stores th e value in the outpu t registe r, bypas sing th e need to us e both the IOSET

and IOCLR registers. This feature is of little or no use in an application because it is not possible to write to individual bytes in this register.

Table 53: GPIO Pin Value Register (IOPIN - 0xE0028000)

IOPIN Description

31:0 GPIO pin value bits. Bit 0 corresponds to P0.0 ... Bit 31 corresponds to P0.31 Undefined

Value afte r

Reset

GPIO Output Set Register (IOSET - 0xE0028004)

This register is us ed to pro duce a HIG H level output at the po rt pins if th ey are c onfigured as GPIO in an OU TPUT mode. Writing 1 produces a HIGH l evel at the corre sponding port pi ns. Writing 0 has no effect. If any pi n is configured as an input or a s econdary function, writing to IOSET has no effect.

Reading the IOSET register returns the value in the GPIO output regi ster, as determined by prev ious writes to IOSET and IOCL R (or IOPIN as noted above). This value does not reflect the effect of any outside world influence on the I/O pins.

Table 54: GPIO Output Set Register (IOSET - 0xE0028004)

IOSET Description

31:0 Output value SET bits. Bit 0 corresponds to P0.0 ... Bit 31 corresponds to P0.31 0

Value afte r

Reset

GPIO Output Clear Register (IOCLR - 0xE002800C)

This register is use d to produce a LO W level at port pins if they are configure d as GPIO in an OUTPUT mode. W riting 1 produc es a LOW level at the corresponding port pins and clears the corresponding bits in the IOSET register. Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing to IOCLR has no effect.

Table 55: GPIO Output Clear Register (IOCLR - 0xE002800C)

IOCLR Description

31:0 Output value CLEAR bits. Bit 0 corresponds to P0.0 ... Bit 31 corresponds to P0.31 0

Value afte r

Reset

GPIO Direction Register (IODIR - 0xE0028008)

This register is used to contro l the di rection o f the pi ns whe n they a re config ured as GPIO port pins. D irection bit for a ny pin must be set accor ding to the pi n functionality.

Table 56: GPIO Direction Register (IODIR - 0xE0028008)

IODIR Description

31:0 Direction control bits (0 = INPUT, 1 = OUTPUT). Bit 0 controls P0.0 ... Bit 31 controls P0.31 0

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GPIO USAGE NOTES

If for the specified output pin corresponding bit is set both in GPIO Output Set Register (IOSET) and in GPIO Output Clear Register (IOCLR), observed pin will output level determined by the later write access of IOSET nad IOCLR. This means that in case of sequence:

IOSET = 0x0000 0080 IOCLR = 0x0000 0080 pin P0.7 will have low output, since access to Clear register came after access to Set register.

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9. UART 0

FEATURES

• 16 byte Receive and Transmit FIFOs.

• Register locations conform to ‘550 industry standard.

• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.

• Built-in baud rate generator.

PIN DESCRIPTION

Table 57: UART 0 Pin Description

Pin Name Type Description

RxD0 Input Serial Input. Serial receive data.

TxD0 Output Serial Output. Serial transmit data.

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REGISTER DESCRIPTION

Table 58: UART 0 Register Map

Address

Offset

0xE000C000

DLAB = 0

0xE000C000

DLAB = 0

0xE000C004

DLAB = 0

0xE000C008 U0IIR

0xE000C008 U0FCR

0xE000C00C U0LCR

0xE000C014 U0LSR

Name Description BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Access

U0RBR

U0THR

U0IER

Receiver

Buffer

Transmit

Holding

Interrupt

Enable

Interrupt ID

FIFO

Control

Line Control

Line Status

Reset

Value*

MSB READ DATA LSB RO

MSB WRITE DATA LSB WO NA

Interrupt

Available

Enable

R/W 0

WO 0

R/W 0

00000

Status

Interrupt

Reset

Bits

of Stop

Enable THRE

Rx FIFO

Word Length

Reset

Select

Enable Rx Data

FIFO

Enable Rx Line

FIFOs Enabled 0 0 IIR3 IIR2 IIR1 IIR0 RO 0x01

Rx Trigger Reserved -

Tx FIFO

DLAB

Rx FIFO Error

Set

TEMT THRE BI FE PE OE DR RO 0x60

Break

Stick

Parity

Even

Parity

Select

Enable

Number

un-

defined

0xE000C01C U0SCR

0xE000C000

DLAB = 1

0xE000C004

DLAB = 1

*Reset Value refers to the data stored in used bits only. It does not include reserved bits content. UART 0 contains ten 8-bit registers as shown in Table 58. The Divisor Latch Access Bit (DLAB) is contained in U0LCR7 and

enables access to the Divisor Latches.

U0DLL

U0DLM

Scratch Pad

Divisor Latch

LSB

Divisor Latch

MSB

MSB LSB R/W 0

MSB LSB R/W 0x01

MSB LSB R/W 0

UART 0 Receiver Buffer Register (U0RBR - 0xE000C000 when DLAB = 0, Read Only)

The U0RBR is the top byte of the UART0 Rx FIFO. The top byte of the Rx FIFO contai ns the oldest cha rac ter received and can be read via the bus interface. The LSB (bit 0) represents the “oldest” received data bit. If the character received is less than 8 bits, the unused MSBs are padded with zeroes.

The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the U0RBR. The U0RBR is always Read Only.

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Table 59: UART0 Receiver Buffer Register (U0RBR - 0xE000C000 when DLAB = 0, Read Only)

U0RBR Function Description

7:0

Receiver Buffer

The UART0 Receive r Buffer Regis ter contains the oldest received byte i n the UART0 Rx FIFO.

Reset Value

un-

defined

UART0 Transmitter Holding Register (U0THR - 0xE000C000 when DLAB = 0, Write Only)

The U0THR is the top byte of the UART0 Tx FIFO. The top byte is the newest character in the Tx FIFO and can be written via the bus interface. The LSB represents the first bit to transmit.

The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the U0THR. The U0THR is always Write Only.

Table 60: UART0 Transmit Holding Register (U0THR - 0xE000C000 when DLAB = 0, Write Only)

U0THR Function Description

Writing to the UART0 Transmit Holding Register causes the data to be stored in the UART0 transmit FIFO. The by te will be sent when it rea ches the bo ttom of the FIF O and the transmitter is available.

7:0

Transmit

Holding Register

Reset Value

N/A

UART0 Divisor Latch LSB Register (U0DLL - 0xE000C000 when DLAB = 1)

UART0 Divisor Latch MSB Register (U0DLM - 0xE000C004 when DLAB = 1)

The UART0 Divisor Latch is part of the UART0 Baud Rate Generator and hold s the v al ue us ed to d iv ide the VPB c lock (pc lk) in order to produce the baud ra te cloc k, whi ch must be 1 6x the des ired ba ud rate. The U0DLL an d U0DLM regist ers toge ther form a 16 bit divisor w here U0DLL contains th e lower 8 bit s of the div isor and U0D LM contai ns the high er 8 bits of the divisor. A ‘h0000 value is treated like a ‘h0001 value as division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in U0LCR must be one in order to access the UART0 Divisor Latches.

Table 61: UART0 Divisor Latch LSB Register (U0DLL - 0xE000C000 when DLAB = 1)

U0DLL Function Description

7:0

Table 62: UART0 Divisor Latch MSB Register (U0DLM - 0xE000C004 when DLAB = 1)

U0DLM Function Description

7:0

Divisor Latch LSB Register

Divisor Latch

MSB Register

The UART0 Divisor Latch LSB Regi ster, a long w ith t he U0D LM regis ter, de termin es the baud rate of the UART0.

The UART0 Divisor Latch MSB Regi st er, along with the U0D LL re gister, determ ines the baud rate of the UART0.

Reset Value

0x01

Reset Value

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UART0 Interrupt Enable Register (U0IER - 0xE000C004 when DLAB = 0)

The U0IER is used to enable the four UART0 interrupt sources.

Table 63: UART0 Interrupt Enable Register Bit Descriptions (U0IER - 0xE000C004 when DLAB = 0)

U0IER Function Description

0: Disable the RDA interrupt.

RBR Interrupt

7:3 Reserved

Enable

THRE Interrupt

Enable

Rx Line Status

Interrupt Enable

1: Enable the RDA interrupt. U0IER0 enables the Receive Data Available interrupt for UART0. It also controls the Character Receive Time-out interrupt.

0: Disable the THRE interrupt. 1: Enable the THRE interrupt. U0IER1 enables the TH RE i nte rrupt fo r UAR T0. The status of this interrupt can be read from U0LSR5.

0: Disable the Rx line status interrupts. 1: Enable the Rx line status interrupts. U0IER2 enables the UART0 Rx line stat us inter rupts. Th e status of this i nterr upt can b e read from U0LSR[4:1].

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Reset Value

UART0 Interrupt Identification Register ( U 0IIR - 0xE000C008, Read Only)

The U0IIR provides a status cod e that denotes the priority and so urce of a pending inte rrupt. The int errupts are frozen duri ng an U0IIR access. If an interrupt occurs during an U0IIR access, the interrupt is recorded for the next U0IIR access.

Table 64: UART0 Interrupt Identification Register Bit Descriptions (U0IIR - 0xE000C008, Read Only)

U0IIR Function Description

0: At least one interrupt is pending.

3:1

5:4 Reserved

7:6 FIFO Enable These bits are equivalent to U0FCR0. 0

Interrupts are handled as described in Table 65. Given the status of U0IIR[3:0], an interrupt handler routine can determine the cause of the interrupt an d ho w to cle ar the active interrupt. Interrupts are handl ed as described in Table 65. The U0IIR must be read in order to clear the interrupt prior to exitting the Interrupt Service Routine.

Interrupt Pending

Interrupt

Identification

1: No pending interrupts. Note that U0IIR0 is active low. The pending interrupt can be determined by evaluating U0IER3:1.

011: 1. Receive Line Status (RLS) 010: 2a.Receive Data Available (RDA) 110: 2b.Character Time-out Indicator (CTI) 001: 3. THRE Interrupt. U0IER3 identifies an interrupt corresponding to the UART0 Rx FIFO. All other combinations of U0IER3:1 not listed above are reserved (000,100,101,111).

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Reset Value

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The UART0 RLS interrupt (U0IIR3:1=011) is the highest priority interrupt and is set whenever any one of four error conditions occur on the UART0 Rx input: overrun error (OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART0 Rx error condition that set the interrupt can be observed via U0LSR4:1. The interrupt is cleared upon an U0LSR read.

The UART0 RDA interrupt (U0IIR3:1=010) shares the second level priority with the CTI interrupt (U0IIR3:1=110). The RDA is activated when the UART0 R x FIFO reach es the trig ger level de fined in U 0FCR7:6 and is rese t when th e UART0 Rx FIFO dept h falls below the trigger level. When the RDA interrupt goes active, the CPU can read a block of data defined by the trigger level.

The CTI interrupt (U0IIR3:1=110 ) is a second level interru pt and is set when the UAR T0 Rx FIFO c ontains at least one chara cter and no UART0 Rx FIFO activity ha s occurre d in 3.5 to 4.5 characte r times. Any UART0 Rx F IFO activity (read or w rite of UART 0 RSR) will clear the interrupt. This interrupt is int end ed to flush the UART0 RBR after a m essa ge has be en received that is not a multiple of the tri gge r lev el si ze . Fo r ex am ple , if a peripheral wished to send a 105 c hara cte r me ss age and the trigger level was 10 characters, the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts (depending on the service routine) resulting in the transfer of the remaining 5 characters.

Table 65: UART0 Interrupt Handling

U0IIR[3:0] Priority

0001 - none none -

0110 Highest

0100 Second

1100 Second

0010 Third THRE THRE

note: values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.

Interrupt

Type

Rx Line Status /

Error

Rx Data

Available

Character Time-

out Indication

OE or PE or FE or BI U0LSR Read

Rx data available or trigger l evel reache d in FIFO (U0FCR0=1 )

Minimum of one character in the Rx FIFO and no character input or removed durin g a time period depend ing on how many characters are in FIFO and what th e trigg er le vel is set at (3.5 to 4.5 character times). The exact time will be: [(word length) X 7 - 2] X 8 + {(trigger level - number of characters) X 8 + 1] RCLKs

Interrupt

Source

U0RBR Read or

U0 RBR Read

U0IIR Read (if

Interrupt

Reset

UART0 FIFO

drops below

trigger level

source of

interrupt) or

THR write

The UART0 THRE interrupt (U0IIR3:1=001) is a third level interrupt and is activated when the UART0 THR FIFO is empty provided certain i nitialization con ditions have bee n met. These init ialization condit ions are intended to give the UART0 THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start-up. The initialization conditions implement a one character delay minus the stop bit whenever THRE=1 and there have not been at least two characters in the U0THR at one time since the las t THRE =1 ev ent . This dela y is prov id ed to give the CPU time to write data to U0THR without a THRE interrupt to decode and service. A THRE interrupt is set immediately if the UART0 THR FIFO has held two or more characters at one time a nd curre ntly, th e U0THR is empt y. Th e THRE in terrupt i s reset when a U0THR w rite oc curs or a read of the U0IIR occurs and the THRE is the highest interrupt (U0IIR3:1=001).

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UART0 FIFO Control Register (U0FCR - 0xE000C008)

The U0FCR controls the operation of the UART0 Rx and Tx FIFOs.

Table 66: UART0 FIFO Control Register Bit Descriptions (U0FCR - 0xE000C008)

U0FCR Function Description

Active high enable for both UART0 Rx and Tx FIFOs and U0FCR7:1 access. This bit

0 FIFO Enable

1 Rx FIFO Reset

2Tx FIFO Reset

5:3 Reserved

Rx Trigger Level

7:6

Select

must be set for proper UART0 opearation. Any transition on this bit will automatically clear the UART0 FIFOs.

Writing a logic 1 to U 0FCR 1 wi ll clear all bytes in UART0 Rx FIFO a nd res et th e p oi nter logic. This bit is self-clearing.

Writing a logic 1 to U0FCR2 will cle ar al l by tes in UAR T0 Tx FIF O an d res et th e po int er logic. This bit is self-clearing.

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

00: trigger level 0 (default=’h1) 01: trigger level 1 (default=’h4) 10: trigger level 2 (default=’h8) 11: trigger level 3 (default=’he) These two bits determine how many receiver UART0 FIFO characters must be written before an interrupt is activated. The four trigger levels are defined by the user at compilation allowing the user to tune the trigger levels to the FIFO depths chosen.

Reset Value

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UART0 Line Control Register (U0LCR - 0xE000C00C)

The U0LCR determines the format of the data character that is to be transmitted or received.

Table 67: UART0 Line Control Register Bit Descriptions (U0LCR - 0xE000C00C)

U0LCR Function Description

00: 5 bit character length

1:0

2 Stop Bit Select

3 Parity Enable

5:4 Parity Select

6 Break Control

Word Length

Select

Divisor Latch

Access Bit

01: 6 bit character length 10: 7 bit character length 11: 8 bit character length

0: 1 stop bit 1: 2 stop bits (1.5 if U0LCR[1:0]=00)

0: Disable parity generation and checking 1: Enable parity generation and checking

00: Odd parity 01: Even parity 10: Forced “1” stick parity 11: Forced “0” stick parity

0: Disable break transmission 1: Enable break transmission. Output pin UART0 TxD is forced to logic 0 when U0LCR6 is active high.

0: Disable access to Divisor Latches 1: Enable access to Divisor Latches

UART0 Line Status Register (U0LSR - 0xE000C014, Read Only)

Reset Value

The U0LSR is a read-only register that provides status information on the UART0 Tx and Rx blocks.

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Table 68: UART0 Line Status Register Bit Descriptions (U0LSR - 0xE000C014, Read Only)

U0LSR Function Description

0: U0RBR is empty 1: U0RBR contains valid data U0LSR0 is set when the U0RBR holds an unread character and is cleared when the UART0 RBR FIFO is empty.

0: Overrun error status is inactive. 1: Overrun error status is active. The overrun error condition is set as so on as it occur s. An U0L SR read clea rs U0LS R1. U0LSR1 is set when UART0 R SR has a new c haracter a ssembled and th e UART0 RB R FIFO is full. In t his cas e, the UART0 RBR FIFO will not be ov erwritten and the cha racter in the UART0 RSR will be lost.

0: Parity error status is inactive. 1: Parity error status is active. When the parity bit of a receiv ed character is in the wrong state , a parity error occ urs. An U0LSR read clears U0LSR2. Time of parity error detection is dependent on U0FCR0. A parity error is associated with the character being read from the UART0 RBR FIFO.

0: Framing error status is inactive. 1: Framing error status is active. When the stop bit of a received character is a log ic 0, a framing error oc curs. An U0LSR read clears U0LSR3. The time of the framing error detection is dependent on U0FCR0. A framing error is associated with the character being read from the UART0 RBR FIFO. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is a ctually an ea rly start bit. Ho wever, it ca nnot be assum ed that the next received byte will be correct even if there is no Framing Error.

Receiver

Data Ready

(RDR)

Overrun

Error (OE)

Parity Error

(PE)

Framing

Error

(FE)

Reset Value

Break

Interrupt

(BI)

Transmitter

Holding

Empty

(THRE)

Transmitter

Empty

(TEMT)

Error in Rx

FIFO

(RXFE)

0: Break interrupt status is inactive. 1: Break interrupt status is active. When RxD0 is he ld in the spaci ng state (all 0 ’s) for one full character transmi ssion (sta rt, data, parity, stop), a break interrupt occ urs. Once the brea k condition has be en detected, the receiver goes idle until RxD0 goes to marking state (all 1’s). An U0LSR read clears this status bit. The time of break detection is dependent on U0FCR0. The break interrupt is associated with the character being read from the UART0 RBR FIFO.

0: U0THR contains valid data. 1: U0THR is empty. THRE is set immediately upon detection of an empty UART0 THR and is cleared on a U0THR write.

0: U0THR and/or the U0TSR contains valid data. 1: U0THR and the U0TSR are empty. TEMT is set when both U0TH R and U 0TSR are e mpty; TEM T is cl eared when either t he U0TSR or the U0THR contain valid data.

0: U0RBR contains no UART0 Rx errors or U0FCR0=0. 1: UART0 RBR contains at least one UART0 Rx error. U0LSR7 is set when a character with a Rx error such as framing error, parity error or break interrupt, is l oaded in to the U 0RBR. Th is bit i s cleare d when th e U0LSR register is read and there are no subsequent errors in the UART0 FIFO.

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UART0 Scratch Pad Register (U0SCR - 0xE000C01C)

The U0SCR has no effect on the UART0 operation. This register can be written and/or read at user’s discretion. There is no provision in the interrupt interface that would indicate to the host that a read or write of the U0SCR has occurred.

Table 69: UART0 Scratchpad Register (U0SCR - 0xE000C01C)

U0SCR Function Description

7:0 - A readable, writable byte. 0

Reset Value

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ARCHITECTURE

The architecture of the UART0 is shown below in the block diagram. The VPB interface provides a communications link between the CPU or host and the UART0. The UART0 receiver block, U0Rx, monitors the serial input line, RxD0, for valid input. The UART0 Rx Shift Register (U0RSR)

accepts valid characters via RxD0. After a valid character is assembled in the U0RSR, it is passed to the UART0 Rx Buffer Register FIFO to await access by the CPU or host via the generic host interface.

The UART0 transmitter block, U0Tx, accepts data written by the CPU or host and buffers the data in the UA RT0 Tx Holding Register FIFO (U0TH R). The U ART0 Tx Shift Regi st er (U0T SR) rea ds the data s tored in the U0T HR and asse mbles the da ta t o transmit via the serial output pin, TxD0.

The UART0 Baud Rate Generato r block, U0 BRG, gener ates the t iming en ables used by the U ART0 Tx b lock. The U0BRG clo ck input source is the VPB cloc k (pclk). The main cl ock is divided do wn per the divisor s pecified in the U0DL L and U0DLM registers. This divided down clock is a 16x oversample clock, NBAUDOUT.

The interrupt int erface cont ains reg isters U0IER a nd U 0IIR. The interru pt interf ace rece ives sev eral one clock wi de enabl es from the U0Tx and U0Rx blocks.

Status information from the U0 Tx a nd U0R x is s tore d in th e U 0LSR. Co ntrol info rma tio n for th e U 0Tx and U0Rx is sto red in the U0LCR.

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U0INTR

INTERRUPT

U0IER

U0IIR

U0SCR

U0THR

THR

U0BRG

U0DLL

U0DLM

U0RBR

U0FCR

U0LSR

LCRU0LCR

U0Tx

U0Rx

U0TSR

U0RSR

NTXRDY

TxD0

NBAUDOUT

RCLK

NRXRDY

RxD0

PA[2:0] PSEL PSTB PWRITE PD[7:0] AR MR pclk

DDISVPB

Interface

Figure 15: UART0 Block Diagram

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10. UART 1

FEATURES

• UART 1 is identical to UART 0, with the addition of a modem interface.

• 16 byte Receive and Transmit FIFOs.

• Register locations conform to ‘550 industry standard.

• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.

• Built-in baud rate generator.

• Standard modem interface signals included.

PIN DESCRIPTION

Table 70: UART1 Pin Description

Pin Name Type Description

RxD1 Input Serial Input. Serial receive data.

TxD1 Output Serial Output. Serial transmit data.

Clear To Send. Active low s ignal indicates if the external mode m is ready to acce pt transmitted

CTS1 Input

DCD1 Input

DSR1 Input

DTR1 Output

RI1 Input

RTS1 Output

data via TxD1 from the UART 1. In norma l opera tion of the mo dem in terface (U1MCR 4=0), the complement value of this signal is stored in U1MSR4. State change information is stored in U1MSR0 and is a source for a priority level 4 interrupt, if enabled (U1IER3=1).

Data Carrier Detect. Active low signal indicates if the external modem has established a communication link with the UART1 and data may be exchanged. In normal operation of the modem interface (U1MCR4=0), the complement value of this signal is stored in U1MSR7. State change information is stored in U1MSR3 and is a source for a priority level 4 interrupt, if enabled (U1IER3=1).

Data Set Ready. Active low signal indicates if the external modem is ready to establish a communications link with the UART1. In normal operation of the modem interface (U1MCR4=0), the complement value of this signal is stored in U1MSR5. State change information is stored in U1MSR1 and is a source for a priority level 4 interrupt, if enabled (U1IER3=1).

Data Terminal Ready. Active low signal indicates that the UART1 is ready to establish connection with external modem. The complement value of this signal is stored in U1MCR0.

Ring Indicator. Active low signal indicates that a telephone ringing signal has been detected by the modem. In normal operation of the modem interface (U1MCR4=0), the complement value of this signa l is stored in U1MSR6. State change in formation i s stored in U1MSR 2 and is a source for a priority level 4 interrupt, if enabled (U1IER3=1).

Request To Send. Active low signal in dicates that the UART1 would like to transmit data to the external modem. The complement value of this signal is stored in U1MCR1.

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REGISTER DESCRIPTION

Table 71: UART 1 Register Map

Address Name Description BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Access

0xE0010000

DLAB = 0

0xE0010000

DLAB = 0

0xE0010004

DLAB = 0

0xE0010008 U1IIR

0xE0010008 U1FCR

0xE001000C U1LCR

0xE0010010 U1MCR

0xE0010014 U1LSR

0xE0010018 U1MSR

0xE001001C U1SCR

0xE0010000

DLAB = 1

0xE0010004

DLAB = 1

U1RBR

U1THR

U1IER

U1DLL

U1DLM

Receiver

Buffer

Transmit

Holding

Interrupt

Enable

Interrupt ID

FIFO

Control

Line Control

Modem

Control

Line Status

Modem

Status

Scratch Pad

Divisor Latch

LSB

Divisor Latch

MSB

MSB READ DATA LSB RO

MSB WRITE DATA LSB WO NA

0000

Status

Enable Modem

FIFOs Enabled 0 0 IIR3 IIR2 IIR1 IIR0 RO 0x01

Rx Trigger Reserved -

Set

DLAB

000

Rx FIFO Error

DCD RI DSR CTS

MSB LSB R/W 0

TEMT THRE BI FE PE OE DR RO 0x60

Stick

Break

Even

Parity

Select

Enable

Loop Back

0 0 RTS DTR R/W 0

Delta DCD

Interrupt

Enable Rx Line

Number

Trailing

Edge

Tx FIFO

Status

Interrupt

Reset

Bits

of Stop

Interrupt

Enable THRE

Enable Rx Data

FIFO

Reset

Rx FIFO

Word Length

Select

Delta

DSR

Delta

CTS

Interrupt

Available

Enable

Reset

Value*

un-

defined

R/W 0

WO 0

R/W 0

RO 0

*Reset Value refers to the data stored in used bits only. It does not include reserved bits content. UART1 contains twel ve 8 -bi t registers as shown in Table 71. The Div is or La tc h Acc es s Bit (D LAB) i s contained in U1LCR7 and

enables access to the Divisor Latches.

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UART1 Receiver Buffer Register (U1RBR - 0xE0010000 when DLAB = 0, Read Only)

The U1RBR is the top byte of the UART1 Rx FIFO. The top byte of the Rx FIFO contai ns the oldest cha rac ter received and can be read via the bus interface. The LSB (bit 0) represents the “oldest” received data bit. If the character received is less than 8 bits, the unused MSBs are padded with zeroes.

The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the U1RBR. The U1RBR is always Read Only.

Table 72: UART1 Receiver Buffer Register (U1RBR - 0xE0010000 when DLAB = 0, Read Only)

U1RBR Function Description

7:0

Receiver Buffer

The UART1 Receive r Buffer Regis ter contains the oldest received byte i n the UART1 Rx FIFO.

Reset Value

un-

defined

UART1 Transmitter Holding Register (U1THR - 0xE0010000 when DLAB = 0, Write Only)

The U1THR is the top byte of the UART1 Tx FIFO. The top byte is the newest character in the Tx FIFO and can be written via the bus interface. The LSB represents the first bit to transmit.

The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the U1THR. The U1THR is always Write Only.

Table 73: UART1 Transmit Holding Register (U1THR - 0xE0010000 when DLAB = 0, Write Only)

U1THR Function Description

Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The by te will be sen t when it reache s the bottom of the FIFO and the transmitter is available.

7:0

Holding Register

Transmit

Reset Value

N/A

UART1 Divisor Latch LSB Register (U1DLL - 0xE0010000 when DLAB = 1)

UART1 Divisor Latch MSB Register (U1DLM - 0xE0010004 when DLAB = 1)

The UART1 Divisor Latch is part of the UART1 Baud Rate Generator and hold s the v al ue us ed to d iv ide the VPB c lock (pc lk) in order to produce the baud ra te cloc k, whi ch must be 1 6x the des ired ba ud rate. The U1DLL an d U1DLM regist ers toge ther form a 16 bit divisor w here U1DLL contains th e lower 8 bit s of the div isor and U1D LM contai ns the high er 8 bits of the divisor. A ‘h0000 value is treated like a ‘h0001 value as division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in U1LCR must be one in order to access the UART1 Divisor Latches.

Table 74: UART1 Divisor Latch LSB Register (U1DLL - 0xE0010000 when DLAB = 1)

U1DLL Function Description

7:0

Divisor Latch LSB Register

The UART1 Divisor Latch LSB Regi ster, a long w ith t he U1D LM regis ter, de termin es the baud rate of the UART1.

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Reset Value

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Table 75: UART1 Divisor Latch MSB Register (U1DLM - 0xE0010004 when DLAB = 1)

U1DLM Function Description

7:0

Divisor Latch

MSB Register

The UART1 Divisor Latch MSB Regi st er, along with the U1D LL re gister, determ ines the baud rate of the UART1.

UART1 Interrupt Enable Register (U1IER - 0xE0010004 when DLAB = 0)

The U1IER is used to enable the four interrupt sources.

Table 76: UART1 Interrupt Enable Register Bit Descriptions (U1IER - 0xE0010004 when DLAB = 0)

U1IER Function Description

0: Disable the RDA interrupt.

RBR Interrupt

THRE Interrupt

Rx Line Status

Interrupt Enable

Enable

1: Enable the RDA interrupt. U1IER0 enables the Receive Data Available interrupt for UART1. It also controls the Receive Time-out interrupt.

0: Disable the THRE interrupt. 1: Enable the THRE interrupt. U1IER1 enables the TH RE i nte rrupt fo r UAR T1. The status of this interrupt can be read from U1LSR5.

0: Disable the Rx line status interrupts. 1: Enable the Rx line status interrupts. U1IER2 enables the UART1 Rx line stat us inter rupts. Th e status of this i nterr upt can b e read from U1LSR[4:1].

Reset Value

Modem Status

Interrupt Enable

7:4 Reserved

0: Disable the modem interrupt. 1: Enable the modem interrupt. U1IER3 enables the modem interrupt. The status of this interrupt can be read from U1MSR[3:0].

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

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Philips LPC2106, LPC2105, LPC2104 User Guide

Specifications and Main Features

Frequently Asked Questions

User Manual

Table of Contents

List of Figures

List of Tables

DOCUMENT REVISION HISTORY

1. INTRODUCTION

FEATURES

APPLICATIONS

ARCHITECTURAL OVERVIEW

ARM7TDMI-S PROCESSOR

ON-CHIP FLASH MEMORY SYSTEM

ON-CHIP STATIC RAM

BLOCK DIAGRAM

LPC2106/2105/2104 REGISTERS

2. LPC2106/2105/2104 MEMORY ADDRESSING

MEMORY MAPS

LPC2106/2105/2104 MEMORY RE-MAPPING AND BOOT BLOCK

Memory Map Concepts and Operating Modes

Memory Re-Mapping

PREFETCH ABORT AND DATA ABORT EXCEPTIONS

3. SYSTEM CONTROL BLOCK

SUMMARY OF SYSTEM CONTROL BLOCK FUNCTIONS

PIN DESCRIPTION

REGISTER DESCRIPTION

CRYSTAL OSCILLATOR

EXTERNAL INTERRUPT INPUTS

Register Description

EXTINT Register (EXTINT - 0xE01FC140)

EXTWAKE Register (EXTWAKE - 0xE01FC144)

MEMORY MAPPING CONTROL

Memory Mapping Control Register (MEMMAP - 0xE01FC040)

PLL (PHASE LOCKED LOOP)

Register Description

PLLCON Register (PLLCON - 0xE01FC080)

PLLCFG Register (PLLCFG - 0xE01FC084)

PLLSTAT Register (PLLSTAT - 0xE01FC088)

PLL Modes

PLLFEED Register (PLLFEED - 0xE01FC08C)

PLL and Power Down Mode

PLL Frequency Calculation

POWER CONTROL

Register Description

PCON Register (PCON - 0xE01FC0C0)

Power Control for Peripherals Register (PCONP - 0xE01FC0C4)

RESET

VPB DIVIDER

VPBDIV Register (VPBDIV - 0xE01FC100)

WAKEUP TIMER

4. MEMORY ACCELERATOR MODULE (MAM)

INTRODUCTION

Memory Accelerator Module Blocks

Flash Memory Banks

Instruction Latches and Data Latches

Flash Programming Issues

MEMORY ACCELERATOR MODULE OPERATING MODES

MAM CONFIGURATION

REGISTER DESCRIPTION

MAM Control Register (MAMCR - 0xE01FC000)

MAM Timing Register (MAMTIM - 0xE01FC004)

MAM USAGE NOTES

5. VECTORED INTERRUPT CONTROLLER (VIC)

FEATURES

DESCRIPTION

REGISTER DESCRIPTION

VIC REGISTERS

Software Interrupt Register (VICSoftInt - 0xFFFFF018, Read/Write)

Software Interrupt Clear Register (VICSoftIntClear - 0xFFFFF01C, Write Only)

Raw Interrupt Status Register (VICRawIntr - 0xFFFFF008, Read Only)

Interrupt Enable Register (VICIntEnable - 0xFFFFF010, Read/Write)

Interrupt Enable Clear Register (VICIntEnClear - 0xFFFFF014, Write Only)

Interrupt Select Register (VICIntSelect - 0xFFFFF00C, Read/Write)

IRQ Status Register (VICIRQStatus - 0xFFFFF000, Read Only)

FIQ Status Register (VICFIQStatus - 0xFFFFF004, Read Only)

Vector Control Registers 0-15 (VICVectCntl0-15 - 0xFFFFF200-23C, Read/Write)

Vector Address Registers 0-15 (VICVectAddr0-15 - 0xFFFFF100-13 C, Read/Write)

Default Vector Address Register (VICDefVectAddr - 0xFFFFF034, Read/Write)

Vector Address Register (VICVectAddr - 0xFFFFF030, Read/Write)