Philips ISP1761 operating Manual

ISP1761

Hi-Speed Universal Serial Bus On-The-Go controller

Rev. 01 — 12 January 2005 Product data sheet

1. General description

The ISP1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG) Controller integrated with the advanced Philips Slave Host Controller and the Philips ISP1582 Peripheral Controller.

2. Features

The Hi-Speed USB Host Controller and Peripheral Controller comply to

Bus Speciﬁcation Rev. 2.0

Enhanced Host Controller Interface (EHCI) core implemented in the Host Controller is adapted from

Rev. 1.0 Speciﬁcation Rev. 1.0a

The ISP1761 has three USB ports. Port 1 can be conﬁgured to function as a downstream port, an upstream port or an OTG port; ports 2 and 3 are always conﬁgured as downstream ports. The OTG port can switch its role from host to peripheral, and peripheral to host. The OTG port can become a host through the Host Negotiation Protocol (HNP) as speciﬁed in the OTG supplement.

■ Compliant with

high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)

■ Integrated Transaction Translator (TT) for Original USB (full-speed and low-speed)

peripheral support

■ Three USB ports that support three operational modes:

◆ Mode 1: Port 1 is an OTG Controller port, and ports 2 and 3 are Host Controller

ports

◆ Mode 2: Ports 1, 2 and 3 are Host Controller ports

◆ Mode 3: Port 1 isaPeripheralController port, and ports 2 and 3 are Host Controller

ports

■ Supports OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)

■ Multitasking support with Virtual Segmentation feature (up to four banks)

■ High-speed memory controller (variable latency and SRAM external interface)

■ Directly addressable memory architecture

■ Generic processor interface to most CPUs, such as: Hitachi® SH-3 and SH-4, Philips

XA, Intel® StrongARM®, NEC® and Toshiba® MIPS, Motorola® DragonBall™ and PowerPC® Reduced Instruction Set Computer (RISC) processors

■ Conﬁgurable 32-bit and 16-bit external memory data bus

■ Supports Programmed I/O (PIO) and Direct Memory Access (DMA)

■ Slave DMA implementation on CPU interface for reducing the host system’s CPU load

Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus

. The OTG controller is compliant with

Universal Serial Bus Speciﬁcation Rev. 2.0

and support data transfer speeds of up to 480 Mbit/s. The

On-The-Go Supplement to the USB

; supporting data transfer at

Universal Serial

Philips Semiconductors

ISP1761

Hi-Speed USB OTG controller

■ Separate IRQ, DREQ and DACK lines for the Host Controller and the Peripheral

Controller

■ Integrated multiconﬁguration FIFO

■ Double-buffering scheme increases throughput and facilitates real-time data transfer

■ Integrated Phase-Locked Loop (PLL) with external 12 MHz crystal for low EMI

■ Tolerant I/O for low voltage CPU interface (1.65 V to 3.3 V)

■ 3.3 V-to-5.0 V external power supply input

■ Integrated 5.0 V-to-1.8 V or 3.3 V-to-1.8 V voltage regulator (internal 1.8 V for

low-power core)

■ Internal power-on reset or low-voltage reset and block-dedicated software reset

■ Supports suspend and remote wake-up

■ Built-in overcurrent circuitry (analog overcurrent protection)

■ Hybrid-power mode: V

(can be switched off), V

CC(5V0)

CC(I/O)

(permanent)

■ Target total current consumption:

◆ Normal operation; one port in high-speed active: ICC< 100 mA when the internal

charge pump is not used

◆ Suspend mode: I

CC(susp)

< 150 µA at the room temperature

■ Available in LQFP128 and TFBGA128 packages

■ Host Controller-speciﬁc features

◆ High performance USB host with integrated high-speed USB transceivers;

supports high-speed, full-speed and low-speed

◆ The EHCI core is adapted from

Enhanced Host Controller Interface Speciﬁcation

for Universal Serial Bus Rev. 1.0

◆ Conﬁgurable power management

◆ Integrated TT for Original USB peripheral support on all three ports

◆ Integrated 64 kB high-speed memory (internally organized as 8kX64bits)

◆ Additional 2.5 kB separate memory for TT

◆ Individual or global overcurrent protection with built-in sense circuits

◆ Overcurrent circuitry built-in (digital or analog overcurrent protection)

■ OTG Controller-speciﬁc features

◆ OTG transceiver: fully integrated; compliant with

On-The-Go Supplement to the

USB Speciﬁcation Rev. 1.0a

◆ Supports HNP and SRP for OTG dual-role devices

◆ HNP: status and control registers for software implementation

◆ SRP: status and control registers for software implementation

◆ Programmable timers with high resolution (0.01 ms to 80 ms)—for HNP and SRP

◆ Supports external source of V

BUS

■ Peripheral Controller-speciﬁc features

◆ High-performance USB Peripheral Controller with integrated Serial Interface

Engine (SIE), FIFO memory and transceiver

◆ Complies with

Universal Serial Bus Speciﬁcation Rev. 2.0

and most device class

speciﬁcations

◆ Supports auto Hi-Speed USB mode discovery and Original USB fallback

capabilities

◆ Supports high-speed and full-speed on the Peripheral Controller

◆ Bus-powered or self-powered capability with suspend mode

Product data sheet Rev. 01 — 12 January 2005 2 of 158

Philips Semiconductors

◆ Slave DMA, fully autonomous and supports multiple conﬁgurations

◆ Seven IN endpoints, seven OUT endpoints and one ﬁxed control IN and OUT

◆ Integrated 8 kB memory

◆ Software-controllable connection to the USB bus, SoftConnect™

3. Applications

The ISP1761 can be used to implement a dual-role USB device in any application—USB host or USB peripheral—depending on the cable connection. If the dual-role device is connected to a typical USB peripheral, it behaves like a typical USB host. The dual-role device can also be connected to a PC or any other USB host and behave like a typical USB peripheral.

3.1 Host/peripheral roles

■ Mobile phone to/from:

◆ Mobile phone: exchange contact information

◆ Digital still camera: e-mail pictures or upload pictures to the web

◆ MP3 player: upload/download/broadcast music

◆ Mass storage: upload/download ﬁles

◆ Scanner: scan business cards

■ Digital still camera to/from:

◆ Digital still camera: exchange pictures

◆ Mobile phone: e-mail pictures, upload pictures to the web

◆ Printer: print pictures

◆ Mass storage: store pictures

■ Printer to/from:

◆ Digital still camera: print pictures

◆ Scanner: print scanned image

◆ Mass storage: print ﬁles stored in a device

■ MP3 player to/from:

◆ MP3 player: exchange songs

◆ Mass storage: upload/download songs

■ Oscilloscope to/from:

◆ Printer: print screen image

■ Personal digital assistant to/from:

◆ Personal digital assistant: exchange ﬁles

◆ Printer: print ﬁles

◆ Mobile phone: upload/download ﬁles

◆ MP3 player: upload/download songs

◆ Scanner: scan pictures

◆ Mass storage: upload/download ﬁles

◆ Global Positioning System (GPS): obtain directions, mapping information

◆ Digital still camera: upload pictures

◆ Oscilloscope: conﬁgure oscilloscope

ISP1761

Hi-Speed USB OTG controller

endpoint

Product data sheet Rev. 01 — 12 January 2005 3 of 158

Philips Semiconductors

4. Ordering information

Table 1: Ordering information

Type number Package

ISP1761BE LQFP128 plastic low proﬁle quad ﬂat package; 128 leads;

ISP1761ET

[1] The ISP1761ET is currently under development.

[1]

ISP1761

Hi-Speed USB OTG controller

Name Description Version

SOT425-1

body 14 x 20 x 1.4 mm

TFBGA128 plastic thin ﬁne-pitch ball grid array package;

128 balls; body 9x9x0.8mm

SOT857-1

Product data sheet Rev. 01 — 12 January 2005 4 of 158

Philips Semiconductors

5. Block diagram

CC(I/O)

ISP1761

Hi-Speed USB OTG controller

37 to 39, 41 to 43, 45 to 47, 49, 51, 52, 54, 56 to 58, 60 to 62, 64 to 66, 68 to 70, 72 to 74, 76 to 78, 80

D[15:0]/D[31:0] 82, 84, 86, 87,

89, 91 to 93, 95 to 98, 100 to 103, 105

A[17:1] 106 107 108 111 112 113 114 116 117

124 125

CHARGE

PUMP

126

GENERIC PROCESSOR BUS

CS_N RD_N

WR_N DC_IRQ HC_IRQ DC_DREQ

HC_DREQ HC_DACK DC_DACK

C_B C_A

CC(C_IN)

10, 40, 48, 59, 67, 75, 83, 94, 104, 115

BUS INTERFACE:

MEMORY

MANAGEMENT

UNIT

SLAVE DMA

CONTROLLER

INTERRUPT

CONTROL

REGISTERS

SUPPORT

TRANSACTION TRANSLATOR

(TT) AND RAM

ISP1761

SEL16/32

HC BUFFER

MEMORY

64 KBYTES

MEMORY ARBITER

AND FIFO

ADVANCED

PHILIPS

SLAVE HOST

CONTROLLER

30 MHz

DC BUFFER

MEMORY 8 KBYTES

ADVANCED

PERIPHERAL

CONTROLLER

PLL

60 MHz

GLOBAL CONTROL

AND POWER

MANAGEMENT

POWER-ON RESET AND

BAT

5 V-TO-1.8 V

VOLTAGE

REGULATOR

5 V-TO-3.3 V

VOLTAGE

REGULATOR

11 12 13

122

119

120

110

5, 50,

85, 118

6, 7

XTAL1 XTAL2

CLKIN

RESET_N

HC_SUSPEND/ WAKEUP_N

DC_SUSPEND/ WAKEUP_N

BAT_ON_N

REG(1V8)

CC(5V0)

REG(3V3)

DIGITAL

AND ANALOG

OVERCURRENT

PROTECTION

4, 8, 14, 17, 24, 31, 36, 44, 53, 55, 63, 71, 79, 88, 90, 99, 109, 121, 123

GND

004aaa450

REF5V

RREF1

GND

HI-SPEED USB ATX1

DP1

GND

OTG CONTROLLER

DYNAMIC PORT ROUTING AND PORT CONTROL LOGIC

HI-SPEED USB ATX2

DM1

OC1_N/

PSW1_N

127

RREF2

BUS

GND

DP2

GND

DM2

PSW2_N

128

RREF3

OC2_N

GND

HI-SPEED USB ATX3

DP3

GND

DM3

PSW3_N

OC3_N

Fig 1. Block diagram

Product data sheet Rev. 01 — 12 January 2005 5 of 158

Philips Semiconductors

6. Pinning information

6.1 Pinning

ISP1761

Hi-Speed USB OTG controller

128

ISP1761BE

Fig 2. Pin conﬁguration (LQFP128); top view

ball A1 index area

B D

H K M

2468101213141516

1357911

A C E

J L N

ISP1761ET

103

004aaa506

102

004aaa551

Fig 3. Pin conﬁguration (TFBGA128); top view

Product data sheet Rev. 01 — 12 January 2005 6 of 158

Philips Semiconductors

ISP1761

Hi-Speed USB OTG controller

6.2 Pin description

Table 2: Pin description

Symbol

[1]

Pin LQFP128

Ball TFBGA128

OC3_N 1 C2 AI/I port 3 analog (5 V input) and digital overcurrent input; if not used,

REF5V 2 A2 AI 5 V reference input for analog OC detector; connect a 100 nF

ID 3 B2 I ID input for detection of the default host or peripheral setting when

GND 4 A1 - analog ground V

REG(1V8)

CC(5V0)

5 B1 P corepoweroutput (1.8 V); internal 1.8 V forthe digital core; used for

6 C1 P input to internal regulators (3.0 V to 5.5 V); connect a 100 nF

7 D2 P input to internal regulators (3.0 V to 5.5 V); connect a 100 nF

GND 8 E3 - oscillator ground V

REG(3V3)

CC(I/O)

9 D1 P regulator output (3.3 V); for decoupling only; connect a 100 nF

10 E2 P digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling

XTAL1 11 E1 AI 12 MHz crystal connection input; connect to ground if an external

XTAL2 12 F2 AO 12 MHz crystal connection output CLKIN 13 F1 I 12 MHz oscillator or clock input; connect to V

GND 14 G3 - digital ground GND 15 G2 - RREF1 ground RREF1 16 G1 AI reference resistor connection; connect a 12 kΩ±1 % resistor

GND 17 H2 - analog ground for port 1 DM1 18 H1 AI/O downstream data minus port 1 GND 19 J3 - analog ground DP1 20 J2 AI/O downstream data plus port 1 PSW1_N 21 J1 OD power switch port 1, active LOW

GND 22 K2 - RREF2 ground RREF2 23 K1 AI reference resistor connection; connect a 12 kΩ±1 % resistor

GND 24 L3 - analog ground for port 2 DM2 25 L1 AI/O downstream data minus port 2 GND 26 L2 - analog ground

Type

[2]

Description

connect to V

through a 10 kΩ resistor

CC(I/O)

input, 3.3 V tolerant

decoupling capacitor

port 1 is in the OTG mode input, 3.3 V tolerant

decoupling; connect a 100 nF capacitor; for details on additional capacitor placement, see

decoupling capacitor; see

capacitor and a 4.7 µFto10µF capacitor; see

capacitor; see

Section 7.7

clock is used

CC(I/O)

3.3 V tolerant

between this pin and the RREF1 ground

output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant

between this pin and the RREF2 ground

when not in use

Product data sheet Rev. 01 — 12 January 2005 7 of 158

Philips Semiconductors

ISP1761

Hi-Speed USB OTG controller

Table 2: Pin description

CC(I/O)

[1]

Pin LQFP128

40 T4 P digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling

Symbol

DP2 27 M2 AI/O downstream data plus port 2 PSW2_N 28 M1 OD power switch port 2, active LOW

GND 29 N2 - RREF3 ground RREF3 30 N1 AI reference resistor connection; connect a 12 kΩ±1 % resistor

GND 31 P2 - analog ground for port 3 DM3 32 P1 AI/O downstream data minus port 3 GND 33 R2 - analog ground DP3 34 R1 AI/O downstream data plus port 3 PSW3_N 35 T1 OD power switch port 3, active LOW

GND 36 T2 - digital ground DATA0 37 R3 I/O data bit 0 input and output

DATA1 38 T3 I/O data bit 1 input and output

DATA2 39 R4 I/O data bit 2 input and output

DATA3 41 P5 I/O data bit 3 input and output

DATA4 42 T5 I/O data bit 4 input and output

DATA5 43 R5 I/O data bit 5 input and output

GND 44 T6 - digital ground DATA6 45 R6 I/O data bit 6 input and output

DATA7 46 P7 I/O data bit 7 input and output

DATA8 47 T7 I/O data bit 8 input and output

…continued

Ball TFBGA128

Type

[2]

Description

output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant

between this pin and the RREF3 ground

output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant

capacitor; see

bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant

Section 7.7

Product data sheet Rev. 01 — 12 January 2005 8 of 158

Philips Semiconductors

ISP1761

Hi-Speed USB OTG controller

Table 2: Pin description

Symbol

[1]

Pin LQFP128

CC(I/O)

48 R7 P digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling

…continued

Ball TFBGA128

Type

[2]

Description

capacitor; see

Section 7.7

DATA9 49 T8 I/O data bit 9 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant

REG(1V8)

50 R8 P core power output (1.8 V); internal 1.8 V for the digital core; used for

decoupling; connect a 100 nF capacitor; for details on additional capacitor placement, see

DATA10 51 P9 I/O data bit 10 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant

DATA11 52 T9 I/O data bit 11 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant GND 53 R9 - core ground DATA12 54 T10 I/O data bit 12 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant GND 55 R10 - digital ground DATA13 56 P11 I/O data bit 13 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant DATA14 57 T11 I/O data bit 14 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant DATA15 58 R11 I/O data bit 15 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant V

CC(I/O)

59 T12 P digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see

Section 7.7

DATA16 60 R12 I/O data bit 16 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant DATA17 61 T13 I/O data bit 17 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant DATA18 62 R13 I/O data bit 18 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant GND 63 R14 - digital ground DATA19 64 T14 I/O data bit 19 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

Section 7.7

Product data sheet Rev. 01 — 12 January 2005 9 of 158

Philips Semiconductors

ISP1761

Hi-Speed USB OTG controller

Table 2: Pin description

CC(I/O)

[1]

Pin LQFP128

67 P15 P digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling

75 M14 P digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling

Symbol

DATA20 65 T15 I/O data bit 20 input and output

DATA21 66 R15 I/O data bit 21 input and output

DATA22 68 T16 I/O data bit 22 input and output

DATA23 69 R16 I/O data bit 23 input and output

DATA24 70 P16 I/O data bit 24 input and output

GND 71 N16 - digital ground DATA25 72 N15 I/O data bit 25 input and output

DATA26 73 M15 I/O data bit 26 input and output

DATA27 74 M16 I/O data bit 27 input and output

DATA28 76 L16 I/O data bit 28 input and output

DATA29 77 L15 I/O data bit 29 input and output

DATA30 78 K16 I/O data bit 30 input and output

GND 79 K15 - digital ground DATA31 80 K14 I/O data bit 31 input and output

TEST 81 J16 - connect to ground A1 82 H16 I address pin 1

…continued

Ball TFBGA128

Type

[2]

Description

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

capacitor; see

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

capacitor; see

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

input, 3.3 V tolerant

Section 7.7

Product data sheet Rev. 01 — 12 January 2005 10 of 158

Philips Semiconductors

ISP1761

Hi-Speed USB OTG controller

Table 2: Pin description

Symbol

[1]

Pin LQFP128

CC(I/O)

83 J15 P digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling

…continued

Ball TFBGA128

Type

[2]

Description

capacitor; see A2 84 H15 I address pin 2

input, 3.3 V tolerant V

REG(1V8)

85 G16 P core power output (1.8 V); internal 1.8 V for the digital core; used for

decoupling; connect a 100 nF capacitor and a 4.7 µFto10µF

capacitor; see A3 86 H14 I address pin 3

input, 3.3 V tolerant A4 87 F16 I address pin 4

input, 3.3 V tolerant GND 88 G15 - core ground A5 89 F15 I address pin 5

input, 3.3 V tolerant GND 90 E16 - digital ground A6 91 F14 I address pin 6

input, 3.3 V tolerant A7 92 E15 I address pin 7

input, 3.3 V tolerant A8 93 D16 I address pin 8

input, 3.3 V tolerant V

CC(I/O)

94 D15 P digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see A9 95 C16 I address pin 9

input, 3.3 V tolerant A10 96 C15 I address pin 10

input, 3.3 V tolerant A11 97 B16 I address pin 11

input, 3.3 V tolerant A12 98 B15 I address pin 12

input, 3.3 V tolerant GND 99 A16 - digital ground A13 100 A15 I address pin 13

input, 3.3 V tolerant A14 101 B14 I address pin 14

input, 3.3 V tolerant A15 102 A14 I address pin 15

input, 3.3 V tolerant A16 103 A13 I address pin 16

input, 3.3 V tolerant V

CC(I/O)

104 B13 P digital voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see

Section 7.7

Product data sheet Rev. 01 — 12 January 2005 11 of 158

Philips Semiconductors

ISP1761

Hi-Speed USB OTG controller

Table 2: Pin description

Symbol

[1]

Pin LQFP128

…continued

Ball TFBGA128

Type

[2]

Description

A17 105 C12 I address pin 17

input, 3.3 V tolerant CS_N 106 A12 I chip select signal that indicates the area being accessed; active

LOW

input, 3.3 V tolerant RD_N 107 B12 I read enable; active LOW

input, 3.3 V tolerant WR_N 108 B11 I write enable; active LOW

input, 3.3 V tolerant GND 109 A11 - digital ground V

BAT_ON_N

110 C10 OD to indicate the presence of a minimum 3.3 V on pins 6 and 7

(open-drain); connect to V

through a 10 kΩ pull-up resistor

CC(I/O)

output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant DC_IRQ 111 A10 O Peripheral Controller interrupt signal

output 4 mA drive, 3.3 V tolerant HC_IRQ 112 B10 O Host Controller interrupt signal

output 4 mA drive, 3.3 V tolerant DC_DREQ 113 A9 O DMAC request for the Peripheral Controller

output 4 mA drive, 3.3 V tolerant HC_DREQ 114 B9 O DMAC request for Host Controller

output 4 mA drive, 3.3 V tolerant V

CC(I/O)

115 C8 P digital voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see

Section 7.7

HC_DACK 116 A8 I Host Controller DMA request acknowledgment; when not in use,

connect to V

through a 10 kΩ pull-up resistor

CC(I/O)

input, 3.3 V tolerant DC_DACK 117 B8 I Peripheral Controller DMA request acknowledgment; when not in

use, connect to V

through a 10 kΩ pull-up resistor

CC(I/O)

input, 3.3 V tolerant V

REG(1V8)

118 B7 P core power output (1.8 V); internal 1.8 V for the digital core; used for

decoupling; connect a 100 nF capacitor; for details on additional

HC_SUSPEND /WAKEUP_N

capacitor placement, see

119 A7 I/OD Host Controller suspend and wake-up; three-state suspend output

(active LOW) and wake-up input circuits are connected together

Section 7.7

• HIGH = output is three-state; ISP1761 is in suspend mode

• LOW = output is LOW; ISP1761 is not in suspend mode.

connect to V

output pad, open-drain, 4 mA output drive, 3.3 V tolerant

through an external 10 kΩ pull-up resistor

CC(I/O)

Product data sheet Rev. 01 — 12 January 2005 12 of 158

Philips Semiconductors

ISP1761

Hi-Speed USB OTG controller

Table 2: Pin description

Symbol

DC_SUSPEND /WAKEUP_N

[1]

Pin LQFP128

120 C6 I/OD Peripheral Controller suspend and wake-up; three-state suspend

…continued

Ball TFBGA128

Type

[2]

Description

output (active LOW) and wake-up input circuits are connected

together

• HIGH = output is three-state; ISP1761 is in suspend mode

• LOW = output is LOW; ISP1761 is not in suspend mode.

connect to V

output pad, open-drain, 4 mA output drive, 3.3 V tolerant GND 121 A6 - core ground RESET_N 122 B6 I external power-up reset; active LOW

input, 3.3 V tolerant

Remark: During reset, ensure that all the input pins to the ISP1761

are not toggling. GND 123 B5 - analog ground C_B 124 A5 AI/O charge pump capacitor input; connect a 220 nF capacitor between

this pin and pin 125 C_A 125 B4 AI/O charge pump capacitor input; connect a 220 nF capacitor between

this pin and pin 124 V

CC(C_IN)

OC1_N/V

BUS

126 A4 P charge pump input; connect to 3.3 V 127 B3 (AI/O)(I) This pin has multiple functions:

through an external 10 kΩ pull-up resistor

CC(I/O)

• Port 1 OC1_N detection when port 1 is conﬁgured for host

functionality and an external power switch is used; connect to V

through a 10 kΩ resistor

CC(I/O)

• V

input, 3.3 V tolerant OC2_N 128 A3 AI/I port 2 analog (5 V input) and digital overcurrent input; if not used,

connect to V

input, 3.3 V tolerant

out when internal charge pump is used and port 1 is

BUS

conﬁgured for the host functionality; maximum 50 mA current capability; only for port 1

input detection when port 1 is deﬁned for the peripheral

BUS

functionality.

through a 10 kΩ resistor

CC(I/O)

[1] Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals. [2] I = input only; O = output only; I/O = digital input/output; OD = open-drain output; AI/O = analog input/output; AI = analog input;

P = power; (AI/O)(I) = analog input/output digital input; AI/I = analog input digital input.

Product data sheet Rev. 01 — 12 January 2005 13 of 158

Philips Semiconductors

7. Functional description

7.1 ISP1761 internal architecture: Advanced Philips Slave Host Controller and hub

The EHCI block and the Hi-Speed USB hub block are the main components of the Advanced Philips Slave Host Controller.

The EHCI is the latest generation design, with improved data bandwidth. The EHCI in the ISP1761 is adapted from

Serial Bus Rev. 1.0

The internal Hi-Speed USB hub block replaces the companion Host Controller block used in the original architecture of a Peripheral Component Interconnect (PCI) Hi-Speed USB Host Controller to handle the full-speed and low-speed modes. The hardware architecture in the ISP1761 is simpliﬁed to help reduce cost and development time, by eliminating the additional work involved in implementing the OHCI software required to support the full-speed and low-speed modes.

Figure 4 shows the internal architecture of the ISP1761. The ISP1761 implements an

EHCI that has an internal port—the Root Hub port (not availableexternally)—on which the internal hub is connected. The three external ports are always routed to the internal hub. The internal hub is a Hi-Speed USB hub including the TT.

ISP1761

Hi-Speed USB OTG controller

Enhanced Host Controller Interface Speciﬁcation for Universal

Remark: The root hub must be enabled and the internal hub must be enumerated. Enumerate the internal hub as if it is externally connected. For details, refer to

Linux Programming Guide (AN10042)

At the Host Controller reset and initialization, the internal Root Hub port will be polled until a new connection is detected, showing the connection of the internal hub.

The internal Hi-Speed USB hub is enumerated using a sequence similar to a standard Hi-Speed USB hub enumeration sequence, and the polling on the Root Hub is stopped because the internal Hi-Speed USB hub will never be disconnected. When enumerated, the internal hub will report the three externally available ports.

ISP176x

Product data sheet Rev. 01 — 12 January 2005 14 of 158

Philips Semiconductors

ISP1761

Hi-Speed USB OTG controller

EHCI

ROOT HUB

PORTSC1

ENUMERATION

AND POLLING USING

ACTUAL PTDs

INTERNAL HUB (TT)

PORT1

Fig 4. Internal hub

7.1.1 Internal clock scheme

Figure 5 shows the internal clock scheme of the ISP1761. The ISP1761 has three ports.

XOSC

PORT2

PORT 2

PORT 1

ATX

peripheral clock:

ATX

PORT3

host clock:

48 MHz, 30 MHz,

60 MHz

48 MHz, 30 MHz,

60 MHz

EXTERNAL

PORTS

004aaa513

DIGITAL

CORE

HOST CORE

PERIPHERAL

CORE

004aaa538

PORT 3

PLL 12 MHz IN

ATX

Fig 5. ISP1761 clock scheme

Product data sheet Rev. 01 — 12 January 2005 15 of 158

Philips Semiconductors

Hi-Speed USB OTG controller

Port 2 does not need to be enabled using software if only port 1 or port 3 is used. No port needs to be disabled by external pull-up resistors, if not used. The DP and DM of the unused ports need not be externally pulled HIGH because there are internal pull-down resistors on each port that are enabled by default.

Table 3 lists the various port connection scenarios.

Table 3: Port connection scenarios

Port conﬁguration Port 1 Port 2 Port 3

One port (port 1) DP and DM are routed to USB

connector

One port (port 2) DP and DM are not connected

(left open)

One port (port 3) DP and DM are not connected

(left open)

Two ports (ports 1 and 2)

Two ports (ports 2 and 3)

Two ports (ports 1 and 3)

Three ports (ports 1, 2 and 3)

DP and DM are routed to USB connector

DP and DM are not connected (left open)

DP and DM are routed to USB connector

DP and DM are not connected (left open)

DP and DM are routed to USB connector

DP and DM are not connected (left open)

DP and DM are routed to USB connector

DP and DM are not connected (left open)

DP and DM are routed to USB connector

DP and DM are not connected (left open)

DP and DM are routed to USB connector

DP and DM are not connected (left open)

DP and DM are routed to USB connector

ISP1761

7.2 Host Controller buffer memory block

7.2.1 General considerations

The internal addressable Host Controller buffer memory is 63 kB. The 63 kB effective memory size is the result of subtracting the size of registers (1 kB) from the total addressable memory space deﬁned by the ISP1761 (64 kB). This is an optimized value for achieving the highest performance with a minimal cost.

The ISP1761 is a slave Host Controller. This means that it does not need access to the local bus of the system to transfer data from the memory of the system to the ISP1761 internal memory, unlike the case of the original PCI Hi-Speed USB Host Controllers. Therefore, correct data must be transferred to both the Philips Transfer Descriptor (PTD) area and the payload area by Parallel I/O (PIO) (CPU access) or programmed DMA.

The ‘slave-host’ architecture ensures better compatibility with most of the processors present in the market today because not all processors allow a ‘bus-master’ on the local bus. It also allows better load balancing of the processor’s local bus because only the internal bus arbiter of the processor controls the transfer of data dedicated to USB. This preventsthe local bus from being busy when other more important transfersmay be in the queue; and therefore achieving a ‘linear’ system data ﬂow that has less impact on other processes running at the same time.

The considerations mentioned are also the main reason for implementing the prefetching technique, instead of using a READY signal. The resulting architecture avoids ‘freezing’ of the local bus (by asserting READY), enhancing the ISP1761 memory access time, and avoiding introduction of programmed additional wait states. For details, see Section 7.3.

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The total amount of memory allocated to the payload determines the maximum transfer size speciﬁed by a PTD—a bigger internal memory size results in less CPU interruption for transfer programming. This means less time spent in context switching, resulting in better CPU usage.

A larger buffer also implies a larger amount of data can be transferred. This transfer, however, can be done over a longer period of time, to maintain the overall system performance. Each transfer of the USB data on the USB bus can span up to a few milliseconds before requiring further CPU intervention for data movement.

The internal architecture of the ISP1761 allows a ﬂexible deﬁnition of the memory buffer for optimization of the data transfer on the CPU extension bus and the USB. It is possible to implement different data transfer schemes, depending on the number and type of USB devices present (for example: push-pull—data can be written to half of the memory while data in the other half is being accessed by the Host Controller and sent on the USB bus). This is useful especially when a high-bandwidth ‘continuous or periodic’ data ﬂow is required.

Through an analysis of the hardware and software environment regarding the usual data ﬂow and performance requirements of most embedded systems, Philips has determined the optimal size for the internal buffer as approximately 64 kB.

ISP1761

Hi-Speed USB OTG controller

7.2.2 Structure of the ISP1761 Host Controller memory

The 63 kB of internal memory consists of the PTD area and the payload area. Both the PTD and payload memory zones are divided into three dedicated areas for each

main type of USB transfer: isochronous (ISO), interrupt (INT) and Acknowledged Transfer List (ATL). As shown in Table 4, the PTD areas for ISO, INT and ATL are grouped at the beginning of the memory, occupying the address range 0400h to 0FFFh, following the address space of the registers. The payload or data area occupies the next memory address range 1000h to FFFFh, meaning that 60 kB of memory are allocated for the payload data.

A maximum of 32 PTD areas and their allocated payload areas can be deﬁned for each type of transfer. The structure of a PTD is similar for every transfer type and consists of eight Double Words (DWs) that must be correctly programmed for a correct USB data transfer. The reserved bits of a PTD must be set to logic 0. A detailed description of the PTD structure can be found in Section 8.5.

The transfer size speciﬁed by the PTD determines the contiguous USB data transfer that can be performed without any CPU intervention. The respective payload memory area must be equal to the transfer size deﬁned. The maximum transfer size is ﬂexible and can be optimized, depending on the number and nature of USB devices or PTDs deﬁned and their respective MaxPacketSize.

The CPU will program the DMA to transfer the necessary data in the payload memory. The next CPU intervention will be required only when the current transfer is completed and DMA programming is necessary to transfer the next data payload. This is normally signaled by the IRQ that is generated by the ISP1761 on completing the current PTD, meaning all the data in the payload area was sent on the USB bus. The external IRQ signal is asserted according to the settings in the IRQ Mask OR or IRQ MASK AND registers, see Section 8.4.

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The RAM is structured in blocks of PTDs and payloads so that while the USB is executing on an active transfer-based PTD, the processor can simultaneously ﬁll up another block area in the RAM. A PTD and its payload can then be updated on-the-ﬂy without stopping or delaying any other USB transaction or corrupting the RAM data.

Some of the design features are:

• The address range of the internal RAM buffer is from 0400h to FFFFh.

• The internal memory contains isochronous, interrupt and asynchronous PTDs, and

respective deﬁned payloads.

• All accesses to the internal memory are double-word aligned.

• Internal memory address range calculation:

Memory address = (CPU address − 0400h) (shift right >> 3). Base address is 0400h.

Table 4: Memory address

Memory map CPU address Memory address

ISO 0400h to 07FFh 0000h to 007Fh INT 0800h to 0BFFh 0080h to 00FFh ATL 0C00h to 0FFFh 0100h to 017Fh Payload 1000h to FFFFh 0180h to 1FFFh

ISP1761

Hi-Speed USB OTG controller

Product data sheet Rev. 01 — 12 January 2005 18 of 158

Philips Semiconductors

ISP1761

Hi-Speed USB OTG controller

USB BUS

63 kbytes

USB HIGH-SPEED

HOST AND

TRANSACTION

TRANSLATOR

(FULL-SPEED

AND LOW-SPEED)

address data (64 bits)

PTD1 PTD2

. .

PTD32

PTD1 PTD2

PTD32

PTD1 PTD2

. . . .

PTD32

PAYLOAD

. . . . . . . .

PAYLOAD

ARBITER

240 MB/s

ISOCHRONOUS

INTERRUPT

ASYNC

PAYLOAD

REGISTERS

MEMORY MAPPED

INPUT/OUTPUT,

MEMORY

MANAGEMENT

UNIT,

SLAVE DMA

CONTROLLER

AND

INTERRUPT

CONTROL

D[15:0]/D[31:0]

A[17:1]

CS_N

RD_N

WR_N

DC_IRQ

HC_IRQ

DC_DREQ HC_DREQ

HC_DACK

MICRO-

PROCESSOR

DC_DACK

control signals

004aaa568

Fig 6. Memory segmentation and access block diagram

Both the CPU interface logic and the USB Host Controller require access to the internal ISP1761 RAM at the same time. The internal arbiter controls these accesses to the internal memory, organized internally on a 64-bit data bus width, allowing a maximum bandwidth of 240 MB/s. This bandwidth avoids any bottleneck on accesses both from the CPU interface and the internal USB Host Controller.

7.3 Accessing the ISP1761 Host Controller memory: PIO and DMA

The CPU interface of the ISP1761 can be conﬁgured for a 16-bit or 32-bit data bus width. When the ISP1761 is conﬁgured for a 16-bit data bus width, the upper unused 16 data

lines must be pulled up to V together to a single 10 kΩ pull-up resistor. The 16-bit or 32-bit data bus width conﬁguration is done by programming bit 8 of the HW Mode Control register. This will determine the register and memory access types in both PIO and DMA modes to all internal blocks: Host Controller, Peripheral Controller and OTG Controller. All accesses must be word-aligned for 16-bit mode and double-word aligned for 32-bit mode, where one word = 16 bits. When accessing the Host Controller registers in 16-bit mode, the

Product data sheet Rev. 01 — 12 January 2005 19 of 158

. This can be achieved by connecting DATA[31:16] lines

CC(I/O)

Philips Semiconductors

register access must always be completed using two subsequent accesses. In the case of a DMA transfer,the 16-bit or 32-bit data bus width conﬁguration will determine the number of bursts that will complete a certain transfer length.

In PIO mode, CS_N, WR_N and RD_N are used to access registers and memory. In DMA mode, the data validation is performed by DACK—instead of CS_N—together with the WR_N and RD_N signals. The DREQ signal will always be asserted as soon as the ISP1761 DMA is enabled, as described in the following section.

7.3.1 PIO mode access—memory read cycle

The followingmethod has been implemented to reduce the read access timing in the case of a memory read:

• The Memory register contains the starting address and the bank selection to read

from the memory. Before every new read cycle of the same or different banks, an appropriate value is written to this register.

• Once a value is written to this register, the address is stored in the FIFO of that bank

and is then used to prefetch data for the memory read of that bank. For every subsequent read operation executed at a contiguous address, the address

pointer corresponding to that bank is automatically incremented to prefetch the next data to be sent to the CPU.

Memory read accesses for multiple banks can be interleaved. In this case, the FIFO block handles the MUXing of appropriate data to the CPU.

• The address written to the Memory register is incremented and used to successively

prefetch data from the memory irrespective of the value on the address bus for each bank, until a new value for a bank is written to the Memory register.

For example, consider the following sequence of operations:

– Write the starting (read) address 4000h and bank1 = 01 to the Memory register.

– Write the starting (read) address 4100h and bank2 = 10 to the Memory register.

ISP1761

Hi-Speed USB OTG controller

When RD_N is asserted for three cycles with A[17:16] = 01, the returned data corresponds to addresses 4000h, 4004h and 4008h.

Remark: Once 4000h is written to the Memory register for bank1, the bank select value determines the successive incremental addresses used to fetch the data. That is, the fetching of data is independent of the address on A[15:0] lines.

When RD_N is asserted for four cycles with A[17:16] = 10, the returned data corresponds to addresses 4100h, 4104h, 4108h and 410Ch.

Consequently, the RD_N assertion with A[17:16] = 01 will return data from 400Ch because the bank1 read stopped there in the previous cycle. Also, RD_N assertions with A[17:16] = 10 will now return data from 4110h because the bank2 read stopped there in the previous cycle.

7.3.2 PIO mode access—memory write cycle

The PIO memory write access is similar to a normal memory access. It is not necessary to set the prefetching address before a write cycle to memory.

The ISP1761 internal write address will not be automatically incremented during consecutive write accesses, unlike in a series of ISP1761 memory read cycles. The memory write address must be incremented before every access.

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Philips Semiconductors

7.3.3 PIO mode access—register read cycle

The PIO register read access is similar to a general register access. It is not necessary to set a prefetching address before a register read.

The ISP1761 register read address will not be automatically incremented during consecutive read accesses, unlike in a series of ISP1761 memory read cycles. The ISP1761 register read address must be correctly speciﬁed before every access.

7.3.4 PIO mode access—register write cycle

The PIO register write access is similar to a general register access. It is not necessary to set a prefetching address before a register write.

The ISP1761 register write address will not be automatically incremented during consecutive write accesses, unlike in a series of ISP1761 memory read cycles. The ISP1761 register write address must be correctly speciﬁed before every access.

7.3.5 DMA—read and write operations

The internal ISP1761 Host Controller DMA is a slave DMA. The host system processor or DMA must ensure the data transfer to or from the ISP1761 memory.

ISP1761

Hi-Speed USB OTG controller

The ISP1761 DMA supports a DMA burst length of 1, 4, 8 and 16 cycles for both the 16-bit and 32-bit data bus width. DREQ will be asserted at the beginning of the ﬁrst burst of a DMA transfer and will be deasserted on the last cycle (RD_N or WR_N active pulse) of that burst. It will be reasserted shortly after the DACK deassertion, as long as the DMA transfer counter was not reached. DREQ will be deasserted on the last cycle when the DMA transfer counter is reached and will not reasserted until the DMA reprogramming is performed. Both the DREQ and DACK signals are programmable as active LOW or active HIGH, according to the system requirements.

The DMA start address must be initialized in the respective register, and the subsequent transfers will automatically increment the internal ISP1761 memory address. A register or memory access or access to other system memory can occur in between DMA bursts, whenever the bus is released because DACK is deasserted, without affecting the DMA transfer counter or the current address.

Any memory area can be accessed by the system’sDMA at any starting address because there are no predeﬁned memory blocks. The DMA transfer must start on a word or Double Word address, depending on whether the data bus width is set to 16-bit or 32-bit. DMA is the most efﬁcient method to initialize the payload area, to reduce the CPU usage and overall system loading.

The ISP1761 does not implement EOT to signal the end of a DMA transfer. If programmed, an interrupt may be generated by the ISP1761 at the end of the DMA transfer.

The slave DMA of the ISP1761 will issue a DREQ to the DMA controller of the system to indicate that it is programmed for transfer and data is ready. The system DMA controller may also start a transfer without the need of the DREQ, if the ISP1761 memory is available for the data transfer and the ISP1761 DMA programming is completed.

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Philips Semiconductors

It is also possible that the system’s DMA will perform a memory-to-memory type of transfer between the system memory and the ISP1761 memory. The ISP1761 will be accessed in the PIO mode. Consequently, memory read operations must be preceded by initializing the Memory register (address 033Ch), as described in Section 7.3.1. No IRQ will be generated by the ISP1761 on completing the DMA transfer but an internal processor interrupt may be generated to signal that the DMA transfer is completed. This is mainly useful in implementing the double-buffering scheme for data transfer to optimize the USB bandwidth.

The ISP1761 DMA programming involves:

• Set the active levels of signals DREQ and DACK in the HW Mode Control register.

• The DMA Start Address register contains the ﬁrst memory address at which the data

transfer will start. It must be word-aligned in the 16-bit data bus mode and double word aligned in the 32-bit data bus mode.

• The programming of the HcDMAConﬁguration register speciﬁes:

– The type of transfer that will be performed: read or write. – The burst size—expressed in bytes—is speciﬁed, regardless of the data bus width.

– The transfer length—expressed in number of bytes—deﬁnes the number of bursts.

– Enable ENABLE_DMA (bit 1) of the HcDMAConﬁgurationregister to determine the

ISP1761

Hi-Speed USB OTG controller

For the same burst size, a double number of cycles will be generated in the 16-bit mode data bus width as compared to the 32-bit mode.

The DREQ will be deasserted and asserted to generate the next burst, as long as there are bytes to be transferred. At the end of a transfer, the DREQ will be deasserted and an IRQ can be generated if DMAEOTINT (bit 3 in the HcInterrupt register) is set. The maximum DMA transfersize is equal to the maximum memory size. The transfer size can be an odd or even number of bytes, as required. If the transfer size is an odd number of bytes, the number of bytes transferred by the system’s DMA is equal to the next multiple of two for the 16-bit data bus width or four for the 32-bit data bus width. For a write operation, however, only the speciﬁed odd number of bytes in the ISP1761 memory will be affected.

assertion of DREQ immediately after setting the bit.

After programming the preceding parameters, the system’sDMA may be enabled (waiting for the DREQ to start the transfer or immediate transfer may be started).

The programming of the system’s DMA must match the ISP1761 DMA parameters programmed above. Only one DMA transfer may take place at a time. A PIO mode data transfer may occur simultaneously with a DMA data transfer, in the same or a different memory area.

7.4 Interrupts

The ISP1761 will assert the IRQ according to the source or event in the HcInterrupt register. The main steps to enable the IRQ assertion are:

1. Set GLOBAL_INTR_EN (bit 0) in the HW Mode Control register.

2. Deﬁne the IRQ active as level or edge in INTR_LEVEL (bit 1) of the HW Mode Control register.

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Philips Semiconductors

3. Deﬁne the IRQ polarity as active LOW or active HIGH in INTR_POL (bit 2) of the HW Mode Control register. These settings must match the IRQ settings of the host processor.

By default, interrupt is level-triggered and active LOW.

4. Program the individual Interrupt Enable bits in the HcInterruptEnable register. The software will need to clear the Interrupt status bits in the HcInterrupt register before enabling individual interrupt enable bits.

Additional IRQ characteristics can be adjusted in the Edge Interrupt Count register, as necessary, applicable only when IRQ is set to be edge-active(a pulse of a deﬁned width is generated every time the IRQ is active).

Bits 15 to 0 of the Edge Interrupt Count register deﬁne the IRQ pulse width. The maximum pulse width that can be programmed is FFFFh, corresponding to a 1 ms pulse width. This setting is necessary for certain processors that may require a different minimum IRQ pulse width than the default value. The default IRQ pulse width set at power on is approximately 500 ns.

Bits 31 to 24 of the Edge Interrupt Count register deﬁne the minimum interval between two interrupts to avoid frequent interrupts to the CPU. The default value of 00h attributed to these bits determines the normal IRQ generation, without any delay. When a delay is programmed and the IRQ becomes active after the respective delay, several IRQ events may have already occurred.

ISP1761

Hi-Speed USB OTG controller

All the interrupt events are represented by the respective bits allocated in the HcInterrupt register. There is no mechanism to show the order or the moment occurrence of an interrupt.

The asserted bits in the HcInterrupt register can be cleared by writing back the same value to the HcInterrupt register. This means that writing logic 1 to each of the set bits will reset that corresponding bits to the initial inactive state.

The IRQ generation rules that apply according to the preceding settings are:

• If an event of interrupt occurs but the respective bit in the Interrupt Enable register is

not set, then the respective HcInterrupt register bit is set but the interrupt signal is not asserted.

An interrupt will be generated when interrupt is enabled and the respective bit in the Interrupt Enable register is set.

• For a level trigger, an interrupt signal remains asserted until the processor clears the

HcInterrupt register by writing logic 1 to clear the HcInterrupt register bits that are set.

• If an interrupt is made edge-sensitive and is asserted, writing to clear the HcInterrupt

• The clock stopping mechanism does not affect the generation of an interrupt. This is

useful during the suspend and resume cycles, when an interrupt is generated to signal a wake-up event.

The IRQ generation can also be conditioned by programming the IRQ Mask OR and IRQ Mask AND registers. Setting some of the bits in these registers to logic 1 will determine the IRQ generation only when the respective AND or OR conditions of completing the respective PTDs is met.

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Philips Semiconductors

With the help of the IRQ Mask AND and IRQ Mask OR registers for each type of transfer— ISO, INT and bulk—software can determine which PTDs get priority and an interrupt will be generated when the AND or OR conditions are met. The PTDs that are set will wait until the respective bits of the remaining PTDs are set and then all PTDs generate an interrupt request to the CPU together.

The registers deﬁnition shows that the AND or OR conditions are applicable to the same category of PTDs—ISO, INT and ATL.

When an IRQ is generated, the PTD Done Map registers and the respective V bits will show which PTDs were completed.

The rules that apply to the IRQ Mask AND or IRQ Mask OR settings are:

• TheOR mask has a higher priority over the AND mask. An IRQ is generated if bit n of

done map is set and the corresponding bit n of the OR mask register is set.

• If the OR mask for any done bit is not set, then the AND mask comes into picture. An

IRQ is generated if all the corresponding done bits of the AND Mask register are set. For example: If bits 2, 4 and 10 are set in the AND Mask register,an IRQ is generated only if bits 2, 4, 10 of the done map are set.

• If using the IRQ interval setting for the bulk PTD, an interrupt will only occur at the

regular time interval as programmed in the ATL Done Timeout register. Even if an interrupt eventoccurs before the timeout of the register,no IRQ will be generated until the time is up.

ISP1761

Hi-Speed USB OTG controller

For an example on using the IRQ Mask AND or IRQ Mask OR registers, without the ATL Done Timeout register, see Table 5.

The AND function: activate the IRQ only if PTDs 1, 2 and 4 are done. The OR function: if any of the PTDs 7, 8 or 9 are done, an IRQ for each of the PTD will be

raised.

Table 5: Using the IRQ Mask AND or IRQ Mask OR registers

PTD AND register OR register Time PTD done IRQ

11 0 1ms1 21 0 - 1 30 0 - - 4 1 0 3 ms 1 active because of AND 50 0 - - 60 0 - - 7 0 1 5 ms 1 active because of OR 8 0 1 6 ms 1 active because of OR 9 0 1 7 ms 1 active because of OR

7.5 Phase-Locked Loop (PLL) clock multiplier

The internal PLL requires a 12 MHz input, which can be a 12 MHz crystal or a 12 MHz clock already existing in the system with a precision better than 50 ppm. This allows the use of a low-cost 12 MHz crystal that also minimizes Electro-Magnetic Interference (EMI). When an external crystal is used, make sure the CLKIN pin is connected to V

CC(I/O)

Product data sheet Rev. 01 — 12 January 2005 24 of 158

Philips Semiconductors

The PLL block generates all the main internal clocks required for normal functionality of various blocks: 30 MHz, 48 MHz and 60 MHz.

No external components are required for the PLL operation.

7.6 Power management

The ISP1761 implements a ﬂexible power management scheme, allowing various power saving stages.

The usual powering scheme implies programming EHCI registers and the internal Hi-Speed USB (USB 2.0) hub in the same way it is done in the case of a PCI Hi-Speed USB Host Controller with a Hi-Speed USB hub attached.

While the ISP1761 is set in suspend mode, the main internal clocks will be stopped to ensure minimum power consumption. An internal LazyClock of 100 kHz ± 40 % will continue running. This allows initiating a resume on one of the following events:

• External USB device connect or disconnect

• Assertion of the CS_N signal because of any access to the ISP1761

• Driving the HC_SUSPEND/WAKEUP_N pin to a LOW logical level will wake up the

Host Controller, and driving the DC_SUSPEND/WAKEUP_N pin to a LOW logical level will wake up the Peripheral Controller

ISP1761

Hi-Speed USB OTG controller

The HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins are bidirectional. These pins should be connected to the GPIO pins of a processor.

The awake state can be veriﬁed by reading the LOW level of this pin. If the level is HIGH, it means that the ISP1761 is in the suspend state.

HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N require pull-up resistors because in the ISP1761 suspended state these pins become three-state and can be pulled down, driving them externally by switching the processor’sGPIO lines to the output mode to generate the ISP1761 wake-up.

The HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins are three-state output and also input to the internal wake-up logic.

When in suspend mode, the ISP1761 internal wake-up circuitry will sense the status of the HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins:

• Ifthe pins remain pulled-up, no wake-upwill be generated because a HIGH is sensed

by the internal wake-up circuit.

• If the pins are externally pulled LOW (for example, by the GPIO lines or just a test by

jumpers), the input to the wake-up circuitry becomes LOW and the wake-up is internally initiated.

The resume state has a clock-off count timer deﬁned by bits 31 to 16 of the Power Down Control register. The default value of this timer is 10 ms, meaning that the resume state will be maintained for 10 ms. If during this time, the RUN/STOP bit in the USBCMD register is set to logic 1, the Host Controller will go into a permanent resume—the normal functional state. If the RUN/STOPbit is not set during the time determined by the clock-off

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Philips Semiconductors

count, the ISP1761 will switch back to suspend mode after the speciﬁed time. The maximum delay that can be programmed in the clock-off count ﬁeld is approximately 500 ms.

Additionally, the Power Down Control register allows the ISP1761 internal blocks to disable for lower power consumption as deﬁned in Table 8.

ISP1761

Hi-Speed USB OTG controller

The lowest suspend current (I

CC(susp)

) that can be achieved is approximately 150 µA at room temperature. The suspend current will increase with the increase in temperature, with approximately 300 µAat40°C and up to a typical 1 mA at 85 °C. The system is not in suspend mode when its temperature increases above 40 °C. Therefore, even a 1 mA current consumption by the ISP1761 in suspend mode can be considered negligible. In normal environmental conditions, when the system is in suspend mode, the maximum ISP1761 temperature is approximately 40 °C, determined by the ambient temperature. Therefore, the ISP1761 maximum suspend current will be below 300 µA. An alternative solution to achieve a very low suspend current is to completely switch off the V

CC(5V0)

power input by using an external PMOS transistor, controlled by one of the GPIO pins of the processor. This is possible because the ISP1761 can be used in the hybrid mode, which allows only the V

powered on to avoid loading of the system bus.

CC(I/O)

The time from wake-up to suspend will be approximately 100 ms when the ISP1761 power is always on.

It is necessary to wait for the CLK_RDY interrupt assertion before programming the ISP1761 because internal clocks are stopped during deep sleep suspend and restarted after the ﬁrst wake-up event. The occurrence of the CLK_RDY interrupt means that the internal clocks are running and the normal functionality is achieved.

It is estimated that the CLK_RDY interrupt will be generated less than 100 µs after the wake-up event, if the power to the ISP1761 was on during suspend.

If the ISP1761 is used in the hybrid mode and V

CC(5V0)

is off during suspend, a 2 ms reset pulse is required when the power is switched back to on, before starting to program the resume state. This will ensure that the internal clocks are running and all logics reach a stable initial state.

7.7 Power supply

Figure 7 shows the ISP1761 power supply connection.

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Philips Semiconductors

ISP1761

Hi-Speed USB OTG controller

10, 40, 48, 59, 67, 75,

83, 94,

104, 115

ISP1761

5, 50, 118

004aaa539

6, 7

126

CC(5V0)

CC(I/O)

REG(1V8)

REG(3V3)

CC(C_IN)

10 µF

3.3 V

100 nF

10 µF

100 nF

3.3 V to 5 V

100 nF

1.65 V to 3.6 V

100 nF

A 4.7 µFto10µF capacitor is required on any one of the pins—5, 50 and 118.

Fig 7. ISP1761 power supply connection

Figure 8 shows the most commonly used power supply connection.

ISP1761

6, 7, 10, 40,

48, 59, 67, 75, 83, 94,

104, 115, 126

5, 50, 118

004aaa540

CC(5V0)

REG(1V8)

REG(3V3)

10 µF

CC(I/O)

CC(C_IN)

10 µF

100 nF

A 4.7 µFto10µF capacitor is required on any one of the pins—5, 50 and 118.

Fig 8. Most commonly used power supply connection

3.3 V

100 nF

Product data sheet Rev. 01 — 12 January 2005 27 of 158

Philips Semiconductors

7.7.1 Hybrid mode

Table 6 shows the description of hybrid mode.

Table 6: Hybrid mode

Voltage Status

CC(5V0)

CC(I/O)

ISP1761

Hi-Speed USB OTG controller

off on

In hybrid mode (see Figure 9), V

can be switched off using an external PMOS

CC(5V0)

transistor,controlled using one of the GPIO pins of the processor. This helps to reduce the suspend current (I V

is off during suspend, a 2 ms reset pulse is required when power is switched

CC(5V0)

) below 100 µA. If the ISP1761 is used in hybrid mode and

CC(I/O

back to on, before starting to program the resume.

controlled by the CPU

10, 40, 48, 59, 67, 75,

83, 94,

104, 115

ISP1761

5, 50, 118

6, 7

CC(5V0)

CC(I/O)

REG(1V8)

REG(3V3)

10 µF

100 nF

3.3 V to 5 V

100 nF

1.65 V to 3.6 V

100 nF

CC(C_IN)

126

004aaa676

A 4.7 µFto10µF capacitor is required on any one of the pins—5, 50 and 118.

3.3 V

100 nF

Fig 9. Hybrid mode

Table 7 shows the status of output pins during hybrid mode.

Table 7: Pin status during hybrid mode

Pins V

DATA[31:0], A[17:1], TEST, HC_IRQ, DC_IRQ, HC_DREQ, DC_DREQ, HC_DACK, DC_DACK, HC_SUSPEND/WAKEUP_N,

CC(I/O)

on on normal on off high-Z off X undeﬁned

DC_SUSPEND/WAKEUP_N CS_N, RESET_N, RD_N, WR_N on X input

off X undeﬁned

Product data sheet Rev. 01 — 12 January 2005 28 of 158

CC(5V0)

Status

Philips Semiconductors

7.8 Overcurrent detection

The ISP1761 can implement a digital or analog overcurrent detection scheme. Bit 15 of the HW Mode Control register can be programmed to select the analog or digital overcurrent detection. An analog overcurrent detection circuit is integrated on-chip. The main features of this circuit are self reporting, automatic resetting, low-trip time and low cost. This circuit offers an easy solution at no extra hardware cost on the board. The port power will be automatically disabled by the ISP1761 on an overcurrent event occurrence, by deasserting the PSWn_N signal without any software intervention.

When using the integrated analog overcurrent detection, the range of the overcurrent detection voltage for the ISP1761 is 45 mV to 90 mV. Calculation of the external components should be based on the 45 mV value, with the actual overcurrent detection threshold usually positioned in the middle of the interval.

ISP1761

Hi-Speed USB OTG controller

For an overcurrent limit of 500 mA per port, a PMOS transistor with R approximately 100 mΩ is required. If a PMOS transistor with a lower R

DSON

is used, the

analog overcurrent detection can be adjusted using a series resistor; see Figure 10. ∆V

Fig 10. Adjusting analog overcurrent detection limit (optional)

= ∆V

PMOS

∆V I

OC(nom)

= voltage drop on PMOS

PMOS

=1µA.

(1) Rtd is optional.

OC(TRIP)

= ∆V

5 V

TRIP(intrinsic)

REF5V

− (I

OC(nom)

ISP1761

× Rtd), where:

PSWn_N

(1)

OCn_N

004aaa662

The digital overcurrent scheme requires using an external power switch with integrated overcurrent detection, such as: LM3526, MIC2526 (2 ports) or LM3544 (4 ports). These devices are controlled by PSWn_N signals corresponding to each port. In the case of overcurrent occurrence, these devices will assert OCn_N signals. On OCn_N assertion, the ISP1761 cuts off the port power by deasserting PSWn_N. The external integrated power switch will also automatically cut-off the port power in the case of an overcurrent event, by implementing a thermal shutdown. An internal delay ﬁlter of 1 ms to 3 ms will prevent false overcurrent reporting because of in-rush currents when plugging a USB device.

Product data sheet Rev. 01 — 12 January 2005 29 of 158

Philips Semiconductors

7.9 Power-On Reset (POR)

ISP1761

Hi-Speed USB OTG controller

When V (t

) will be typically 800 ns. The pulse is started when V

PORP

is directly connected to the RESET_N pin, the internal POR pulse width

CC(5V0)

rises above V

CC(5V0)

TRIP

(1.2 V). To give a better viewof the functionality, Figure 11 shows a possible curve of V

CC(5V0)

with dips at t2–t3 and t4–t5. If the dip at t4–t5 is too short (that is, < 11 µs), the internal POR pulse will not react and will remain LOW. The internal POR starts with a 1 at t0. At t1, the detector will see the passing of the trip level and a delay element will add another t

PORP

before it drops to 0. The internal POR pulse will be generated whenever V

drops below V

CC(5V0)

TRIP

for more

than 11 µs.

CC(5V0)

TRIP

t0 t1

PORP

(1) PORP = Power-On Reset Pulse.

Fig 11. Internal power-on reset timing

PORP

(1)

004aaa584

PORP

The recommended RESET input pulse length at power-on should be at least 2 ms to ensure that internal clocks are stable.

The RESET_N pin can be either connected to V

(using the internal POR circuit) or

CC(I/O)

externally controlled (by the microcontroller, ASIC, and so on). Figure 12 shows the availability of the clock with respect to the external POR.

RESET_N

EXTERNAL CLOCK

004aaa583

Stable external clock is available at A.

Fig 12. Clock with respect to the external power-on reset

Product data sheet Rev. 01 — 12 January 2005 30 of 158

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