Philips ISP1760 User Manual

ISP1760

Hi-Speed Universal Serial Bus host controller for embedded applications

Rev. 01 — 8 November 2004 Product data sheet

1. General description

The ISP1760 is a Hi-Speed Universal Serial Bus (USB) Host Controller with a generic processor interface. It integrates one Enhanced Host Controller Interface (EHCI), one Transaction Translator (TT) and three transceivers. The Host Controller portion of the ISP1760 and thethree transceivers comply to The EHCI portion of the ISP1760 is adapted from

Speciﬁcation for Universal Serial Bus Rev. 1.0

The integrated high-performance Hi-Speed USB transceivers enable the ISP1760 to handle all Hi-Speed USB transfer speed modes: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The three downstream ports allow simultaneous connection of three devices at different speeds (high-speed, full-speed and low-speed).

The generic processor interface allows the ISP1760 to be connected to various processors as a memory-mapped resource. The ISP1760 is a slave host: it does not require ‘bus-mastering’ capabilities of the host system bus. The interface is conﬁgurable, ensuring compatibility with a variety of processors. Data transfer can be performed on 16 bits or 32 bits, using Programmed Input/Output (PIO) or Direct Memory Access (DMA) with major control signals conﬁgurable as active LOW or active HIGH.

Universal Serial Bus Speciﬁcation Rev. 2.0

Enhanced Host Controller Interface

2. Features

Integration of the TT allows connection to full-speed and low-speed devices, without the need of integrating Open Host Controller Interface (OHCI) or Universal Host Controller Interface (UHCI). Instead of dealing with two sets of software drivers—EHCI and OHCI or UHCI—you need to deal with only one set—EHCI—that dramatically reduces software complexity and IC cost.

■ The Host Controller portion of the ISP1760 complies with

Speciﬁcation Rev. 2.0

■ The EHCI portion of the ISP1760 is adapted from

Speciﬁcation for Universal Serial Bus Rev. 1.0

■ Contains three integrated Hi-Speed transceivers that support the high-speed,

full-speed and low-speed modes

■ Integrates a TT for Original USB (full-speed and low-speed) device support

■ Up to 64-kbyte internal memory (8kx64bits) accessible through a generic processor

interface; operation in multitasking environments is made possible by the implementation of virtual segmentation mechanism with bank switching on task request

Enhanced Host Controller Interface

Universal Serial Bus

Philips Semiconductors

■ Generic processor interface (nonmultiplexed and variable latency) with a conﬁgurable

32-bit or 16-bit external data bus; the processor interface can be deﬁned as variable-latency or SRAM type (memory mapping)

■ Slave DMA support for reducing the load of the host system CPU during the data

transfer to or from the memory

■ Integrated phase-locked loop (PLL) with a 12 MHz crystal or an external clock input

■ Integrated multiconﬁguration FIFO

■ Optimized ‘msec-based’ or ‘multi-msec-based’ Philips Transfer Descriptor (PTD)

interrupt

■ Tolerant I/O for low voltage CPU interface (1.65 V to 3.6 V)

■ 3.3 V-to-5.0 V external power supply input

■ Integrated 5.0 V-to-1.8 V or 3.3 V-to-1.8 V voltage regulator (internal 1.8 V for

low-power core)

■ Internal power-on reset and low-voltage reset

■ Supports suspend and remote wake-up

■ Target current consumption:

◆ Normal operation; one port in high-speed active: ICC< 100 mA

◆ Suspend mode: I

■ Built-in conﬁgurable overcurrent circuitry (digital or analog overcurrent protection)

■ Available in LQFP128 package.

Embedded Hi-Speed USB host controller

< 150 µA at the room temperature

susp

ISP1760

3. Applications

The ISP1760 can be used to implement a Hi-Speed USB compliant Host Controller connected to most of the CPUs present in the market today, having a generic processor interface with demultiplexed address and data bus. This is because of the efﬁcient slave-type interface of the ISP1760.

The internal architecture of the ISP1760 is such that it can be used in a large spectrum of applications requiring a high-performance internal Host Controller.

3.1 Examples of a multitude of possible applications

■ Set-top box: for connecting external high-performance mass storage devices

■ Mobile phone: for connecting various USB devices

■ Personal Digital Assistant (PDA): for connecting a large variety of USB devices

■ Printer: for connecting external memory card readers, allowing direct printing

■ Digital Still Camera (DSC): for printing to an external USB printer, for direct printing

■ Mass storage: for connecting external memory card readers or other mass storage

devices, for direct back-up. The low power consumption and deep power management modes of the ISP1760

make it particularly suitable for use in portable devices.

Product data sheet Rev. 01 — 8 November 2004 2 of 105

Philips Semiconductors

4. Ordering information

Table 1: Ordering information

Type number Package

ISP1760BE LQFP128 plastic low proﬁle quad ﬂat package; 128 leads;

ISP1760

Embedded Hi-Speed USB host controller

Name Description Version

SOT425-1

body 14 x 20 x 1.4 mm

Product data sheet Rev. 01 — 8 November 2004 3 of 105

Philips Semiconductors

5. Block diagram

CC(I/O)

ISP1760

Embedded Hi-Speed USB host controller

37 to 39, 41 to 43, 45 to 47, 49, 51, 52, 54, 56 to 58, 60 to 62, 64 to 66, 68 to 70, 72 to 74, 76 to 78, 80

GENERIC PROCESSOR BUS

DATA[15:0]/DATA[31:0]

82, 84, 86, 87, 89, 91 to 93, 95 to 98, 100 to 103, 105

A[17:1]

106

CS_N

107

RD_N

108

WR_N

112

IRQ

114

DREQ

116

DACK

USB FULL-SPEED AND LOW SPEED DATA PATH

PORT ROUTING OR CONTROL LOGIC + HOST AND HUB PORT STATUS

RISC PROCESSOR

10, 40, 48, 59, 67, 75, 83, 94, 104, 115

INTERFACE:

MEMORY

MANAGEMENT

UNIT

INTERRUPT

CONTROL

SLAVE DMA

CONTROLLER

HARDWARE

CONFIGURATION

REGISTERS

TRANSACTION

TRANSLATOR

AND RAM

ISP1760

PTD AND PAYLOAD MEMORY:

16-bit

32-bit

INTERNAL MEMORY

UP TO 64 KBYTES

VIRTUAL SEGMENTATION

FOR MULTITASKING SUPPORT

MEMORY

ARBITER

AND FIFO

EHCI AND

OPERATIONAL

REGISTERS

PIE

USB HIGH-SPEED DATA PATH

30 MHz

60 MHz

GLOBAL CONTROL

AND POWER

MANAGEMENT

POWER-ON RESET

AND V

5 V-TO-1.8 V REGULATOR

5 V-TO-3.3 V REGULATOR

BAT

VOLTAGE

AND ANALOG

OVERCURRENT

DETECTION

DIGITAL

PLL

122

119

110

5, 50,

85, 118

6, 7

11 12 13

XTAL1 XTAL2

CLKIN

RESET_N

SUSPEND/ WAKEUP_N

BAT_ON_N

REG(1V8)

CC(5V0)

REG(3V3)

REF5V

RREF1

GND

HI-SPEED USB ATX1

DP1

GND

DM1

PSW1_N

127

OC1_N

RREF2

GND

DP2

HI-SPEED USB ATX2

DM2

GND

PSW2_N

128

OC2_N

RREF3

GND

HI-SPEED USB ATX3

DP3

GND

DM3

PSW3_N

OC3_N

4, 8, 14, 17, 24, 31, 36, 44, 53, 55, 63, 71, 79, 88, 90, 99, 109, 121, 123

004aaa435

GND

Fig 1. Block diagram.

Product data sheet Rev. 01 — 8 November 2004 4 of 105

Philips Semiconductors

6. Pinning information

6.1 Pinning

ISP1760

Embedded Hi-Speed USB host controller

128

ISP1760BE

103

004aaa505

102

Fig 2. Pin conﬁguration (LQFP128).

6.2 Pin description

Table 2: Pin description

Symbol

[1]

Pin Type

OC3_N 1 AI port 3 analog (5 V input) and digital overcurrent input; if not used,

REF5V 2 AI 5 V reference input for analog OC detector; connect a 100 nF

TEST 3 - connect to ground GND 4 - analog ground V

REG(1V8)

CC(5V0)

5 P core power output (1.8 V); internal 1.8 V for the digital core; used for

6 P input to internal regulators (3.0 V to 5.5 V); connect a 100 nF

7 P input to internal regulators (3.0 V to 5.5 V); connect a 100 nF

GND 8 - oscillator ground V

REG(3V3)

CC(I/O)

9 P regulator output (3.3 V); for decoupling only; connect a 100 nF

10 P digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling

XTAL1 11 AI 12 MHz crystal connection input; connect to ground if an external

XTAL2 12 AO 12 MHz crystal connection output CLKIN 13 I 12 MHz oscillator or clock input; connect to V

GND 14 - digital ground

[2]

Description

connect to V

through a 10 kΩ resistor

CC(I/O)

decoupling capacitor

decoupling; connect a 100 nF capacitor

decoupling capacitor

capacitor and a 4.7 µFto10µF capacitor

capacitor

clock is used; see

Table 84

3.3 V tolerant

CC(I/O)

when not in use

Product data sheet Rev. 01 — 8 November 2004 5 of 105

Philips Semiconductors

ISP1760

Embedded Hi-Speed USB host controller

Table 2: Pin description

CC(I/O)

[1]

Pin Type

40 P digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling

Symbol

GND 15 - RREF1 ground RREF1 16 AI reference resistor connection; connect a 12 kΩ±1 % resistor

GND 17 - analog ground for port 1 DM1 18 AI/O downstream data minus port 1 GND 19 - analog ground DP1 20 AI/O downstream data plus port 1 PSW1_N 21 OD power switch port 1, active LOW

GND 22 - RREF2 ground RREF2 23 AI reference resistor connection; connect a 12 kΩ±1 % resistor

GND 24 - analog ground for port 2 DM2 25 AI/O downstream data minus port 2 GND 26 - analog ground DP2 27 AI/O downstream data plus port 2 PSW2_N 28 OD power switch port 2, active LOW

GND 29 - RREF3 ground RREF3 30 AI reference resistor connection; connect a 12 kΩ±1 % resistor

GND 31 - analog ground for port 3 DM3 32 AI/O downstream data minus port 3 GND 33 - analog ground DP3 34 AI/O downstream data plus port 3 PSW3_N 35 OD power switch port 3, active LOW

GND 36 - digital ground DATA0 37 I/O data bit 0 input and output

DATA1 38 I/O data bit 1 input and output

DATA2 39 I/O data bit 2 input and output

DATA3 41 I/O data bit 3 input and output

…continued

[2]

Description

between this pin and the RREF1 ground

output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant

between this pin and the RREF2 ground

output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant

between this pin and the RREF3 ground

output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant

capacitor

bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant

Product data sheet Rev. 01 — 8 November 2004 6 of 105

Philips Semiconductors

ISP1760

Embedded Hi-Speed USB host controller

Table 2: Pin description

Symbol

[1]

Pin Type

…continued

[2]

Description

DATA4 42 I/O data bit 4 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant

DATA5 43 I/O data bit 5 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant GND 44 - digital ground DATA6 45 I/O data bit 6 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant DATA7 46 I/O data bit 7 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant DATA8 47 I/O data bit 8 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant V

CC(I/O)

48 P digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor DATA9 49 I/O data bit 9 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant V

REG(1V8)

50 P core power output (1.8 V); internal 1.8 V forthe digital core; used for

decoupling; connect a 100 nF capacitor DATA10 51 I/O data bit 10 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant DATA11 52 I/O data bit 11 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant GND 53 - core ground DATA12 54 I/O data bit 12 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant GND 55 - digital ground DATA13 56 I/O data bit 13 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant DATA14 57 I/O data bit 14 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant DATA15 58 I/O data bit 15 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant V

CC(I/O)

59 P digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor

Product data sheet Rev. 01 — 8 November 2004 7 of 105

Philips Semiconductors

ISP1760

Embedded Hi-Speed USB host controller

Table 2: Pin description

CC(I/O)

[1]

Pin Type

67 P digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling

75 P digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling

Symbol

DATA16 60 I/O data bit 16 input and output

DATA17 61 I/O data bit 17 input and output

DATA18 62 I/O data bit 18 input and output

GND 63 - digital ground DATA19 64 I/O data bit 19 input and output

DATA20 65 I/O data bit 20 input and output

DATA21 66 I/O data bit 21 input and output

DATA22 68 I/O data bit 22 input and output

DATA23 69 I/O data bit 23 input and output

DATA24 70 I/O data bit 24 input and output

GND 71 - digital ground DATA25 72 I/O data bit 25 input and output

DATA26 73 I/O data bit 26 input and output

DATA27 74 I/O data bit 27 input and output

DATA28 76 I/O data bit 28 input and output

…continued

[2]

Description

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

capacitor

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

capacitor

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant

Product data sheet Rev. 01 — 8 November 2004 8 of 105

Philips Semiconductors

ISP1760

Embedded Hi-Speed USB host controller

Table 2: Pin description

Symbol

[1]

Pin Type

…continued

[2]

Description

DATA29 77 I/O data bit 29 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant DATA30 78 I/O data bit 30 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant GND 79 - digital ground DATA31 80 I/O data bit 31 input and output

bidirectional pad, push-pull input, three-state output, 4 mA output

drive, 3.3 V tolerant TEST 81 - connect to ground A1 82 I address pin 1

input, 3.3 V tolerant V

CC(I/O)

83 P digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor A2 84 I address pin 2

input, 3.3 V tolerant V

REG(1V8)

85 P core power output (1.8 V); internal 1.8 V forthe digital core; used for

decoupling; connect a 100 nF capacitor and a 4.7 µFto10µF

capacitor A3 86 I address pin 3

input, 3.3 V tolerant A4 87 I address pin 4

input, 3.3 V tolerant GND 88 - core ground A5 89 I address pin 5

input, 3.3 V tolerant GND 90 - digital ground A6 91 I address pin 6

input, 3.3 V tolerant A7 92 I address pin 7

input, 3.3 V tolerant A8 93 I address pin 8

input, 3.3 V tolerant V

CC(I/O)

94 P digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor A9 95 I address pin 9

input, 3.3 V tolerant A10 96 I address pin 10

input, 3.3 V tolerant A11 97 I address pin 11

input, 3.3 V tolerant A12 98 I address pin 12

input, 3.3 V tolerant

Product data sheet Rev. 01 — 8 November 2004 9 of 105

Philips Semiconductors

ISP1760

Embedded Hi-Speed USB host controller

Table 2: Pin description

Symbol

[1]

Pin Type

…continued

[2]

Description

GND 99 - digital ground A13 100 I address pin 13

input, 3.3 V tolerant A14 101 I address pin 14

input, 3.3 V tolerant A15 102 I address pin 15

input, 3.3 V tolerant A16 103 I address pin 16

input, 3.3 V tolerant V

CC(I/O)

104 P digital voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor A17 105 I address pin 17

input, 3.3 V tolerant CS_N 106 I chip select signal that indicates the area being accessed; active

LOW

input, 3.3 V tolerant RD_N 107 I read enable; active LOW

input, 3.3 V tolerant WR_N 108 I write enable; active LOW

input, 3.3 V tolerant GND 109 - digital ground V

BAT_ON_N

110 OD to indicate the presence of a minimum 3.3 V on pins 6 and 7

(open-drain); connect to V

through a 10 kΩ pull-up resistor

CC(I/O)

output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant n.c. 111 - not connected IRQ 112 O Host Controller interrupt signal

output pad, 4 mA drive, 3.3 V tolerant n.c. 113 - not connected DREQ 114 O DMAC request for the Host Controller

output pad, 4 mA drive, 3.3 V tolerant V

CC(I/O)

115 P digital voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor DACK 116 I Host Controller DMA request acknowledgment; when not in use,

connect to V

through a 10 kΩ pull-up resistor

CC(I/O)

input, 3.3 V tolerant TEST 117 - connect to ground V

REG(1V8)

118 P core power output (1.8 V); internal 1.8 V forthe digital core; used for

decoupling; connect a 100 nF capacitor SUSPEND/

WAKEUP_ N

119 I/OD Host Controller suspend and wake-up; three-state suspend output

(active LOW) and wake-up input circuits are connected together

• HIGH = output is three-state; ISP1760 is in suspend mode;

connect to V

through an external 10 kΩ pull-up resistor

CC(I/O)

• LOW = output is LOW; ISP1760 is not in suspend mode.

output pad, open-drain, 4 mA output drive, 3.3 V tolerant

Product data sheet Rev. 01 — 8 November 2004 10 of 105

Philips Semiconductors

ISP1760

Embedded Hi-Speed USB host controller

Table 2: Pin description

Symbol

[1]

Pin Type

TEST 120 - pull up to V

…continued

[2]

Description

CC(I/O)

GND 121 - core ground RESET_N 122 I external power-up reset; active LOW

input, 3.3 V tolerant GND 123 - analog ground TEST 124 - connect a 220 nF capacitor between this pin and pin 125 TEST 125 - connect a 220 nF capacitor between this pin and pin 124 TEST 126 - connect to 3.3 V OC1_N 127 AI port 1 analog (5 V input) and digital overcurrent input; if not used,

connect to V

through a 10 kΩ resistor

CC(I/O)

OC2_N 128 AI port 2 analog (5 V input) and digital overcurrent input; if not used,

connect to V

[1] Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals. [2] I = input only; O = output only; I/O = digital input/output; OD = open-drain output; AI/O = analog

input/output; AI = analog input; P = power.

through a 10 kΩ resistor

CC(I/O)

Product data sheet Rev. 01 — 8 November 2004 11 of 105

Philips Semiconductors

7. Functional description

7.1 ISP1760 internal architecture:Advanced Philips Slave Host Controller and hub

The EHCI block and the Hi-Speed USB hub block are the main components of the Advanced Philips Slave Host Controller.

The EHCI is the latest generation design, with improved data bandwidth. The EHCI in the ISP1760 is adapted from

Serial Bus Rev. 1.0

The internal Hi-Speed USB hub block replaces the companion Host Controller block used in the original PCI Hi-Speed USB Host Controllers to handle the full-speed and low-speed modes. The hardware architecture in the ISP1760 is simpliﬁed to help reduce cost and development time, by eliminating the additional work involved in implementing the OHCI software required to support the full-speed and low-speed modes.

Figure 3 shows the internal architecture of the ISP1760. The ISP1760 implements the

EHCI that has an internal port—the Root Hub port (not availableexternally)—on which the internal hub is connected. The three external ports are always routed to the internal hub. The internal hub is a Hi-Speed USB (USB 2.0) hub including the TT.

ISP1760

Embedded Hi-Speed USB host controller

Enhanced Host Controller Interface Speciﬁcation for Universal

Remark: The root hub must be enabled and the internal hub must be enumerated. Enumerate the internal hub as if it is externally connected. For details, refer to

Linux Programming Guide (AN10042)

At the Host Controller reset and initialization, the internal Root Hub port will be polled until a new connection is detected, showing the connection of the internal hub.

The internal Hi-Speed USB hub is enumerated using a sequence similar to a standard Hi-Speed USB hub enumeration sequence, and the polling on the Root Hub is stopped because the internal Hi-Speed USB hub will never be disconnected. When enumerated, the internal hub will report the three externally available ports.

ISP176x

Product data sheet Rev. 01 — 8 November 2004 12 of 105

Philips Semiconductors

ISP1760

Embedded Hi-Speed USB host controller

EHCI

ROOT HUB

PORTSC1

ENUMERATION

AND POLLING USING

ACTUAL PTDs

INTERNAL HUB (TT)

PORT1

Fig 3. Internal hub.

PORT2

7.2 Host Controller buffer memory block

7.2.1 General considerations

The internal addressable Host Controller buffer memory is 63 kbytes. The 63-kbyte effective memory size is the result of subtracting the size of registers (1 kbyte) from the total addressable memory space deﬁned in the ISP1760 (64 kbytes).This is the optimized value for achieving the highest performance with a minimal cost.

The ISP1760 is a slave Host Controller. This means that it does not need access to the local bus of the system to transfer data from the memory of the system to the ISP1760 internal memory, unlike the case of the original PCI Hi-Speed USB Host Controllers. Therefore, correct data must be transferred to both the Philips Transfer Descriptor (PTD) area and the payload area by Parallel I/O (PIO) (CPU access) or programmed DMA.

The ‘slave-host’ architecture ensures better compatibility with most of the processors present in the market today because not all processors allow a ‘bus-master’ on the local bus. It also allows better load balancing of the processor’s local bus because only the internal bus arbiter of the processor controls the transfer of data dedicated to USB. This preventsthe local bus from being busy when other more important transfersmay be in the queue; and therefore achieving a ‘linear’ system data ﬂow that has less impact on other processes running at the same time.

PORT3

EXTERNAL

PORTS

004aaa513

The considerations mentioned are also the main reason for implementing the prefetching technique, instead of using a READYsignal. The resulting architecture avoids ‘freezing’ of the local bus (by asserting READY), enhancing the ISP1760 memory access time, and avoiding introduction of programmed additional wait states. For details, see Section 7.3 and Section 8.3.8.

Product data sheet Rev. 01 — 8 November 2004 13 of 105

Philips Semiconductors

The total amount of memory allocated to the payload determines the maximum transfer size speciﬁed by a PTD—a larger internal memory size results in less CPU interruption for transfer programming. This means less time spent in context switching, resulting in better CPU usage.

A larger buffer also implies a larger amount of data can be transferred. The transfer, however, can be done over a longer period of time, to maintain the overall system performance. Each transfer of the USB data on the USB bus can span for up to a few milliseconds before requiring further CPU intervention for data movement.

The internal architecture of the ISP1760 allows a ﬂexible deﬁnition of the memory buffer for optimization of the data transfer on the CPU extension bus and the USB. It is possible to implement various data transfer schemes, depending on the number and type of USB devices present (for example: push-pull—data can be written to half of the memory while data in the other half is being accessed by the Host Controller and sent on the USB bus). This is useful especially when a high-bandwidth ‘continuous or periodic’ data ﬂow is required.

Through an analysis of the hardware and software environment regarding the usual data ﬂow and performance requirements of most embedded systems, Philips has determined the optimal size for the internal buffer as approximately 64 kbytes.

ISP1760

Embedded Hi-Speed USB host controller

7.2.2 Structure of the ISP1760 Host Controller memory

The 63-kbyte internal memory consists of the PTD area and the payload area. Both the PTD and payload memory zones are divided into three dedicated areas for each

main type of USB transfer: isochronous (ISO), interrupt (INT) and Acknowledged Transfer List (ATL). As shown in Table 3, the PTD areas for ISO, INT and ATL are grouped at the beginning of the memory, occupying the address range 0400h to 0FFFh, following the address space of the registers. The payload or data area occupies the next memory address range 1000h to FFFFh, meaning that 60 kbytes of memory are allocated for the payload data.

A maximum of 32 PTD areas and their allocated payload areas can be deﬁned for each type of transfer. The structure of a PTD is similar for every transfer type and consists of eight Double Words (DWs) that must be correctly programmed for a correct USB data transfer. The reserved bits of a PTD must be set to logic 0. A detailed description of the PTD structure can be found in Section 9.

The transfer size speciﬁed by the PTD determines the contiguous USB data transfer that can be performed without any CPU intervention. The respective payload memory area must be equal to the transfer size deﬁned. The maximum transfer size is ﬂexible and can be optimized, depending on the number and nature of USB devices or PTDs deﬁned and their respective MaxPacketSize.

The CPU will program the DMA to transfer the necessary data in the payload memory. The next CPU intervention will be required only when the current transfer is completed and DMA programming is necessary to transfer the next data payload. This is normally signaled by the IRQ that is generated by the ISP1760 on completing the current PTD, meaning all the data in the payload area was sent on the USB bus. The external IRQ signal is asserted according to the settings in the IRQ Mask OR or IRQ Mask AND registers, see Section 8.4.

Product data sheet Rev. 01 — 8 November 2004 14 of 105

Philips Semiconductors

The RAM is structured in blocks of PTDs and payloads so that while the USB is executing on an active transfer-based PTD, the processor can simultaneously ﬁll up another block area in the RAM. A PTD and its payload can then be updated on-the-ﬂy without stopping or delaying any other USB transaction or corrupting the RAM data.

Some of the design features are:

• The address range of the internal RAM buffer is from 0400h to FFFFh.

• The internal memory contains isochronous, interrupt and asynchronous PTDs, and

respective deﬁned payloads.

• All accesses to the internal memory are double-word aligned.

• Internal memory address range calculation:

Memory address = (CPU address – 0400h) (shift right >> 3). Base address is 0400h.

Table 3: Memory address

Memory map CPU address Memory address

ISO 0400h to 07FFh 0000h to 007Fh INT 0800h to 0BFFh 0080h to 00FFh ATL 0C00h to 0FFFh 0100h to 017Fh Payload 1000h to FFFFh 0180h to 1FFFh

ISP1760

Embedded Hi-Speed USB host controller

Product data sheet Rev. 01 — 8 November 2004 15 of 105

Philips Semiconductors

ISP1760

Embedded Hi-Speed USB host controller

USB BUS

63 kbytes

USB HIGH-SPEED

HOST AND

TRANSACTION

TRANSLATOR (FULL-SPEED

AND LOW-SPEED)

address data (64 bits)

PTD1

PTD2

. .

PTD32

PTD1 PTD2

. .

PTD32

PTD1

PTD2

. .

PTD32

PAYLOAD

. . . . . . . .

PAYLOAD

ARBITER

240 MB/s

ISOCHRONOUS

INTERRUPT

ASYNC

PAYLOAD

REGISTERS

MEMORY MAPPED

INPUT/OUTPUT,

MEMORY

MANAGEMENT

UNIT,

SLAVE DMA

CONTROLLER

AND

INTERRUPT

CONTROL

D[15:0]/D[31:0]

A[17:1]

CS_N

RD_N

WR_N

IRQ

DREQ

DACK

MICRO-

PROCESSOR

control signals

004aaa436

Fig 4. Memory segmentation and access block diagram.

Both the CPU interface logic and the USB Host Controller require access to the internal ISP1760 RAM at the same time. The internal arbiter controls these accesses to the internal memory, organized internally on a 64-bit data bus width, allowing a maximum bandwidth of 240 MB/s. This bandwidth avoids any bottleneck on accesses both from the CPU interface and the internal USB Host Controller.

7.3 Accessing the ISP1760 Host Controller memory: PIO and DMA

The CPU interface of the ISP1760 can be conﬁgured for a 16-bit or 32-bit data bus width. When the ISP1760 is conﬁgured for a 16-bit data bus width, the upper unused 16 data lines must be pulled up to V together to a single 10 kΩ pull-up resistor. The 16-bit or 32-bit data bus width conﬁguration is done by programming bit 8 of the HW Mode Control register. This will determine the register and memory access types in both PIO and DMA modes to all internal blocks: Host Controller, Peripheral Controller and OTG Controller. All accesses must be word-aligned for 16-bit mode and double-word aligned for 32-bit mode, where one word = 16 bits. When accessing the Host Controller registers in 16-bit mode, the

Product data sheet Rev. 01 — 8 November 2004 16 of 105

. This can be achieved by connecting DATA[31:16] lines

CC(I/O)

Philips Semiconductors

register access must alwaysbe completed using two subsequent accesses. In the case of a DMA transfer, the 16-bit or 32-bit data bus width conﬁguration will determine the number of bursts that will complete a certain transfer length.

In PIO mode, CS_N, WR_N and RD_N are used to access registers and memory. In DMA mode, the data validation is performed by DACK—instead of CS_N—together with the WR_N and RD_N signals. The DREQ signal will always be asserted as soon as the ISP1760 DMA is enabled, as described in the following section.

7.3.1 PIO mode access—memory read cycle

The following method has been implemented to reduce the read access timing in the case of a memory read:

• The Memory register contains the starting address and the bank selection to read

from the memory. Before every new read cycle of the same or different banks, an appropriate value is written to this register.

• Once a value is written to this register, the address is stored in the FIFO of that bank

and is then used to prefetch data for the memory read of that bank. For every subsequent read operation executed at a contiguous address, the address

pointer corresponding to that bank is automatically incremented to prefetch the next data to be sent to the CPU.

Memory read accesses for multiple banks can be interleaved. In this case, the FIFO block handles the MUXing of appropriate data to the CPU.

• The address written to the Memory register is incremented and used to successively

prefetch data from the memory irrespective of the value on the address bus for each bank, until a new value for a bank is written to the Memory register.

For example, consider the following sequence of operations:

– Write the starting (read) address 4000h and bank1 = 01 to the Memory register.

– Write the starting (read) address 4100h and bank2 = 10 to the Memory register.

ISP1760

Embedded Hi-Speed USB host controller

When RD_N is asserted for three cycles with A[17:16] = 01, the returned data corresponds to addresses 4000h, 4004h and 4008h.

Remark: Once 4000h is written to the Memory register for bank1, the bank select value determines the successive incremental addresses used to fetch the data. That is, the fetching of data is independent of the address on A[15:0] lines.

When RD_N is asserted for four cycles with A[17:16] = 10, the returned data corresponds to addresses 4100h, 4104h, 4108h and 410Ch.

Consequently, the RD_N assertion with A[17:16] = 01 will return data from 400Ch because the bank1 read stopped there in the previous cycle. Also, RD_N assertions with A[17:16] = 010 will now return data from 4110h because the bank2 read stopped there in the previous cycle.

7.3.2 PIO mode access—memory write cycle

The PIO memory write access is similar to a normal memory access. It is not necessary to set the prefetching address before a write cycle to the memory.

The ISP1760 internal write address will not be automatically incremented during consecutive write accesses, unlike in a series of ISP1760 memory read cycles. The memory write address must be incremented before every access.

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Philips Semiconductors

7.3.3 PIO mode access—register read cycle

The PIO register read access is similar to a general register access. It is not necessary to set a prefetching address before a register read.

The ISP1760 register read address will not be automatically incremented during consecutive read accesses, unlike in a series of ISP1760 memory read cycles. The ISP1760 register read address must be correctly speciﬁed before every access.

7.3.4 PIO mode access—register write cycle

The PIO register write access is similar to a general register access. It is not necessary to set a prefetching address before a register write.

The ISP1760 register write address will not be automatically incremented during consecutive write accesses, unlike in a series of ISP1760 memory read cycles. The ISP1760 register write address must be correctly speciﬁed before every access.

7.3.5 DMA—read and write operations

The internal ISP1760 Host Controller DMA is a slave DMA. The host system processor or DMA must ensure the data transfer to or from the ISP1760 memory.

ISP1760

Embedded Hi-Speed USB host controller

The ISP1760 DMA supports a DMA burst length of 1, 4, 8 and 16 cycles forboth the 16-bit and 32-bit data bus width. DREQ will be asserted at the beginning of the ﬁrst burst of a DMA transfer and will be deasserted on the last cycle (RD_N or WR_N active pulse) of that burst. It will be reasserted shortly after the DACK deassertion, as long as the DMA transfer counter was not reached. DREQ will be deasserted on the last cycle when the DMA transfer counter is reached and will not reasserted until the DMA reprogramming is performed. Both the DREQ and DACK signals are programmable as active LOW or active HIGH, according to the system requirements.

The DMA start address must be initialized in the respective register, and the subsequent transfers will automatically increment the internal ISP1760 memory address. A register or memory access or access to other system memory can occur in between DMA bursts, whenever the bus is released because DACK is deasserted, without affecting the DMA transfer counter or the current address.

Any memory area can be accessed by the system’sDMA at any starting address because there are no predeﬁned memory blocks. The DMA transfer must start on a word or Double Word address, depending on whether the data bus width is set to 16 bit or 32 bit. DMA is the most efﬁcient method to initialize the payload area, to reduce the CPU usage and overall system loading.

The ISP1760 does not implement EOT to signal the end of a DMA transfer. If programmed, an interrupt may be generated by the ISP1760 at the end of the DMA transfer.

The slave DMA of the ISP1760 will issue a DREQ to the DMA controller of the system to indicate that it is programmed for transfer and data is ready. The system DMA controller may also start a transfer without the need of the DREQ, if the ISP1760 memory is available for the data transfer and the ISP1760 DMA programming is completed.

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Philips Semiconductors

It is also possible that the system’s DMA will perform a memory-to-memory type of transfer between the system memory and the ISP1760 memory. The ISP1760 will be accessed in the PIO mode. Consequently, memory read operations must be preceded by initializing the Memory register (address 033Ch), as described in Section 7.3.1. No IRQ will be generated by the ISP1760 on completing the DMA transfer but an internal processor interrupt may be generated to signal that the DMA transfer is completed. This is mainly useful in implementing the double-buffering scheme for data transfer to optimize the USB bandwidth.

The ISP1760 DMA programming involves:

• Set the active levels of signals DREQ and DACK in the HW Mode Control register.

• The DMA Start Address register contains the ﬁrst memory address at which the data

transfer will start. It must be word-aligned in the 16-bit data bus mode and double word aligned in the 32-bit data bus mode.

• The programming of the DMA Conﬁguration register speciﬁes:

– The type of transfer that will be performed: read or write – The burstsize—expressed in bytes—is speciﬁed, regardless of the data bus width.

– The transferlength—expressed in number of bytes—deﬁnes the number of bursts.

– Enable ENABLE_DMA (bit 1) of the DMA Conﬁguration register to determine the

ISP1760

Embedded Hi-Speed USB host controller

For the same burst size, a double number of cycles will be generated in the 16-bit mode data bus width as compared to the 32-bit mode.

The DREQ will be deasserted and asserted to generate the next burst, as long as there are bytes to be transferred. At the end of a transfer, the DREQ will be deasserted and an IRQ can be generated if DMAEOTINT (bit 3 in the Interrupt register) is set. The maximum DMA transfersize is equal to the maximum memory size. The transfer size can be an odd or even number of bytes, as required. If the transfer size is an odd number of bytes, the number of bytes transferred by the system’s DMA is equal to the next multiple of two for the 16-bit data bus width or four for the 32-bit data bus width. For a write operation, however, only the speciﬁed odd number of bytes in the ISP1760 memory will be affected.

assertion of DREQ immediately after setting the bit.

After programming the preceding parameters, the system’sDMA maybe enabled (waiting for the DREQ to start the transfer or immediate transfer may be started).

The programming of the system’s DMA must match the ISP1760 DMA parameters programmed above. Only one DMA transfer may take place at a time. A PIO mode data transfer may occur simultaneously with a DMA data transfer, in the same or a different memory area.

7.4 Interrupts

The ISP1760 will assert an IRQ according to the source or event in the Interrupt register. The main steps to enable the IRQ assertion are:

1. Set GLOBAL_INTR_EN (bit 0) in the HW Mode Control register.

2. Deﬁne the IRQ active as levelor edge in INTR_LEVEL (bit 1) of the HW Mode Control register.

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Philips Semiconductors

3. Deﬁne the IRQ polarity as active LOW or active HIGH in INTR_POL (bit 2) of the HW Mode Control register. These settings must match the IRQ settings of the host processor.

By default, interrupt is level-triggered and active LOW.

4. Program the individual interrupt enable bits in the Interrupt Enable register. The software will need to clear the interrupt status bits in the Interrupt register before enabling individual interrupt enable bits.

Additional IRQ characteristics can be adjusted in the Edge Interrupt Count register, as necessary, applicableonly when IRQ is set to be edge-active (a pulse of a deﬁned width is generated every time IRQ is active).

Bits 15 to 0 of the Edge Interrupt Count register deﬁne the IRQ pulse width. The maximum pulse width that can be programmed is FFFFh, corresponding to a 1 ms pulse width. This setting is necessary for certain processors that may require a different minimum IRQ pulse width than the default value. The default IRQ pulse width set at power on is approximately 500 ns.

Bits 31 to 24 of the Edge Interrupt Count register deﬁne the minimum interval between two interrupts to avoid frequent interrupts to the CPU. The default value of 00h attributed to these bits determines the normal IRQ generation, without any delay. When a delay is programmed and the IRQ becomes active after the respective delay, several IRQ events may have already occurred.

ISP1760

Embedded Hi-Speed USB host controller

All the interrupt events are represented by the respective bits allocated in the Interrupt register. There is no mechanism to show the order or the moment of occurrence of an interrupt.

The asserted bits in the Interrupt register can be cleared by writing back the same valueto the Interrupt register. This means that writing logic 1 to each of the set bits will reset the corresponding bits to the initial inactive state.

The IRQ generation rules that apply according to the preceding settings are:

• If an event of interrupt occurs but the respective bit in the Interrupt Enable register is

not set, then the respective Interrupt register bit is set but the interrupt signal is not asserted.

An interrupt will be generated when interrupt is enabled and the respective bit in the Interrupt Enable register is set.

• For a level trigger, an interrupt signal remains asserted until the processor clears the

Interrupt register by writing logic 1 to clear the Interrupt register bits that are set.

• If an interrupt is made edge-sensitive and is asserted, writing to clear the Interrupt

• The clock stopping mechanism does not affect the generation of an interrupt. This is

useful during the suspend and resume cycles, when an interrupt is generated to signal a wake-up event.

The IRQ generation can also be conditioned by programming the IRQ Mask OR and IRQ Mask AND registers. Setting some of the bits in these registers to logic 1 will determine the IRQ generation only when the respective AND or OR conditions of completing the respective PTDs is met.

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Philips Semiconductors

With the help of the IRQ Mask AND and IRQ Mask OR registers for each type of transfer—ISO, INT and bulk—software can determine which PTDs get priority and an interrupt will be generated when the AND or OR conditions are met. The PTDs that are set will wait until the respective bits of the remaining PTDs are set and then all PTDs generate an interrupt request to the CPU together.

The registers deﬁnition shows that the AND or OR conditions are applicable to the same category of PTDs—ISO, INT, ATL.

When an IRQ is generated, the PTD Done Map registers and the respective V bits will show which PTDs were completed.

The rules that apply to the IRQ Mask AND or IRQ Mask OR settings are:

• TheOR mask has a higher priority over the AND mask. An IRQ is generated if bit n of

the done map is set and the corresponding bit n of the OR Mask register is set.

• If the OR mask for any done bit is not set, then the AND mask comes into picture. An

IRQ is generated if all the corresponding done bits of the AND Mask register are set. For example: If bits 2, 4 and 10 are set in the AND Mask register, an IRQ is generated only if bits 2, 4, 10 of the done map are set.

• If using the IRQ interval setting for the bulk PTD, an interrupt will only occur at the

regular time interval as programmed in the ATL Done Timeout register. Even if an interrupt event occurs before the timeout of the register, no IRQ will be generated until the time is up.

ISP1760

Embedded Hi-Speed USB host controller

For an example on using the IRQ Mask AND or IRQ Mask OR registers without the ATL Done Timeout register, see Table 4.

The AND function: Activate the IRQ only if PTDs 1, 2 and 4 are done. The OR function: If any of the PTDs 7, 8 or 9 are done, an IRQ for each of the PTD will be

raised.

Table 4: Using the IRQ Mask AND or IRQ Mask OR registers

PTD AND register OR register Time PTD done IRQ

11 0 1ms1 21 0 - 1 30 0 - - 4 1 0 3 ms 1 active because of AND 50 0 - - 60 0 - - 7 0 1 5 ms 1 active because of OR 8 0 1 6 ms 1 active because of OR 9 0 1 7 ms 1 active because of OR

7.5 Phase-Locked Loop (PLL) clock multiplier

The internal PLL requires a 12 MHz input, which can be a 12 MHz crystal or a 12 MHz clock already existing in the system with a precision better than 50 ppm. This allows the use of a low-cost 12 MHz crystal that also minimizes Electro-Magnetic Interference (EMI). When an external crystal is used, make sure the CLKIN pin is connected to V

CC(I/O)

Product data sheet Rev. 01 — 8 November 2004 21 of 105

Philips Semiconductors

The PLL block generates all the main internal clocks required for normal functionality of various blocks: 30 MHz, 48 MHz and 60 MHz.

No external components are required for the PLL operation.

7.6 Power management

The ISP1760 implements a ﬂexible power management scheme, allowing various power saving stages.

The usual powering scheme implies programming EHCI registers and the internal Hi-Speed USB (USB 2.0) hub in the same way it is done in the case of a PCI Hi-Speed USB Host Controller with a Hi-Speed USB hub attached.

When the ISP1760 is in suspend mode, the main internal clocks will be stopped to ensure minimum power consumption. An internal LazyClock of 100 kHz ± 40 % will continue running. This allows initiating a resume on one of the following events:

• External USB device connect or disconnect

• Assertion of the CS_N signal because of any access to the ISP1760

• Driving the SUSPEND/WAKEUP_N pin to a LOW level.

ISP1760

Embedded Hi-Speed USB host controller

The SUSPEND/WAKEUP_N pin is a bidirectional pin. This pin should be connected to one of the GPIO pins of a processor.

The awake state can be veriﬁed by reading the LOW level of this pin. If the level is HIGH, it means that the ISP1760 is in the suspend state.

The SUSPEND/WAKEUP_N pin requires a pull-up because in the ISP1760 suspended state the pin becomes three-state and can be pulled down, driving it externally by switching the processor’s GPIO line to the output mode to generate the ISP1760 wake-up.

The SUSPEND/WAKEUP_N pin is a three-state output. It is also an input to the internal wake-up logic.

When in suspend mode, the ISP1760 internal wake-up circuitry will sense the status of the SUSPEND/WAKEUP_N pin:

• If it remains pulled-up, no wake-up is generated because a HIGH is sensed by the

internal wake-up circuit.

• If the pin is externally pulled LOW (for example, by the GPIO line or just as a test by

jumper), the input to the wake-up circuitry becomes LOW and the wake-up is internally initiated.

The resume state has a clock-off count timer deﬁned by bits 31 to 16 of the Power Down Control register. The default value of this timer is 10 ms, meaning that the resume state will be maintained for 10 ms. If during this time, the RUN/STOP bit in the USBCMD register is set to logic 1, the Host Controller will go into a permanent resume—the normal functional state. If the RUN/STOP bit is not set during the time determined bythe clock-off count, the ISP1760 will switch back to suspend mode after the speciﬁed time. The maximum delay that can be programmed in the clock-off count ﬁeld is approximately 500 ms.

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Philips Semiconductors

Additionally, the Power Down Control register allows the ISP1760 internal blocks to be disabled for lower power consumption as deﬁned in Table 5.

The lowest suspend current that can be achieved is approximately 100 µA at room temperature. The suspend current will increase with the increase in temperature, with approximately 300 µA at 40 °C and up to a typical 1 mA at 85 °C. The system is not in suspend mode when its temperature increases above 40 °C. Therefore, even a 1 mA current consumption by the ISP1760 (in suspend mode) can be considered negligible. In normal environmental conditions, when the system is in suspend mode, the maximum ISP1760 temperature will be approximately 40 °C (determined by the ambient temperature) so the ISP1760 maximum suspend current will be below 300 µA. An alternative solution to achieve a very low suspend current is to completely switch off the V

CC(5V0)

pins of the processor. This is possible because the ISP1760 can be used in the hybrid mode, which allows only the V

The time from wake-up to suspend will be approximately 100 ms when the ISP1760 power is always on.

It is necessary to wait for the CLK_RDY interrupt assertion before programming the ISP1760 because internal clocks are stopped during deep-sleep suspend and restarted after the ﬁrst wake-up event. The occurrence of the CLK_RDY interrupt means that the internal clocks are running and the normal functionality is achieved.

ISP1760

Embedded Hi-Speed USB host controller

power input by using an external PMOS transistor, controlled by one of the GPIO

powered on to avoid loading of the system bus.

CC(I/O)

It is estimated that the CLK_RDY interrupt will be generated less than 100 µs after the wake-up event, if the power to the ISP1760 was on during suspend.

If the ISP1760 is used in the hybrid mode and V

CC(5V0)

is off during suspend, a 2 ms reset pulse is required when the power is switched back to on, before starting to program the resume state. This will ensure that the internal clocks are running and all logics reach a stable initial state.

7.7 Overcurrent detection

The ISP1760 can implement a digital or analog overcurrent detection scheme. Bit 15 of the HW Mode Control register can be programmed to select the analog or digital overcurrent detection. An analog overcurrent detection circuit is integrated on-chip. The main features of this circuit are self reporting, automatic resetting, low-trip time and low cost. This circuit offers an easy solution at no extra hardware cost on the board. The port power will be automatically disabled by the ISP1760 on an overcurrent event occurrence, by deasserting the PSWn_N signal without any software intervention.

When using the integrated analog overcurrent detection, the range of the overcurrent detection voltage for the ISP1760 is 45 mV to 100 mV. Calculation of the external components should be based on the 45 mV value, with the actual overcurrent detection threshold usually positioned in the middle of the interval.

Foran overcurrentlimit of 500 mA per port, a PMOS with R is required. If a PMOS with a lower R

is used, analog overcurrent detection can be

DSON

adjusted using a series resistor; see Figure 5.

of approximately 100 mΩ

DSON

∆V

Product data sheet Rev. 01 — 8 November 2004 23 of 105

PMOS

∆V

= ∆V

= voltage drop on PMOS

PMOS

TRIP

= ∆V

TRIP(intrinsic)

− (I

OC(nom)

× Rtd), where:

Philips Semiconductors

ISP1760

Embedded Hi-Speed USB host controller

OC(nom)

=1µA.

5 V

REF5V

PSWn_N

OC (1)

OCn_N

ISP1760

004aaa662

(1) Rtd is optional.

Fig 5. Adjusting analog overcurrent detection limit (optional).

The digital overcurrent scheme requires using an external power switch with integrated overcurrent detection, such as: LM3526, MIC2526 (2 ports) or LM3544 (4 ports). These devices are controlled by PSWn_N signals corresponding to each port. In the case of overcurrent occurrence, these devices will assert OCn_N signals. On OCn_N assertion, the ISP1760 cuts off the port power by deasserting PSWn_N. The external integrated power switch will also automatically cut-off the port power in the case of an overcurrent event, by implementing thermal shutdown. An internal delay ﬁlter of 1 ms to 3 ms will prevent false overcurrent reporting because of in-rush currents when plugging a USB device.

7.8 Power supply

Figure 6 shows the ISP1760 power supply connection.

ISP1760

CC(5V0)

6, 7

10, 40, 48, 59, 67, 75,

83, 94,

104, 115

5, 50, 118

004aaa533

CC(I/O)

REG(1V8)

10 µF

REG(1V8)

REG(3V3)

10 µF

100 nF

Fig 6. ISP1760 power supply connection.

Product data sheet Rev. 01 — 8 November 2004 24 of 105

3.3 V to 5 V

100 nF

1.65 V to 3.6 V

100 nF

Philips Semiconductors

Figure 7 shows the most commonly used power supply connection.

Fig 7. Most commonly used power supply connection.

ISP1760

6, 7, 10, 40, 48, 59, 67, 75, 83,

94, 104, 115

5, 50, 118

004aaa534

ISP1760

Embedded Hi-Speed USB host controller

, V

CC(5V0)

REG(1V8)

REG(3V3)

10 µF

CC(I/O

)

10 µF

100 nF

3.3 V

100 nF

7.9 Power-on reset (POR)

When V (t

) will be typically 800 ns. The pulse is started when V

PORP

(1.2 V). To give a better view of the functionality, Figure 8 shows a possible curve of V

dips at t2–t3 and t4–t5. If the dip at t4–t5 is too short (that is, < 11 µs), the internal POR pulse will not react and will remain LOW. The internal POR starts with a 1 at t0. At t1, the detector will see the passing of the trip level and a delay element will add another t before it drops to 0.

The internal POR pulse will be generated whenever V than 11 µs.

Fig 8. Internal power-on reset timing.

is directly connected to the RESET_N pin, the internal POR pulse width

CC(5V0)

rises above V

CC(5V0)

drops below V

CC(5V0)

V V

t0 t1

PORP

004aaa584

PORP

(1) PORP = power-on reset pulse.

CC(5V0) TRIP

CC(5V0)

TRIP

(1)

TRIP

with

PORP

for more

The RESET_N pin can be either connected to V

(using the internal POR circuit) or

CC(I/O)

externally controlled (by the microcontroller, ASIC, and so on). Figure 9 shows the availability of the clock with respect to the external POR.

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Philips Semiconductors

Fig 9. Clock with respect to the external power-on reset.

ISP1760

Embedded Hi-Speed USB host controller

RESET_N

EXTERNAL CLOCK

004aaa583

Stable external clock is available at A.

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Philips Semiconductors

8. Registers

Table 5 shows the bit description of the registers.

• All registers range from 0000h to 03FFh. These registers can be read or written as

double word, that is 32-bit data. In the case of a 16-bit data bus width, two subsequent accesses are necessary to complete the register read or write cycle.

• Operational registers range from 0000h to 01FFh. Conﬁguration registers range from

0300h to 03FFh.

Table 5: Register overview

Address Register Reset value References

EHCI capability registers

0000h CAPLENGTH 20h 0002h HCIVERSION 0100h 0004h HCSPARAMS 0000 0011h 0008h HCCPARAMS 0000 0086h

EHCI operational registers

0020h USBCMD 0008 0000h 0024h USBSTS 0000 1000h 0028h USBINTR 0000 0000h 002Ch FRINDEX 0000 0000h 0030h CTRLDSSEGMENT 0000 0000h 0060h CONFIGFLAG 0000 0000h 0064h PORTSC1 0000 2000h 0130h ISO PTD Done Map 0000 0000h 0134h ISO PTD Skip Map FFFF FFFFh 0138h ISO PTD Last PTD 0000 0000h 0140h INT PTD Done Map 0000 0000h 0144h INT PTD Skip Map FFFF FFFFh 0148h INT PTD Last PTD 0000 0000h 0150h ATL PTD Done Map 0000 0000h 0154h ATL PTD Skip Map FFFF FFFFh 0158h ATL PTD Last PTD 0000 0000h 0200h–02FFh reserved - -

Conﬁguration registers

0300h HW Mode Control 0000 0000h 0304h Chip ID 0001 1761h 0308h Scratch 0000 0000h 030Ch SW Reset 0000 0000h 0330h DMA Conﬁguration 0000 0000h 0334h Buffer Status 0000 0000h 0338h ATL Done Timeout 0000 0000h 033Ch Memory 0000 0000h

ISP1760

Embedded Hi-Speed USB host controller

Section 8.1.1 on page 28 Section 8.1.2 on page 28 Section 8.1.3 on page 28 Section 8.1.4 on page 29

Section 8.2.1 on page 30 Section 8.2.2 on page 31 Section 8.2.3 on page 32 Section 8.2.4 on page 33 Section 8.2.5 on page 34 Section 8.2.6 on page 34 Section 8.2.7 on page 35 Section 8.2.8 on page 36 Section 8.2.9 on page 37 Section 8.2.10 on page 37 Section 8.2.11 on page 37 Section 8.2.12 on page 38 Section 8.2.13 on page 38 Section 8.2.14 on page 38 Section 8.2.15 on page 38 Section 8.2.16 on page 39

Section 8.3.1 on page 39 Section 8.3.2 on page 41 Section 8.3.3 on page 41 Section 8.3.4 on page 41 Section 8.3.5 on page 42 Section 8.3.6 on page 43 Section 8.3.7 on page 44 Section 8.3.8 on page 44

Product data sheet Rev. 01 — 8 November 2004 27 of 105

Philips Semiconductors

ISP1760

Embedded Hi-Speed USB host controller

Table 5: Register overview

Address Register Reset value References

0340h Edge Interrupt Count 0000 000Fh Section 8.3.9 on page 45 0344h DMA Start Address 0000 0000h 0354h Power Down Control 03E8 1BA0h 0374h Port 1 Control 0086 0086h

Interrupt registers

0310h Interrupt 0000 0000h 0314h Interrupt Enable 0000 0000h 0318h ISO IRQ Mask OR 0000 0000h 031Ch INT IRQ Mask OR 0000 0000h 0320h ATL IRQ Mask OR 0000 0000h 0324h ISO IRQ Mask AND 0000 0000h 0328h INT IRQ Mask AND 0000 0000h 032Ch ATL IRQ Mask AND 0000 0000h

…continued

8.1 EHCI capability registers

8.1.1 CAPLENGTH register (R: 0000h)

The bit description of the Capability Length (CAPLENGTH) register is given in Table 6.

Section 8.3.10 on page 46 Section 8.3.11 on page 46 Section 8.3.12 on page 48

Section 8.4.1 on page 50 Section 8.4.2 on page 51 Section 8.4.3 on page 53 Section 8.4.4 on page 53 Section 8.4.5 on page 53 Section 8.4.6 on page 54 Section 8.4.7 on page 54 Section 8.4.8 on page 54

Table 6: CAPLENGTH register: bit description

Bit Symbol Access Value Description

7 to 0 CAPLENGTH

[7:0]

R 20h Capability Length: This is used as an offset. It

is added to the register base to ﬁnd the beginning of the operational register space.

8.1.2 HCIVERSION register (R: 0002h)

Table 7 shows the bit description of the Host Controller Interface Version Number

(HCIVERSION) register.

Table 7: HCIVERSION register: bit description

Bit Symbol Access Value Description

15 to 0 HCIVERSION

[15:0]

R 0100h Host Controller Interface Version Number: It

contains a BCD encoding of theversionnumberof the interface to which the Host Controller interface conforms.

8.1.3 HCSPARAMS register (R: 0004h)

The Host Controller Structural Parameters (HCSPARAMS) register is a set of ﬁelds that are structural parameters. The bit allocation is given in Table 8.

Table 8: HCSPARAMS register: bit allocation

Bit 31 30 29 28 27 26 25 24 Symbol reserved Reset 00000000 Access RRRRRRRR

Product data sheet Rev. 01 — 8 November 2004 28 of 105

Philips Semiconductors

ISP1760

Embedded Hi-Speed USB host controller

Bit 23 22 21 20 19 18 17 16 Symbol DPN[3:0] reserved P_INDI

CATOR

Reset 00000000 Access RRRRRRRR Bit 15 14 13 12 11 10 9 8 Symbol N_CC[3:0] N_PCC[3:0] Reset 00000000 Access RRRRRRRR Bit 7 6 5 4 3 2 1 0 Symbol PRR reserved PPC N_PORTS[3:0] Reset 00010001 Access RRRRRRRR

Table 9: HCSPARAMS register: bit description

Bit Symbol Description

31 to 24 - reserved; write logic 0 23 to 20 DPN[3:0] Debug Port Number: This ﬁeld identiﬁes which of the Host

Controller ports is the debug port. 19 to 17 - reserved; write logic 0 16 P_INDICATOR Port Indicators: This bit indicates whether the ports support port

indicator control. 15 to 12 N_CC[3:0] Number of Companion Controller: This ﬁeld indicates the number

of companion controllers associated with this Hi-Speed USB Host

Controller. 11 to 8 N_PCC[3:0] Number of Ports per Companion Controller: This ﬁeld indicates

the number of ports supported per companion Host Controller. 7 PRR Port Routing Rules: This ﬁeld indicates the method used for

mapping ports to the companion controllers. 6 to 5 - reserved; write logic 0 4 PPC Port Power Control: This ﬁeld indicates whether the Host Controller

implementation includes port power control. 3 to 0 N_PORTS[3:0] N_Ports: This ﬁeld speciﬁes the number of physical downstream

ports implemented on this Host Controller.

[1]

[1] For details on register bit description, referto

Serial Bus Rev. 1.0

Enhanced Host Controller Interface Speciﬁcation for Universal

8.1.4 HCCPARAMS register (R: 0008h)

The Host Controller Capability Parameters (HCCPARAMS) register is a four-byte register, and the bit allocation is given in Table 10.

Table 10: HCCPARAMS register: bit allocation

Bit 31 30 29 28 27 26 25 24 Symbol reserved Reset 00000000 Access RRRRRRRR

Product data sheet Rev. 01 — 8 November 2004 29 of 105

Philips Semiconductors

ISP1760

Embedded Hi-Speed USB host controller

Bit 23 22 21 20 19 18 17 16 Symbol reserved Reset 00000000 Access RRRRRRRR Bit 15 14 13 12 11 10 9 8 Symbol EECP[7:0] Reset 00000000 Access RRRRRRRR Bit 7 6 5 4 3 2 1 0 Symbol IST[3:0] reserved ASPC PFLF 64AC Reset 10000110 Access RRRRRRRR

Table 11: HCCPARAMS register: bit description

Bit Symbol Description

31 to 16 - reserved; write logic 0 15 to 8 EECP[7:0] EHCI Extended Capabilities Pointer: Default = implementation

dependent. This optional ﬁeld indicates the existence of a capabilities list.

7 to 4 IST[3:0] Isochronous Scheduling Threshold: Default = implementation

dependent. This ﬁeld indicates, relative to the current position of the executing Host Controller, where software can reliably update the

isochronous schedule. 3 - reserved; write logic 0 2 ASPC Asynchronous Schedule Park Capability: Default = implementation

dependent. If this bit is set to logic 1, the Host Controller supports the park

feature for high-speed queue heads in the Asynchronous Schedule. 1 PFLF Programmable Frame List Flag: Default = implementation dependent. If

this bit is cleared, the system software must use a frame list length of

1024 elements with this Host Controller.

If PFLF is set, the system software can specify and use a smaller frame

list and conﬁgure the host through the FLS ﬁeld of the USBCMD register. 0 64AC 64-bit Addressing Capability: This ﬁeld contains the addressing range

capability.

[1]

[1] For details on register bit description, referto

Serial Bus Rev. 1.0

Enhanced Host Controller Interface Speciﬁcation for Universal

8.2 EHCI operational registers

8.2.1 USBCMD register (R/W: 0020h)

The USB Command (USBCMD) register indicates the command to be executed by the serial Host Controller. Writing to this register causes a command to be executed. Table 12 shows the USBCMD register bit allocation.

Product data sheet Rev. 01 — 8 November 2004 30 of 105

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