Philips ISP1582 User Manual

ISP1582

Hi-Speed Universal Serial Bus peripheral controller

Rev. 03 — 25 August 2004 Preliminary data

1. General description

The ISP1582 is a cost-optimized and feature-optimized Hi-Speed Universal Serial Bus (USB) peripheral controller. It fully complies with

Speciﬁcation Rev. 2.0

full-speed (12 Mbit/s). The ISP1582 provides high-speed USB communication capacity to systems based

on microcontrollers or microprocessors. It communicates with a microcontroller or microprocessor of a system through a high-speed general-purpose parallel interface.

The ISP1582 supports automatic detection of Hi-Speed USB system operation. Original USB fall-back mode allows thedevice to remain operational under full-speed conditions. It is designed as a generic USB peripheral controller so that it can ﬁt into all existing device classes, such as imaging class, mass storage devices, communication devices, printing devices and human interface devices.

Universal Serial Bus

, supporting data transfer at high-speed (480 Mbit/s) and

The internal generic Direct Memory Access (DMA) block allows easy integration into data streaming applications.

The modular approach to implementing a USB peripheral controller allows the designer to select the optimum system microcontroller from the wide variety available. The ability to reuse existing architecture and ﬁrmware investments shortens the development time, eliminates risk and reduces cost. The result is fast and efﬁcient development of the most cost-effective USB peripheral solution.

The ISP1582 is ideally suited for many types of peripherals, such as: printers, scanners, digital still cameras, USB-to-Ethernet links, cable and DSL modems. The low power consumption during suspend mode allows easy design of equipment that is compliant to the ACPI™, OnNow™ and USB power management requirements.

The ISP1582 also incorporates features such as SoftConnect™, a reduced frequency crystal oscillator,andintegrated termination resistors. These features allow signiﬁcant cost savings in system design and easy implementation of advanced USB functionality into PC peripherals.

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2. Features

■ Complies fully with:

■ Supports data transfer at high-speed (480 Mbit/s) and full-speed (12 Mbit/s)

■ High performance USB peripheral controller with integrated Serial Interface

■ Automatic Hi-Speed USB mode detection and Original USB fall-back mode

■ Supports sharing mode

■ Supports V

■ High-speed DMA interface

■ Fully autonomous and multiconﬁguration DMA operation

■ 7 IN endpoints, 7 OUT endpoints and a ﬁxed control IN/OUT endpoint

■ Integrated physical 8 kbytes of multiconﬁguration FIFO memory

■ Endpoints with double buffering to increase throughput and ease real-time data

■ Bus-independent interface with most microcontrollers and microprocessors

■ 12 MHz crystal oscillator with integrated PLL for low EMI

■ Software-controlled connection to the USB bus (SoftConnect™)

■ Low-power consumption in operation and power-down modes; suitable for use in

■ Supports Session Request Protocol (SRP) that complies with

■ Internal power-on and low-voltage reset circuits; also supports software reset

■ Operation over the extended USB bus voltage range (DP, DM and V

■ 5 V tolerant I/O pads at 3.3 V

■ Operating temperature range from −40 °C to +85 °C

■ Available in HVQFN56 halogen-free and lead-free package.

ISP1582

Hi-Speed USB peripheral controller

◆

Universal Serial Bus Speciﬁcation Rev. 2.0

◆ Most Device Class speciﬁcations

◆ ACPI™, OnNow™ and USB power management requirements.

Engine (SIE), Parallel Interface Engine (PIE), FIFO memory and data transceiver

sensing

BUS

transfer

bus-powered USB devices

On-The-Go

Supplement to the USB Speciﬁcation Rev. 1.0a

)

BUS

3. Applications

■ Personal digital assistant

■ Digital video camera

■ Digital still camera

■ 3G mobile phone

■ MP3 player

■ Communication device, for example: router and modem

■ Printer

■ Scanner.

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4. Abbreviations

DMA — Direct Memory Access EMI — ElectroMagnetic Interference FS — Full-speed GDMA — Generic DMA HS — High-speed MMU — Memory Management Unit NRZI — Non-Return-to-Zero Inverted OTG — On-The-Go PDA — Personal Digital Assistant PID — Packet IDentiﬁer PIE — Parallel Interface Engine PIO — Parallel Input/Output PLL — Phase-Locked Loop SE0 — Single-Ended zero SIE — Serial Interface Engine SRP — Session Request Protocol USB — Universal Serial Bus.

ISP1582

Hi-Speed USB peripheral controller

5. Ordering information

Table 1: Ordering information

Type number

ISP1582BS HVQFN56 plastic thermal enhanced very thin quad ﬂat package;

Package Name Description Version

SOT684-1

no leads; 56 terminals; body 8 × 8 × 0.85 mm

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6. Block diagram

Philips Semiconductors

3.3 V

1.5 kΩ

RREF

12.0 kΩ

RESET_N

RPU

53, 54

3.3 V

to/from USB

HI-SPEED USB

TRANSCEIVER

POWER-ON

RESET

analog supply

VOLT AGE

REGULATORS

13, 26, 29, 41

12 MHz

DMDP

43495251

BUS

XTAL2XTAL1

ISP1582

SoftConnect

MEMORY

MANAGEMENT

UNIT

INTEGRATED

RAM

(8 KBYTES)

I/O pad

supply

21, 34, 4828, 50

CC(I/O)

1, 5

CC(1V8)

internal reset

digital supply

PHILIPS

SIE/PIE

SYSTEM

CONTROLLER

SUSPEND WAKEUPAGNDDGND

5556

DMA

HANDLER

DMA

REGISTERS

MICRO-

CONTROLLER

HANDLER

OTG SRP

MODULE

DREQ DIOR

DACK

9101112

INTERFACE

CONTROLLER

INTERFACE

DIOW

DMA

MICRO-

30 to 33, 35 to 40, 42 to 47

18 to 20, 22 to 25,

15 16 17

004aaa199

EOT

DATA[15:0

A[7:0 CS_N

RD_N WR_N

INT

]

Fig 1. Block diagram.

Hi-Speed USB peripheral controller

ISP1582

Philips Semiconductors

7. Pinning information

7.1 Pinning

AGND

RPU

AGND

RREF

RESET_N

EOT

DREQ

DACK

DIOR

DIOW

DGND

INT

Hi-Speed USB peripheral controller

BUS

CC(1V8)

XTAL1

ISP1582BS

19 A1

XTAL2 515349

20 A2

WAKEUP

SUSPEND

56 1 42 2 3 4 5 6 7 8 9

10 11 12 13 14

171518

CS_N

RD_N

WR_N

CC(I/O)

DATA15 474648

DATA14

DATA13 45

25 A6

DGND

DATA12

DATA11

CC(1V8)

41 40 39 38 37 36 35 34 33 32 31 30 29

ISP1582

DATA10 DGND DATA9 DATA8 DATA7

DATA6 DATA5

DATA4 V

CC(I/O)

DATA3 DATA2 DATA1 DATA0 DGND

004aaa536

Fig 2. Pin conﬁguration HVQFN56 (top view).

CC(I/O)

201822

GND (exposed die pad)

ISP1582BS

terminal 1

XTAL1

XTAL2

CC(1V8)

INT

DGND

DIOW

DIOR DACK DREQ

EOT

RESET_N

RREF

AGND

RPU

AGND

Bottom View

CS_N

WR_N

RD_N

15 14 29 13 12 11 10

9 8 7 6 5 4 3 2 1

545653

WAKEUP

SUSPEND

BUS

242523

CC(I/O)

DATA15

DGND 26

DATA13

DATA14

CC(1V8)

30 31 32 33 34 35 36 37 38 39 40 41 42

DATA11

DATA12

DGND DATA0 DATA1 DATA2 DATA3

CC(I/O)

DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DGND DATA10

004aaa377

Fig 3. Pin conﬁguration HVQFN56 (bottom view).

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7.2 Pin description

Table 2: Pin description

Symbol

AGND 1 - analog ground RPU 2 A connect to the external pull-up resistor for pin DP; must be

DP 3 A USB D+ line connection (analog) DM 4 A USB D− line connection (analog) AGND 5 - analog ground RREF 6 A connect to the external bias resistor; must be connected to

RESET_N 7 I reset input (500 µs); a LOW levelproducesanasynchronous

EOT 8 I End-of-transfer input (programmable polarity); used in DMA

DREQ 9 O DMA request (programmable polarity) output; when not in

DACK 10 I DMA acknowledge input (programmable polarity); when not

DIOR 11 I DMA read strobe input (programmable polarity); when not in

DIOW 12 I DMA write strobe input (programmable polarity); when not in

DGND 13 - digital ground INT 14 O interrupt output; programmable polarity (active HIGH or

CS_N 15 I chip select input

RD_N 16 I read strobe input

WR_N 17 I write strobe input

[1]

Pin Type

ISP1582

Hi-Speed USB peripheral controller

[2]

Description

connected to 3.3 V via a 1.5 kΩ resistor

ground via a 12.0 kΩ±1 % resistor

reset; connect to V circuit)

TTL; 5 V tolerant

slavemodeonly; when not in use, connect this pin to V through a 10 kΩ resistor

input pad; TTL; 5 V tolerant

use, connect this pin to ground through a 10 kΩ resistor; see

Table 54 and Table 55

TTL; 4 ns slew-rate control

in use, connect this pin to V see Table 54 and Table 55

TTL; 5 V tolerant

use, connect this pin to V

Table 54 and Table 55

TTL; 5 V tolerant

use, connect this pin to V

Table 54 and Table 55

TTL; 5 V tolerant

LOW) and signaling (edge or level triggered) CMOS output; 8 mA drive

input pad; TTL; 5 V tolerant

for the power-on reset (internal POR

through a 10 kΩ resistor;

CC(I/O)

through a 10 kΩ resistor; see

CC(I/O)

through a 10 kΩ resistor; see

CC(I/O)

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Philips Semiconductors

ISP1582

Hi-Speed USB peripheral controller

Table 2: Pin description

Symbol

[1]

Pin Type

…continued

[2]

Description

A0 18 I bit 0 of the address bus

input pad; TTL; 5 V tolerant

A1 19 I bit 1 of the address bus

input pad; TTL; 5 V tolerant

A2 20 I bit 2 of the address bus

input pad; TTL; 5 V tolerant

[3]

CC(I/O)

21 - supply voltage; used to supply voltage to the I/O pads; see

Section 8.14

A3 22 I bit 3 of the address bus

input pad; TTL; 5 V tolerant

A4 23 I bit 4 of the address bus

input pad; TTL; 5 V tolerant

A5 24 I bit 5 of the address bus

input pad; TTL; 5 V tolerant

A6 25 I bit 6 of the address bus

input pad; TTL; 5 V tolerant DGND 26 - digital ground A7 27 I bit 7 of the address bus

input pad; TTL; 5 V tolerant

[3]

CC(1V8)

28 - regulator output voltage (1.8 V ± 0.15 V); tapped out voltage

from the internal regulator; this regulated voltage cannot

drive external devices; decouple this pin using a 0.1 µF

capacitor; see Section 8.14 DGND 29 - digital ground DATA0 30 I/O bit0 of bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant DATA1 31 I/O bit1 of bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant DATA2 32 I/O bit2 of bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant DATA3 33 I/O bit3 of bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

[3]

CC(I/O)

34 - supply voltage; used to supply voltage to the I/O pads; see

Section 8.14

DATA4 35 I/O bit4 of bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant DATA5 36 I/O bit5 of bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant DATA6 37 I/O bit6 of bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant DATA7 38 I/O bit7 of bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

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ISP1582

Hi-Speed USB peripheral controller

Table 2: Pin description

Symbol

[1]

Pin Type

…continued

[2]

Description

DATA8 39 I/O bit8 of bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant DATA9 40 I/O bit9 of bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant DGND 41 - digital ground DATA10 42 I/O bit10 of bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant DATA11 43 I/O bit11 of bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant DATA12 44 I/O bit12 of bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant DATA13 45 I/O bit13 of bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant DATA14 46 I/O bit14 of bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant DATA15 47 I/O bit15 of bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

[3]

CC(I/O)

48 - supply voltage; used to supply voltage to the I/O pads; see

Section 8.14

BUS

49 A USB bus power pin sensing input; used to detect whether

the host is connected or not; it is an output for V

in OTG mode; when V

is not detected, pin RPU is

BUS

pulsing

internally disconnected from pin DP in approximately 4 ns;

connect a 1 µF electrolytic capacitor and a 1 MΩ pull-down

resistor to ground; see Section 8.12

5 V tolerant

[3]

CC(1V8)

50 - regulator output voltage (1.8 V ± 0.15 V); tapped out voltage

from the internal regulator; this regulated voltage can drive

external devices up to 1 mA; decouple this pin using 4.7 µF

and 0.1 µF capacitors; see Section 8.14 XTAL2 51 O crystal oscillator output (12 MHz); connect a fundamental

parallel-resonant crystal; leave this pin open-circuit when

using an external clock source on pin XTAL1; see Table 83 XTAL1 52 I crystal oscillator input (12 MHz); connect a fundamental

parallel-resonant crystal or an external clock source (leaving

pin XTAL2 unconnected); see Table 83

[3]

53 - supply voltage (3.3 V ± 0.3 V); this pin supplies the internal

voltage regulator and the analog circuit; see Section 8.14

[3]

54 - supply voltage (3.3 V ± 0.3 V); this pin supplies the internal

voltage regulator and the analog circuit; see Section 8.14

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ISP1582

Hi-Speed USB peripheral controller

Table 2: Pin description

Symbol

[1]

Pin Type

…continued

[2]

Description

WAKEUP 55 I wake-up input; when this pin is at the HIGH level, the chip is

prevented from getting into the suspend state and the chip

wakes up from the suspend state; when not in use, connect

this pin to ground through a 10 kΩ resistor

input pad; TTL; 5 V tolerant SUSPEND 56 O suspend state indicator output; used as a power switch

control output for powered-off application or as a resume

signal to the CPU for powered-on application

CMOS output; 8 mA drive GND exposed

die pad

[1] Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals. [2] All outputs and I/O pins can source 4 mA. [3] Add a decoupling capacitor (0.1 µF) to all the supply pins. For better EMI results, add a 0.01 µF

capacitor in parallel to the 0.1 µF.

- ground supply; down bonded to the exposed die pad (heatsink); to be connected to DGND during PCB layout

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8. Functional description

The ISP1582 is a high-speed USB peripheral controller. It implements the Hi-Speed USB or the Original USB physical layer and the packet protocol layer. It maintains up to 16 USB endpoints concurrently (control IN and control OUT, 7 IN and 7 OUT conﬁgurable) along with endpoint EP0 setup, which accesses the setup buffer. The USB Chapter 9 protocol handling is executed by means of external ﬁrmware.

For high-bandwidth data transfer, the integrated DMA handler can be invoked to transfer data to or from external memory or devices. The DMA interface can be conﬁgured by writing to the proper DMA registers (see Section 9.4).

The ISP1582 supports Hi-Speed USB and Original USB signaling. The USB signaling speed is automatically detected.

The ISP1582 has 8 kbytes of internal FIFO memory, which is shared among the enabled USB endpoints.

There are 7 IN endpoints, 7 OUT endpoints and 2 control endpoints that are a ﬁxed 64 bytes long. Any of the 7 IN and 7 OUT endpoints can be separately enabled or disabled. The endpoint type (interrupt, isochronous or bulk) and packet size of these endpoints can be individually conﬁgured depending on the requirements of the application. Optional double buffering increases the data throughput of these data endpoints.

ISP1582

Hi-Speed USB peripheral controller

The ISP1582 requires 3.3 V power supply. It has 5 V tolerant I/O pads when operating at V transceiver.

The ISP1582 operates on a 12 MHz crystal oscillator. An integrated 40× PLL clock multiplier generates the internal sampling clock of 480 MHz.

= 3.3 V and an internal 1.8 V regulator for powering the analog

CC(I/O)

8.1 DMA interface, DMA handler and DMA registers

The DMA block can be subdivided into two blocks: the DMA handler and the DMA interface.

The ﬁrmware writes to the DMA command register to start a DMA transfer (see

Table 47). The command opcode determines whether a generic DMA or PIO transfer

will start. The handler interfaces to the same FIFO (internal RAM) as used by the USB core. On receiving the DMA command, the DMA handler directs the data from the endpoint FIFO to the external DMA device or from the external DMA device to the endpoint FIFO.

The DMA interface conﬁgures the timing and the DMA handshake. Data can be transferred using either the DIOR and DIOW strobes or by the DACK and DREQ handshakes. The DMA conﬁgurations are set up by writing to the DMA Conﬁguration register (see Table 52 and Table 53).

For a generic DMA interface, Generic DMA (GDMA) slave mode can be used. Remark: The DMA endpoint buffer length must be a multiple of 4 bytes. For details on DMA registers, see Section 9.4.

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8.2 Hi-Speed USB transceiver

The analog transceiver directly interfaces to the USB cable through integrated termination resistors. The high-speed transceiver requires an external resistor (12.0 kΩ±1 %) between pin RREF and ground to ensure an accurate current mirror that generates the Hi-Speed USB current drive. A full-speed transceiver is integrated as well. This makes the ISP1582 compliant to Hi-Speed USB and Original USB, supporting both the high-speed and full-speed physical layers. After automatic speed detection, the Philips Serial Interface Engine (SIE) sets the transceiver to use either high-speed or full-speed signaling.

8.3 MMU and integrated RAM

The Memory Management Unit (MMU) and the integrated RAM provide the conversion between the USB speed (full-speed: 12 Mbit/s, high-speed: 480 Mbit/s) and the microcontroller handler or the DMA handler. The data from the USB bus is stored in the integrated RAM, which is cleared only when the microcontroller has read or written all data from or to the corresponding endpoint buffer or when the DMA handler has read or written all data from or to the endpoint buffer. The OUT endpoint buffer can also be cleared forcibly by setting bit CLBUF in the Control Function register. A total of 8 kbytes RAM is available for buffering.

ISP1582

Hi-Speed USB peripheral controller

8.4 Microcontroller interface and microcontroller handler

The microcontroller handler allows the external microcontroller or microprocessor to access the register set in the Philips SIE as well as the DMA handler. The initialization of the DMA conﬁguration is done through the microcontroller handler.

8.5 OTG SRP module

The OTG supplement deﬁnes a Session Request Protocol (SRP), which allows a B-device to request the A-device to turn on V allows the A-device, which may be battery-powered, to conserve power by turning off V

when there is no bus activity while still providing a means for the B-device to

BUS

initiate bus activity. Any A-device, including a PC or laptop, can respond to SRP. Any B-device, including

a standard USB peripheral, can initiate SRP. The ISP1582 is a device that can initiate SRP.

and start a session. This protocol

BUS

8.6 Philips high-speed transceiver

8.6.1 Philips Parallel Interface Engine (PIE)

In the high-speed (HS) transceiver, the Philips PIE interface uses a 16-bit parallel bidirectional data interface. The functions of the HS module also include bit-stufﬁng or destufﬁng and Non-Return-to-Zero Inverted (NRZI) encoding or decoding logic.

8.6.2 Peripheral circuit

To maintain a constant current driver for HS transmit circuits and to bias other analog circuits, an internal band gap reference circuit and an RREF resistor form the reference current. This circuit requires an external precision resistor (12.0 kΩ±1%) connected to the analog ground.

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8.6.3 HS detection

The ISP1582 handles more than one electrical state—full-speed (FS) or high-speed (HS)—under the USB speciﬁcation. When the USB cable is connected from the peripheral to the host controller, the ISP1582 defaults to the FS state until it sees a bus reset from the host controller.

During the bus reset, the peripheral initiates an HS chirp to detect whether the host controller supports Hi-Speed USB or Original USB. Chirping must be done with the pull-up resistor connected and the internal termination resistors disabled. If the HS handshake shows that there is an HS host connected, then the ISP1582 switches to the HS state.

In the HS state, the ISP1582 should observe the bus for periodic activity. If the bus remains inactive for 3 ms, the peripheral switches to the FS state to check for a Single-Ended Zero (SE0) condition on the USB bus. If an SE0 condition is detected for the designated time (100 µs to 875 µs; refer to section 7.1.7.6 of the USB speciﬁcation Rev. 2.0), the ISP1582 switches to the HS chirp state to perform an HS detection handshake. Otherwise, the ISP1582 remains in the FS state adhering to the bus-suspend speciﬁcation.

ISP1582

Hi-Speed USB peripheral controller

8.7 Philips Serial Interface Engine (SIE)

The Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no ﬁrmware intervention. The functions of this block include: synchronization pattern recognition, parallel or serial conversion, bit (de)stufﬁng, CRC checking or generation, Packet IDentiﬁer (PID) veriﬁcation or generation, address recognition, handshake evaluation or generation.

8.8 SoftConnect

The connection to the USB is established by pulling pin DP (for full-speed devices) HIGH through a 1.5 kΩ pull-up resistor. In the ISP1582, an external 1.5 kΩ pull-up resistor must be connected between pin RPU and 3.3 V. Pin RPU connects the pull-up resistor to pin DP, when bit SOFTCT in the Mode register is set (see Table 20 and Table 21). After a hardware reset, the pull-up resistor is disconnected by default (bit SOFTCT = 0). The USB bus reset does not change the value of bit SOFTCT.

When the V the back-drive voltage.

is not present, the SOFTCT bit must be set to logic 0 to comply with

BUS

8.9 System controller

The system controller implements the USB power-down capabilities of the ISP1582. Registers are protected against data corruption during wake-up following a resume (from the suspend state) by locking the write access until an unlock code has been written in the Unlock Device register (see Table 73 and Table 74).

8.10 Output pins status

Table 3 illustrates the behavior of output pins when V

various operating conditions.

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is supplied with VCC in

CC(I/O)

Philips Semiconductors

ISP1582

Hi-Speed USB peripheral controller

Table 3: ISP1582 pin status

0V V 0V V 0V−> 3.3 V V

3.3 V V

[1] X: Don’t care. [2] Dead: The USB cable is plugged-out and V [3] Plug-out: The USB cable is not present but V [4] Plug-in: The USB cable is being plugged-in and V

CC(I/O)

CC CC CC CC CC

[1]

State Pin

[2]

dead plug-out plug-in

[3]

[4]

reset LOW HIGH LOW high-Z high-Z normal HIGH HIGH LOW high-Z high-Z

CC(I/O)

8.11 Interrupt

8.11.1 Interrupt output pin

The Interrupt Conﬁguration register of the ISP1582 controls the behavior of the INT output pin. The polarity and signaling mode of pin INT can be programmed by setting bits INTPOL and INTLVL of the Interrupt Conﬁguration register (R/W: 10h); see

Table 24. Bit GLINTENA of the Mode register (R/W: OCh) is used to enable pin INT.

Default settings after reset are active LOW and level mode. When pulse mode is selected, a pulse of 60 ns is generated when the OR-ed combination of all interrupt bits changes from logic 0 to logic 1.

RESET_N INT_N SUSPEND DREQ DATA[15:0]

XXXXX X LOW HIGH high-Z input X LOW HIGH high-Z high-Z

is not available.

is available.

CC(I/O)

Figure 4 shows the relationship between the interrupt events and pin INT.

Each of the indicated USB and DMA events is logged in a status bit of the Interrupt register and the DMA Interrupt Reason register, respectively. Corresponding bits in the Interrupt Enable register and the DMA Interrupt Enable register determine whether or not an event will generate an interrupt.

Interrupts can be masked globally by means of bit GLINTENA of the Mode register; see Table 21.

Field CDBGMOD[1:0] of the Interrupt Conﬁguration register controls the generation of the INT signals for the control pipe. Field DDBGMODIN[1:0] of the Interrupt Conﬁguration register controls the generation of the INT signals for the IN pipe. Field DDBGMODOUT[1:0] of the Interrupt Conﬁguration register controls the generation of the INT signals for the OUT pipe; see Table 25.

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DMA Interrupt Reason

EXT_EOT

INT_EOT

DMA_XFER_OK

IE_EXT_EOT

IE_INT_EOT

IE_DMA_XFER_OK

DMA Interrupt Enable

Interrupt Enable register

IEBRESET

IESOF

IEDMA

IEP7RX IEP7TX

Interrupt register

BRESET

SOF

..........

DMA

....................

INT

LATCH

PULSE/LEVEL GENERATOR

Interrupt Configuration

INTPOL

Hi-Speed USB peripheral controller

Fig 4. Interrupt logic.

EP7RX EP7TX

GLINTENA

Mode register

004aaa275

ISP1582

Philips Semiconductors

8.11.2 Interrupt control

Bit GLINTENA in the Mode register is a global enable/disable bit. The behavior of this bit is given in Figure 5.

Event A: When an interrupt event occurs (for example, SOF interrupt) with bit GLINTENA set to logic 0, an interrupt will not be generated at pin INT. It will, however, be registered in the corresponding Interrupt register bit.

Event B: When bit GLINTENA is set to logic 1, pin INT is asserted because bit SOF in the Interrupt register is already set.

Event C: If the ﬁrmware sets bit GLINTENA to logic 0, pin INT will still be asserted. The bold dashed line shows the desired behavior of pin INT.

Deassertion of pin INT can be achieved either by clearing all the Interrupt register or the DMA Interrupt Reason register, depending on the event.

Remark: When clearing an interrupt event, perform write to all the bytes of the register.

For more information on interrupt control, see Section 9.2.2, Section 9.2.5 and

Section 9.5.1.

ISP1582

Hi-Speed USB peripheral controller

8.12 V

Pin V with bit CLKAON set to logic 0 (clock off option).

To detect whether the host is connected or not, that is V and a 1 µF electrolytic capacitor must be added to damp the overshoot upon plug-in.

INT pin

GLINTENA = 0

(during this time,

an interrupt event

occurs. For example,

SOF asserted.)

Pin INT: HIGH = deassert; LOW = assert (individual interrupts are enabled).

GLINTENA = 1

SOF asserted

Fig 5. Behavior of bit GLINTENA.

sensing

BUS

is one of the ways to wake up the clock when the ISP1582 is suspended

BUS

ISP1582

1 MΩ

1 µF

GLINTENA = 0

SOF asserted

004aaa394

sensing, a 1 MΩ resistor

USB

Connector

004aaa440

Fig 6. Resistor and electrolytic capacitor needed for V

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sensing.

BUS

Philips Semiconductors

ISP1582

Hi-Speed USB peripheral controller

004aaa441 004aaa442

Fig 7. Oscilloscope reading: no resistor

and capacitor in the network.

8.13 Power-on reset

The ISP1582 requires a minimum pulse width of 500 µs. Pin RESET_N can be either connected to VCC (using the internal POR circuit) or

externally controlled (by the microcontroller, ASIC, and so on). When VCC is directly connected to pin RESET_N, the internal pulse width t

The power-on reset function can be explained by viewing the dips at t2-t3 and t4-t5 on the V

CC(POR)

t0 — The internal POR starts with a HIGH level. t1 — The detector will see the passing of the trip level and a delay element will add

another t

PORP

t2-t3 — The internal POR pulse will be generated whenever V V

for more than 11 µs.

trip

t4-t5 — The dip is too short (< 11 µs) and the internal POR pulse will not react and will remain LOW.

curve (Figure 9).

before it drops to LOW.

Fig 8. Oscilloscope reading: with

resistor and capacitor in the network.

will be typically 200 ns.

PORP

CC(POR)

drops below

BAT(POR)

trip

t0 t1

PORP

(1) PORP = power-on reset pulse.

PORP

(1)

PORP

004aaa389

Fig 9. POR timing.

Figure 10 shows the availability of the clock with respect to the external POR.

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Fig 10. Clock with respect to the external POR.

8.14 Power supply

The ISP1582 can be powered by 3.3 V ± 0.3 V, and 3.3 V at the interface. For connection details, see Figure 11.

If the ISP1582 is powered by VCC= 3.3 V, an integrated 3.3 V-to-1.8 V voltage regulator provides a 1.8 V supply voltage for the internal logic.

ISP1582

Hi-Speed USB peripheral controller

POR

EXTERNAL CLOCK

004aaa365

Stable external clock is to be available at A.

In sharing mode (that is, when VCC is not present and V

is present), all the I/O

CC(I/O)

pins are in three-state, the interrupt pin is connected to ground, and the suspend pin is connected to V

ISP1582

CC(I/O)

53, 54

. See Table 3.

CC(I/O)

0.01 µF 0.1 µF

CC(1V8)

(1)

4.7 µF

CC(1V8)

0.1 µF

0.01 µF

0.1 µF

0.01 µF

0.1 µF

3.3 V ± 0.3 V

0.1 µF

004aaa203

(1) It is mandatory to use a 4.7 µF electrolytic capacitor on V

0.1 µF

CC(1V8)

Fig 11. ISP1582 with 3.3 V supply.

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Table 4 shows power modes in which the ISP1582 can be operated.

Table 4: Power modes

BUS

self-powered self-powered self-powered V

BUS

[1] Power supply to the IC (VCC) is 3.3 V. Therefore, if the application is bus-powered, a 3.3 V regulator

[2] V

8.14.1 Power-sharing mode

[1]

needs to be used.

CC(I/O)=VCC

. If the application is bus-powered, a voltage regulator needs to be used.

CC(I/O)

[2]

BUS

self-powered power-sharing (hybrid)

To GPIO of processor

for sensing V

BUS

1.5 kΩ

5 V-to-3.3 V

VOLTAGE

REGULATOR

ISP1582

Hi-Speed USB peripheral controller

Power mode

bus-powered

RPU

CC(I/O)

−

ISP1582

BUS

004aaa457

1 µF

−

BUS

USB

1 MΩ

Fig 12. Power-sharing mode.

As can be seen in Figure 12, in power-sharing mode, VCCis supplied by the output of the 5 V-to-3.3 V voltage regulator. The input to the regulator is from V

BUS

. V

CC(I/O)

is supplied through the power source of the system. When the USB cable is plugged in, the ISP1582 goes through the power-on reset cycle. In this mode, OTG is disabled.

The processor will experience continuous interrupt because the default status of the interrupt pin when operating in sharing mode with the V overcomethis,implement external V

sensing circuitry.The output from the voltage

BUS

not present is LOW. To

BUS

regulator can be connected to pin GPIO of the processor to qualify the interrupt from the ISP1582.

Remark: When the core power is removed, the ISP1582 must be reset using the RESET_N pin. The reset pulse width must be 2 ms.

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CC(I/O)

ISP1582

Hi-Speed USB peripheral controller

INT

power off

004aaa469

Fig 13. Interrupt pin status during power off in power-sharing mode.

Table 5: Operation truth table for SoftConnect

ISP1582 operation Power supply Bit SOFTCT in

CC(I/O)

RPU

Mode register

BUS

(3.3 V)

Normal bus operation 3.3 V 3.3 V 3.3 V 5 V enabled Core power is lost 0 V 3.3 V 0 V 0 V not applicable

Table 6: Operation truth table for clock off during suspend

ISP1582 operation Power supply Clockoffduring

CC(I/O)

RPU

BUS

suspend

(3.3 V)

Clock will wake up:

3.3 V 3.3 V 3.3 V 5 V enabled After resume and After a bus reset

Core power is lost 0 V 3.3 V 0 V 0 V not applicable

Table 7: Operation truth table for back voltage compliance

ISP1582 operation Power supply Bit SOFTCT in

CC(I/O)

RPU

Mode register

BUS

(3.3 V)

Back voltage is not measured in this

3.3 V 3.3 V 3.3 V 5 V enabled

mode Back voltage is not an issue because

0 V 3.3 V 0 V 0 V not applicable

core power is lost

Table 8: Operation truth table for OTG

ISP1582 operation Power supply OTG register

CC(I/O)

RPU

BUS

(3.3 V)

SRP is not applicable 3.3 V 3.3 V 3.3 V 5 V not applicable

OTG is not possible because V

BUS

0 V 3.3 V 0 V 0 V not applicable

not present and so core power is lost

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8.14.2 Self-powered mode

ISP1582

Hi-Speed USB peripheral controller

1.5 kΩ

RPU

CC(I/O)

−

ISP1582

BUS

004aaa460

1 µF

BUS

−

USB

1 MΩ

Fig 14. Self-powered mode.

In self-powered mode, VCC and V

are supplied by the system. Bit SOFTCT in

CC(I/O)

the Mode register must be always logic 1. See Figure 14.

Table 9: Operation truth table for SoftConnect

ISP1582 operation Power supply Bit SOFTCT in

CC(I/O)

RPU (3.3 V)

Normal bus operation 3.3 V 3.3 V 3.3 V 5 V enabled No pull-up on DP 3.3 V 3.3 V 3.3 V 0 V

[1] When the USB cable is removed, SoftConnect is disabled.

Mode register

BUS

[1]

disabled

Table 10: Operation truth table for clock off during suspend

ISP1582 operation Power supply Clock off

during suspend

Clock will wake up:

CC(I/O)

RPU

BUS

(3.3 V)

3.3 V 3.3 V 3.3 V 5 V enabled After resume and After a bus reset

Clock will wake up:

After detecting the presence of V

3.3 V 3.3 V 3.3 V 0 V => 5 V enabled

BUS

Table 11: Operation truth table for back voltage compliance

ISP1582 operation Power supply Bit SOFTCT

in Mode register

Back voltage is not measured in this

CC(I/O)

RPU

BUS

(3.3 V)

3.3 V 3.3 V 3.3 V 5 V enabled

mode Back voltage is not an issue because

3.3 V 3.3 V 3.3 V 0 V disabled

pull-up on DP will not be present when V

is not present

BUS

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+ 46 hidden pages

Philips ISP1582 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features

3. Applications

4. Abbreviations

5. Ordering information

6. Block diagram

7. Pinning information

7.1 Pinning

7.2 Pin description

8. Functional description

8.1 DMA interface, DMA handler and DMA registers

8.2 Hi-Speed USB transceiver

8.3 MMU and integrated RAM

8.4 Microcontroller interface and microcontroller handler

8.5 OTG SRP module

8.6 Philips high-speed transceiver

8.7 Philips Serial Interface Engine (SIE)

8.8 SoftConnect

8.9 System controller

8.10 Output pins status

8.11 Interrupt

8.13 Power-on reset

8.14 Power supply