Philips ISP1562 User Manual

ISP1562

Hi-Speed Universal Serial Bus PCI Host Controller

Rev. 01 — 14 July 2005 Product data sheet

1. General description

The ISP1562 is a Peripheral Component Interconnect (PCI)-based, single-chip Universal Serial Bus (USB) Host Controller. It integrates two Original USB Open Host Controller Interface (OHCI) cores, one Hi-Speed USB Enhanced Host Controller Interface (EHCI) core, and two transceivers that are compliant with Hi-Speed USB and Original USB. The functional parts of the ISP1562 are fully compliant with

Rev. 2.0,Open Host Controller Interface Speciﬁcation for USB Rev. 1.0a,Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus Rev. 1.0,PCI Local Bus Speciﬁcation Rev. 2.2

The integrated high performance USB transceivers allow the ISP1562 to handle all Hi-Speed USB transfer speed modes: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The ISP1562 provides two downstream ports, allowing simultaneous connection of USB devices at different speeds.

Universal Serial Bus Speciﬁcation

, and

PCI Bus Power Management Interface Speciﬁcation Rev. 1.1

2. Features

The ISP1562 is fully compatible with various operating system drivers, such as Microsoft Windows standard OHCI and EHCI drivers that are present in Windows XP, Windows 2000 and Red Hat Linux.

The ISP1562 directly interfaces to any 32-bit, 33 MHz PCI bus. Its PCI pins can source

3.3 V. The PCI interface fully complies with The ISP1562isideally suited for use in Hi-Speed USB mobile applications and embedded

solutions. The ISP1562 uses a 12 MHz crystal.

■ Complies with

■ Supports data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and

low-speed (1.5 Mbit/s)

■ Two Original USB OHCI cores comply with

Speciﬁcation for USB Rev. 1.0a

■ One Hi-Speed USB EHCI core complies with

Speciﬁcation for Universal Serial Bus Rev. 1.0

■ Supports PCI 32-bit, 33 MHz interface compliant with

Rev. 2.2

standard

■ Compliant with

hosts (EHCI and OHCI), and supports all power states: D0, D1, D2, D3

Universal Serial Bus Speciﬁcation Rev. 2.0

, with support for D3

PCI Bus Power Management Interface Speciﬁcation Rev. 1.1

standby and wake-up modes; all I/O pins are 3.3 V

cold

PCI Local Bus Speciﬁcation Rev. 2.2

Open Host Controller Interface

Enhanced Host Controller Interface

PCI Local Bus Speciﬁcation

and D3

hot

for all

cold

Philips Semiconductors

■ CLKRUN support for mobile applications, such as internal notebook design

■ Conﬁgurable subsystem ID and subsystem Vendor ID through external EEPROM

■ Digital and analog powerseparation forbetter Electro-Magnetic Interference (EMI) and

Electro-Static Discharge (ESD) protection

■ Supports hot Plug and Play and remote wake-up of peripherals

■ Supports individual power switching and individual overcurrent protection for

downstream ports

■ Supports partial dynamic port-routing capability for downstream ports that allows

sharing of the same physical downstream ports between the Original USB Host Controller and the Hi-Speed USB Host Controller

■ Uses 12 MHz crystal oscillator to reduce system cost and EMI emissions

■ Supports dual power supply: PCI V

■ Operates at +3.3 V power supply input

■ Low power consumption

■ Full industrial operating temperature range from −40 °Cto+85°C

■ Full-scan design with high fault coverage (93 % to 95 %) ensures high quality

■ Available in LQFP100 package.

aux(3V3)

and V

ISP1562

USB PCI Host Controller

3. Applications

■ Digital consumer appliances

■ Notebook

■ PCI add-on card

■ PC motherboard

■ Set-Top Box (STB)

■ Web appliances.

4. Ordering information

Table 1: Ordering information

Type number Package

Name Description Version

ISP1562BE LQFP100 plastic low proﬁle quad ﬂat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1

Product data sheet Rev. 01 — 14 July 2005 2 of 98

Product data sheet Rev. 01 — 14 July 2005 3 of 98

xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x

SCL SDA

5. Block diagram

Philips Semiconductors

C/BE#[3:0]

32-bit, 33 MHz PCI bus

I(VREG3V3)

REG1V8

XTAL1

XTAL2

PME#

PCICLK

AD[31:0]

REQ# GNT#

IDSEL

INTA#

FRAME#

DEVSEL#

IRDY#

CLKRUN#

PAR PERR# SERR#

TRDY# STOP#

RST#

CC(I/O)

99 7

10, 12 to 15, 20 to 22, 26 to 31, 33, 34, 50 to 54, 56, 57, 59, 62, 63, 65 to 70

23, 35, 48, 60 9 8 24

4 36 39 37 42 47 44 45 38 41

5 11, 25, 40,

55, 71 16

18, 43, 58

74 75

PCI CORE

PCI MASTER

PCI SLAVE

CONFIGURATION SPACE

CONFIGURATION FUNCTION 0

CONFIGURATION FUNCTION 1

CONFIGURATION FUNCTION 2

CORE RESET_N

POR

VOLTAGE

REGULATOR

CC(I/O)

DETECT

XOSC

PLL

CORE

DDA_AUX

86, 93

OHCI

(FUNCTION 0)

RAM

ORIGINAL

USB ATX

OC1_N

PWE1_N

96 97

GLOBAL CONTROL

(FUNCTION 1)

PORT ROUTER

ATX1

Hi-SPEED

USB ATX

79 83 85

DM1 DP1

ISP1562

OHCI

RAM

ATX2

ORIGINAL

USB ATX

87 88 90 92

OC2_N

PWE2_N

VOLTAGE

REGULATOR

EHCI

(FUNCTION 2)

RAM

Hi-SPEED

USB ATX

DM2 DP2

)

aux

aux(1V8)

77, 98, 100

core

1, 17, 46,

61, 72, 80,

6, 19, 32,

49, 64, 76,

004aaa507

2, 73

82, 84,

89, 91

94, 95

CC(I/O)_AUX

I(VAUX3V3)

AUX1V8

RREF

GNDA

GNDD

USB PCI Host Controller

ISP1562

Fig 1. Block diagram.

Philips Semiconductors

6. Pinning information

6.1 Pinning

CC(I/O)_AUX

99989796959493929190898887

100

DDA_AUX

DP1

GNDA

DM1

8685848382

GNDA

8180797877

ISP1562

USB PCI Host Controller

CC(I/O)_AUX

GNDA XTAL2

AUX1V8 XTAL1

I(VAUX3V3)

PCICLK AD[1]

I(VREG3V3)

REG1V8

C/BE#[3] AD[12]

2 3 4

INTA# GNDA

RST# V

GNDD AD[0]

7 8

GNT# AD[2]

REQ# AD[3]

AD[31] AD[4]

CC(I/O)

AD[30] GNDD

AD[29] AD[6]

AD[28] AD[7]

AD[27]

16 17

GNDA

18 19

GNDD

AD[26] AD[10]

AD[25] V

AD[24] AD[11]

23 24

IDSEL

CC(I/O)

ISP1562BE

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

AUX1V8

CC(I/O)

AD[5]

GNDA C/BE#[0] AD[8] REG1V8 AD[9]

CC(I/O)

AD[13] AD[14]

26272829303132333435363738

AD[23] V

AD[22] PME#

AD[21] V

AD[20] SDA

AD[19] SCL

GNDD GNDD

AD[18] GNDD

AD[17] V

AD[16] DP2

C/BE#[2] GNDA

FRAME# DM2

IRDY# GNDA

TRDY# PWE2_N

4041424344

CC(I/O)

STOP#

DEVSEL# OC2_N

PERR#

REG1V8

CLKRUN#

4546474849

PAR PWE1_N

GNDA GNDA

SERR# RREF

C/BE#[1] OC1_N

GNDD

AD[15] GNDD

004aaa508

Fig 2. Pin conﬁguration.

Product data sheet Rev. 01 — 14 July 2005 4 of 98

Philips Semiconductors

6.2 Pin description

Table 2: Pin description

Symbol

GNDA 1 - analog ground AUX1V8 2 - 1.8 Vauxiliary output voltage;only for voltage conditioning; cannot be

I(VAUX3V3)

INTA# 4 I/O PCI interrupt

RST# 5 I PCI reset; used to bring PCI-speciﬁc registers, sequencers and

GNDD 6 - digital ground PCICLK 7 I PCI system clock (33 MHz)

GNT# 8 I/O PCI grant; indicates to the agent that access to the bus is granted

REQ# 9 I/O PCIrequest; indicates to the arbitrator that the agent wants to use the

AD[31] 10 I/O bit 31 of multiplexed PCI address and data

CC(I/O)

AD[30] 12 I/O bit 30 of multiplexed PCI address and data

AD[29] 13 I/O bit 29 of multiplexed PCI address and data

AD[28] 14 I/O bit 28 of multiplexed PCI address and data

AD[27] 15 I/O bit 27 of multiplexed PCI address and data

I(VREG3V3)

GNDA 17 - analog ground REG1V8 18 - 1.8 V regulator output voltage; only for voltage conditioning; cannot

GNDD 19 - digital ground AD[26] 20 I/O bit 26 of multiplexed PCI address and data

AD[25] 21 I/O bit 25 of multiplexed PCI address and data

AD[24] 22 I/O bit 24 of multiplexed PCI address and data

ISP1562

USB PCI Host Controller

[1]

Pin Type Description

used to supply power to external components; connected to 100 nF and 20 µF capacitors

3 - 3.3 V auxiliary input voltage; add a 100 nF decoupling capacitor

PCI pad; 3.3 V signaling; open-drain

signals to a consistent state

3.3 V input pad; push-pull; CMOS

PCI pad; 3.3 V signaling

bus PCI pad; 3.3 V signaling

PCI pad; 3.3 V signaling

11 - 3.3 V supply voltage; used to power pads; add a 100 nF decoupling

capacitor

PCI pad; 3.3 V signaling

16 - 3.3 V regulator input voltage; add a 100 nF decoupling capacitor

be used to supply power to external components; connected to 100 nF and 20 µF capacitors

PCI pad; 3.3 V signaling

Product data sheet Rev. 01 — 14 July 2005 5 of 98

Philips Semiconductors

ISP1562

USB PCI Host Controller

Table 2: Pin description

CC(I/O)

[1]

Pin Type Description

25 - 3.3 V supply voltage; used to power pads; add a 100 nF decoupling

40 - 3.3 V supply voltage; used to power pads; add a 100 nF decoupling

Symbol

C/BE#[3] 23 I/O byte 3 of multiplexed PCI bus command and byte enable

IDSEL 24 I PCI initialization device select; used as a chip select during

AD[23] 26 I/O bit 23 of multiplexed PCI address and data

AD[22] 27 I/O bit 22 of multiplexed PCI address and data

AD[21] 28 I/O bit 21 of multiplexed PCI address and data

AD[20] 29 I/O bit 20 of multiplexed PCI address and data

AD[19] 30 I/O bit 19 of multiplexed PCI address and data

AD[18] 31 I/O bit 18 of multiplexed PCI address and data

GNDD 32 - digital ground AD[17] 33 I/O bit 17 of multiplexed PCI address and data

AD[16] 34 I/O bit 16 of multiplexed PCI address and data

C/BE#[2] 35 I/O byte 2 of multiplexed PCI bus command and byte enable

FRAME# 36 I/O PCI cycle frame; driven by the master to indicate the beginning and

IRDY# 37 I/O PCI initiator ready; indicates the ability of the initiating agent to

TRDY# 38 I/O PCI target ready; indicates the ability of the target agent to complete

DEVSEL# 39 I/O PCI device select; indicates if any device is selected on the bus

STOP# 41 I/O PCI stop; indicates that the current target is requesting the master to

CLKRUN# 42 I/O PCI CLKRUN signal; pull-down to ground through a 10 kΩ resistor

…continued

PCI pad; 3.3 V signaling

conﬁguration read and write transactions PCI pad; 3.3 V signaling

capacitor

PCI pad; 3.3 V signaling

duration of an access PCI pad; 3.3 V signaling

complete the current data phase of a transaction PCI pad; 3.3 V signaling

the current data phase of a transaction PCI pad; 3.3 V signaling

PCI pad; 3.3 V signaling

capacitor

stop the current transaction PCI pad; 3.3 V signaling

PCI pad; 3.3 V signaling; open-drain

Product data sheet Rev. 01 — 14 July 2005 6 of 98

Philips Semiconductors

ISP1562

USB PCI Host Controller

Table 2: Pin description

CC(I/O)

[1]

Pin Type Description

55 - 3.3 V supply voltage; used to power pads; add a 100 nF decoupling

Symbol

REG1V8 43 - 1.8 V regulator output voltage; only for voltage conditioning; cannot

PERR# 44 I/O PCI parity error; used to report data parity errors during all PCI

SERR# 45 I/O PCI system error; used to report address parity errors and data parity

GNDA 46 - analog ground PAR 47 I/O PCI parity

C/BE#[1] 48 I/O byte 1 of multiplexed PCI bus command and byte enable

GNDD 49 - digital ground AD[15] 50 I/O bit 15 of multiplexed PCI address and data

AD[14] 51 I/O bit 14 of multiplexed PCI address and data

AD[13] 52 I/O bit 13 of multiplexed PCI address and data

AD[12] 53 I/O bit 12 of multiplexed PCI address and data

AD[11] 54 I/O bit 11 of multiplexed PCI address and data

AD[10] 56 I/O bit 10 of multiplexed PCI address and data

AD[9] 57 I/O bit 9 of multiplexed PCI address and data

REG1V8 58 - 1.8 V regulator output voltage; only for voltage conditioning; cannot

AD[8] 59 I/O bit 8 of multiplexed PCI address and data

C/BE#[0] 60 I/O byte 0 of multiplexed PCI bus command and byte enable

GNDA 61 - analog ground AD[7] 62 I/O bit 7 of multiplexed PCI address and data

AD[6] 63 I/O bit 6 of multiplexed PCI address and data

…continued

be used to supply power to external components; add a 100 nF decoupling capacitor

transactions, except a Special Cycle PCI pad; 3.3 V signaling

errors on the Special Cycle command, or any other system error in which the result will be catastrophic

PCI pad; 3.3 V signaling; open-drain

PCI pad; 3.3 V signaling

capacitor

PCI pad; 3.3 V signaling

be used to supply power to external components; add a 100 nF decoupling capacitor

PCI pad; 3.3 V signaling

Product data sheet Rev. 01 — 14 July 2005 7 of 98

Philips Semiconductors

ISP1562

USB PCI Host Controller

Table 2: Pin description

Symbol

GNDD 64 - digital ground AD[5] 65 I/O bit 5 of multiplexed PCI address and data

AD[4] 66 I/O bit 4 of multiplexed PCI address and data

AD[3] 67 I/O bit 3 of multiplexed PCI address and data

AD[2] 68 I/O bit 2 of multiplexed PCI address and data

AD[1] 69 I/O bit 1 of multiplexed PCI address and data

AD[0] 70 I/O bit 0 of multiplexed PCI address and data

GNDA 72 - analog ground AUX1V8 73 - 1.8 V auxiliary output voltage; only forvoltageconditioning; cannot be

XTAL1 74 AI crystal oscillator input; this can also be a 12 MHz clock input XTAL2 75 AO crystal oscillator output (12 MHz); leave open when clock is used GNDD 76 - digital ground V

OC1_N 78 I overcurrent sense input for the USB downstream port 1 (digital)

PWE1_N 79 O power enable for the USB downstream port 1

GNDA 80 - analog ground RREF 81 AI/O analog connection for the external resistor (12 kΩ±1%) GNDA 82 - analog ground DM1 83 AI/O D−; analog connection for the USB downstream port 1; leave this pin

GNDA 84 - analog ground DP1 85 AI/O D+; analog connection forthe USB downstream port 1; leave this pin

V OC2_N 87 I overcurrent sense input for the USB downstream port 2 (digital)

PWE2_N 88 O power enable for the USB downstream port 2

GNDA 89 - analog ground

[1]

CC(I/O)

CC(I/O)_AUX

DDA_AUX

Pin Type Description

71 - 3.3 V supply voltage; used to power pads; add a 100 nF decoupling

77 - 3.3 V auxiliary supply voltage; used to power pads; add a 100 nF

86 - auxiliary analog supply voltage; add a 100 nF decoupling capacitor

…continued

PCI pad; 3.3 V signaling

capacitor

used to supply power to external components; add a 100 nF decoupling capacitor

decoupling capacitor

3.3 V input pad; push-pull; CMOS

3.3 V output pad; 3 ns slew rate control; CMOS; open-drain

open when not in use

3.3 V input pad; push-pull; CMOS

3.3 V output pad; 3 ns slew rate control; CMOS; open-drain

Product data sheet Rev. 01 — 14 July 2005 8 of 98

Philips Semiconductors

ISP1562

USB PCI Host Controller

Table 2: Pin description

Symbol

[1]

Pin Type Description

…continued

DM2 90 AI/O D−; analog connection for the USB downstream port 2; leave this pin

open when not in use GNDA 91 - analog ground DP2 92 AI/O D+; analog connection forthe USB downstream port 2; leave this pin

open when not in use V

DDA_AUX

93 - auxiliary analog supply voltage; add a 100 nF decoupling capacitor GNDD 94 - digital ground GNDD 95 - digital ground SCL 96 I/O I

C-bus clock; pull-up to 3.3 V through a 10 kΩ resistor

[2]

I2C-bus pad; clock signal

SDA 97 I/O I

C-bus data; pull-up to 3.3 V through a 10 kΩ resistor

[2]

I2C-bus pad; data signal

CC(I/O)_AUX

98 - 3.3 V auxiliary supply voltage; used to power pads; add a 100 nF

decoupling capacitor

PME# 99 O PCI Power Management Event; used by a device to request a

change in the device or system power state PCI pad; 3.3 V signaling; open-drain

CC(I/O)_AUX

100 - 3.3 V auxiliary supply voltage; used to power pads; add a 100 nF

decoupling capacitor

[1] Symbol names ending with # represent active LOW signals for PCI pins, for example: NAME#. Symbol

names ending with underscore N represent active LOW signals for USB pins, for example: NAME_N.

[2] Connect to ground if I2C-bus is not used.

Product data sheet Rev. 01 — 14 July 2005 9 of 98

Philips Semiconductors

7. Functional description

7.1 OHCI Host Controller

An OHCI Host Controller per port transfersdata to devices at the Original USB deﬁned bit rate of 12 Mbit/s or 1.5 Mbit/s.

7.2 EHCI Host Controller

The EHCI Host Controller transfers data to a Hi-Speed USB compliant device at the Hi-Speed USB deﬁned bit rate of 480 Mbit/s. When the EHCI Host Controller has the ownership of a port, the OHCI Host Controllers are not allowed to modify the port register. All additional port bit deﬁnitions required for the Enhanced Host Controller are not visible to the OHCI Host Controller.

7.3 Dynamic port-routing logic

The port-routing feature allows sharing of the same physical downstream ports between the Original USB Host Controller and the Hi-Speed USB Host Controller.This requirement of the

Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus Rev. 1.0

provides ports that are multiplexed with the ports of the OHCI.

ISP1562

USB PCI Host Controller

The EHCI is responsible for the port-routing switching mechanism. Two register bits are used for ownership switching. During power-onand system reset, the defaultownership of all downstream ports is the OHCI. The Enhanced Host Controller Driver (HCD) controls the ownership during normal functionality.

7.4 Hi-Speed USB analog transceivers

The Hi-Speed USB analog transceivers directly interface to the USB cables through integrated termination resistors. These transceivers can transmit and receive serial data at all data rates: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s).

7.5 Power management

The ISP1562 provides an advanced power management capability interface that is compliant with controlled and managed by the interaction between drivers and PCI registers.

For a detailed description on power management, see Section 10.

PCI Bus Power Management Interface Speciﬁcation Rev. 1.1

7.6 Phase-Locked Loop (PLL)

A 12 MHz-to-30 MHz and 48 MHz clock multiplier PLL is integrated on-chip. This allows the use of a low-cost 12 MHz crystal, which also minimizes EMI. No external components are required for the PLL to operate.

. Power is

Product data sheet Rev. 01 — 14 July 2005 10 of 98

Philips Semiconductors

7.7 Power-On Reset (POR)

ISP1562

USB PCI Host Controller

Figure 3 shows a possible curve of V

with dips at t2 to t3 and t4 to t5. At t0, POR will

CC(I/O)

start with 1. At t1, the detector passes through the trip level. Another delay will be added before POR drops to 0 to ensure that the length of the generated detector pulse, POR, is large enough to reset asynchronous ﬂip-ﬂops. If the dip is too short (t4 to t5 < 11 µs), POR will not react and will stay LOW.

CC(I/O)

POR(trip)

t0 t1

POR(trip)

is typically 1.2 V.

004aaa664

POR

Fig 3. Power-on reset.

7.8 Power supply

Figure 4 shows the ISP1562 power supply connection.

Product data sheet Rev. 01 — 14 July 2005 11 of 98

Philips Semiconductors

ISP1562

USB PCI Host Controller

ISP1562

40, 55, 71

77, 98, 100

11, 25,

86, 93

I(VREG3V3)

CC(I/O)

I(VAUX3V3)

CC(I/O)_AUX

DDA_AUX

AUX1V8

REG1V8

20 µF

100 nF

PCI 3.3 V

PCI V

aux(3V3)

PCI V

aux(3V3)

PCI V

aux(3V3)

(1)

8. PCI

REG1V8

(1) If V

43, 58

1, 6, 17, 19, 32,

46, 49, 61, 64, 72, 76, 80, 82,

84, 89, 91, 94, 95

GND

is not present on PCI, the pin should be connected to PCI 3.3 V.

aux(3V3)

004aaa665

100 nF

Fig 4. Power supply connection.

8.1 PCI interface

The PCI interface has three functions. The ﬁrst function (#0) and the second function (#1) are for the OHCI Host Controllers, and the third function (#2) is for the EHCI Host Controller. All functions support both master and target accesses, and share the same PCI interrupt signal INTA#. These functions provide memory-mapped, addressable operational registers as required in

Rev. 1.0a Rev. 1.0

and

Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus

Open Host Controller Interface Speciﬁcation for USB

Product data sheet Rev. 01 — 14 July 2005 12 of 98

Philips Semiconductors

Each function has its own conﬁguration space. The PCI enumerator should allocate the memory address space for each of these functions. Power management is implemented in each PCI function and all power states are provided. This allows the system to achieve low power consumption by switching off the functions that are not required.

8.1.1 PCI conﬁguration space

ISP1562

USB PCI Host Controller

PCI Local Bus Speciﬁcation Rev. 2.2

ISP1562 provides its ownPCI conﬁguration registers, which can vary in size. In addition to the basic PCI conﬁguration header registers, these functions implement capability registers to support power management.

The registers of each of these functions are accessed bythe respectivedriver.Section 8.2 provides a detailed description of the various PCI conﬁguration registers.

8.1.2 PCI initiator and target

A PCI initiator initiates PCI transactions to the PCI bus. A PCI target responds to PCI transactions as a slave. In the case of the ISP1562, the two Open Host Controllers and the Enhanced Host Controller function as both initiators or targets of PCI transactions issued by the host CPU.

All USB Host Controllers have their own operational registers that can be accessed by the system driver software. Drivers use these registers to conﬁgure the Host Controller hardware system, issue commands to it, and monitor the status of the current hardware operation. The Host Controller plays the role of a PCI target. All operational registers of the Host Controllers are the PCI transaction targets of the CPU.

Normal USB transfers require the Host Controller to access system memory ﬁelds, which are allocated by USB HCDs and PCI drivers. The Host Controller hardware interacts with the HCD by accessing these buffers. The Host Controller works as an initiator in this case and becomes a PCI master.

requires that each of the three PCI functions of the

8.2 PCI conﬁguration registers

The OHCI USB Host Controllers and the EHCI USB Host Controller contain two sets of software-accessible hardware registers: PCI conﬁguration registers and memory-mapped Host Controller registers.

A set of conﬁguration registers is implemented for each of the three PCI functions of the ISP1562, see Table 3.

Remark: In addition to the normal PCI header, from offset index 00h to 3Fh, implementation-speciﬁc registers are deﬁned to support power management and function-speciﬁc features.

Table 3: PCI conﬁguration space registers of OHCI1, OHCI2 and EHCI

Address Bits 31 to 24 Bits 23 to 16 Bits 15 to 8 Bits 7 to 0 Reset value

Func0 OHCI1 Func1 OHCI2 Func2 EHCI

PCI conﬁguration header registers

00h Device ID[15:0] Vendor ID[15:0] 1561 1131h 1561 1131h 1562 1131h 04h Status[15:0] Command[15:0] 0210 0000h 0210 0000h 0210 0000h

Product data sheet Rev. 01 — 14 July 2005 13 of 98

[1]

Philips Semiconductors

ISP1562

USB PCI Host Controller

Table 3: PCI conﬁguration space registers of OHCI1, OHCI2 and EHCI

Address Bits 31 to 24 Bits 23 to 16 Bits 15 to 8 Bits 7 to 0 Reset value

08h Class Code[23:0] Revision

ID[7:0]

0Ch reserved Header

Type[7:0] 10h Base Address 0[31:0] 0000 0000h 0000 0000h 0000 0000h 14h 18h 1Ch 20h 24h 28h 2Ch Subsystem ID[15:0] Subsystem Vendor ID[15:0] 1561 1131h 1561 1131h 1562 1131h 30h reserved 0000 0000h 0000 0000h 0000 0000h 34h reserved Capabilities

38h reserved 0000 0000h 0000 0000h 0000 0000h 3Ch Max_ Lat[7:0] Min_Gnt[7:0] Interrupt

40h reserved Retry

Enhanced Host Controller-speciﬁc PCI registers

60h PORTWAKECAP[15:0] FLADJ[7:0] SBRN[7:0] - - 0007 2020h

Power management registers

DCh PMC[15:0] Next_Item_Ptr

E0h Data[7:0] PMCSR_BSE

reserved 0000 0000h 0000 0000h 0000 0000h

[7:0]

Latency

Timer[7:0]

Pin[7:0]

Timeout

[7:0]

PMCSR[15:0] 0000 XX00h

CacheLine

Size[7:0]

Pointer[7:0]

Interrupt Line[7:0]

TRDY

Timeout

Cap_ID[7:0] D282 0001h D282 0001h FE82 0001h

…continued

[1]

Func0 OHCI1 Func1 OHCI2 Func2 EHCI

0C03 1011h 0C03 1011h 0C03 2011h

0080 0000h 0080 0000h 0080 0000h

0000 00DCh 0000 00DCh 0000 00DCh

2A01 0100h 2A01 0100h 1002 0100h

0000 8000h 0000 8000h 0000 8000h

[2]

0000 XX00h

[2]

0000 XX00h

[2]

[1] Reset values that are highlighted—for example, 0—indicate read and write accesses; and reset values that are not highlighted—for

example, 0—indicate read-only.

[2] See Section 8.2.3.4.

The HCD does not usually interact with the PCI conﬁguration space. The conﬁguration space is used only by the PCI enumerator to identify the USB Host Controller and assign appropriate system resources by reading the Vendor ID (VID) and the Device ID (DID).

8.2.1 PCI conﬁguration header registers

The Enhanced Host Controller implements the normal PCI header register values, except the values for the memory-mapping base address register, serial bus number and Device ID.

8.2.1.1 Vendor ID register

This read-only register identiﬁes the manufacturer of the device. PCI Special Interest Group (PCI-SIG) assigns valid vendor identiﬁers to ensure the uniqueness of the identiﬁer. The bit description is shown in Table 4.

Product data sheet Rev. 01 — 14 July 2005 14 of 98

Philips Semiconductors

Table 4: VID - Vendor ID register (address 00h) bit description

Legend: * reset value

Bit Symbol Access Value Description 15 to 0 VID[15:0] R 1131h* Vendor ID: This read-only register value is assigned

8.2.1.2 Device ID register

This is a 2 B read-only register that identiﬁes a particular device.The identiﬁer is allocated by Philips Semiconductors. Table 5 shows the bit description of the register.

Table 5: DID - Device ID register (address 02h) bit description

Legend: * reset value

Bit Symbol Access Value Description

15 to 0 DID[15:0] R 156Xh*

[1] X is 1h for OHCI1 and OHCI2; X is 2h for EHCI.

8.2.1.3 Command register

This is a 2 B register that provides coarse control over the ability of a device to generate and respond to PCI cycles. The bit allocation of the Command register is given in Table 6. When logic 0 is written to this register, the device is logically disconnected from the PCI bus for all accesses, except conﬁguration accesses. All devices are required to support this base level of functionality. Individual bits in the Command register may or may not support this base level of functionality.

ISP1562

USB PCI Host Controller

to Philips Semiconductors by PCI-SIG as 1131h.

[1]

Device ID: This register value is deﬁned by Philips Semiconductors to identify the USB Host Controller IC product.

Table 6: Command register (address 04h) bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol SCTRL PER VGAPS MWIE SC BM MS IOS Reset 00000000 Access R R/W R R/W R R/W R/W R/W

[1] The reserved bits should always be written with the reset value.

[1]

FBBE SERRE

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Table 7: Command register (address 04h) bit description

Bit Symbol Description

15 to 10 reserved 9 FBBE Fast Back-to-Back Enable: This bit controls whether a master can do

8 SERRE SERR# Enable: This bit is an enable bit for the SERR# driver. All devices

7 SCTRL Stepping Control: This bit controls whether a device does address and

6 PER Parity Error Response: This bit controls the response of a device to

5 VGAPS VGA Palette Snoop: This bit controls how VGA compatible and graphics

4 MWIE Memory Write and Invalidate Enable: This is an enable bit for using the

3SCSpecial Cycles: Controls the action of a device on Special Cycle

ISP1562

USB PCI Host Controller

fast back-to-back transactions to various devices. The initialization software must set this bit if all targets are fast back-to-back capable.

0 — Fast back-to-back transactions are only allowed to the same agent (value after RST#)

1 — The master is allowed to generate fast back-to-back transactions to different agents.

that have an SERR# pin must implement this bit. Address parity errors are reported only if this bit and the PER bit are logic 1.

0 — Disable the SERR# driver 1 — Enable the SERR# driver.

data stepping. Devicesthat neverdo stepping must clear this bit. Devices that always do stepping must set this bit. Devicesthat can do either,must make this bit read and write, and initialize it to logic 1 after RST#.

parity errors. When the bit is set, the device must take its normal action when a parity error is detected. When the bit is logic 0, the device sets DPE (bit 15 in the Status register) when an error is detected, but does not assert PERR# and continues normal operation. The state of this bit after RST# is logic 0. Devices that check parity must implement this bit. Devices are required to generate parity, even if parity checking is disabled.

devices handle accesses to VGA palette registers. 0 — The device should treat palette write accesses like all other

accesses. 1 — Palette snooping is enabled, that is, the device does not respond to

palette register writes and snoops data. VGA compatible devices should implement this bit.

Memory Write and Invalidate command.

0 — Memory Writes must be used instead. State after RST# is logic 0. 1 — Masters may generate the command.

This bit must be implemented by master devices that can generate the Memory Write and Invalidate command.

operations. 0 — Causes the deviceto ignore all Special Cycle operations. State after

RST# is logic 0. 1 — Allows the device to monitor Special Cycle operations.

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ISP1562

USB PCI Host Controller

Table 7: Command register (address 04h) bit description

Bit Symbol Description

2BMBus Master: Controls the ability of a deviceto act as a master on the PCI

bus. 0 — Disables the device from generating PCI accesses. State after

RST# is logic 0. 1 — Allows the device to behave as a bus master.

1MSMemory Space: Controls the response of a device to Memory Space

accesses.

0 — Disables the device response. State after RST# is logic 0. 1 — Allows the device to respond to memory space accesses.

0 IOS IO Space: Controls the response of a device to I/O space accesses.

0 — Disables the device response. State after RST# is logic 0. 1 — Allows the device to respond to I/O space accesses.

…continued

8.2.1.4 Status register

The Status register is a 2 B read-only register used to record status information on PCI bus-related events. For bit allocation, see Table 8.

Table 8: Status register (address 06h) bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol DPE SSE RMA RTA STA DEVSELT[1:0] MDPE Reset 00000010 Access RRRRRRRR Bit 7 6 5 4 3 2 1 0 Symbol FBBC reserved 66MC CL reserved Reset 00010000 Access RRRRRRRR

Table 9: Status register (address 06h) bit description

Bit Symbol Description

15 DPE Detected Parity Error: This bit must be set by the device whenever it

detects a parity error, even if the parity error handling is disabled.

14 SSE Signaled System Error: This bit must be set whenever the device asserts

SERR#. Devices that never assert SERR# do not need to implement this bit.

13 RMA Received Master Abort: This bit must be set bya master device whenever

its transaction, except for Special Cycle,is terminated with Master-Abort. All master devices must implement this bit.

12 RTA Received Target Abort: This bit must be set by a master device whenever

its transaction is terminated with Target-Abort. All master devices must implement this bit.

11 STA Signaled Target Abort: This bit must be set by a target device whenever it

terminates a transaction with Target-Abort. Devices that never signal Target-Abort do not need to implement this bit.

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ISP1562

USB PCI Host Controller

Table 9: Status register (address 06h) bit description

Bit Symbol Description

10 to 9 DEVSELT

[1:0]

8 MDPE Master Data Parity Error: This bit is implemented by bus masters. It is set

DEVSEL Timing: These bits encode the timing of DEVSEL#. There are three allowable timing to assert DEVSEL#:

00b — Fast 01b — Medium 10b — Slow 11b — Reserved.

These bits are read-only and must indicate the slowest time that a device asserts DEVSEL# for any bus command, except Conﬁguration Read and Conﬁguration Write.

when the following three conditions are met:

…continued

• The bus agent asserted PERR# itself, on a read; or observed PERR#

asserted, on a write.

• The agent setting the bit acted as the bus master for the operation in

which error occurred.

• PER (bit 6 in the Command register) is set.

7 FBBC Fast Back-to-Back Capable: This read-only bit indicates whether the

target is capable of accepting fast back-to-back transactions when the transactions are not to the same agent. This bit can be set to logic 1, if the

device can accept these transactions; and must be set to logic 0 otherwise. 6 reserved 5 66MC 66 MHz Capable: This read-only bit indicates whether this device is

capable of running at 66 MHz.

0 — 33 MHz

1 — 66 MHz.

4CL Capabilities List: This read-only bit indicates whether this device

implements the pointer for a new capabilities linked list at offset 34h.

0 — No new capabilities linked list is available

1 — The value read at offset 34h is a pointer in conﬁguration space to a

linked list of new capabilities. 3 to 0 reserved -

8.2.1.5 Revision ID register

This 1 B read-only register indicates a device-speciﬁc revision identiﬁer. The value is chosen by the vendor. This ﬁeld is a vendor-deﬁned extension of the Device ID. The Revision ID register bit description is given in Table 10.

Table 10: REVID - Revision ID register (address 08h) bit description

Legend: * reset value

Bit Symbol Access Value Description

7 to 0 REVID[7:0] R 11h* Revision ID: This byte speciﬁes the design revision

number of functions.

8.2.1.6 Class Code register

Class Code is a 24-bit read-only register used to identify the generic function of the device, and in some cases, a speciﬁc register-level programming interface. Table 11 shows the bit allocation of the register.

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ISP1562

USB PCI Host Controller

The Class Code register is divided into three byte-size ﬁelds. The upper byte is a base class code that broadly classiﬁes the type of function the device performs. The middle byte is a sub-class code that identiﬁes more speciﬁcally the function of the device. The lower byte identiﬁes a speciﬁc register-level programming interface, if any, so that device-independent software can interact with the device.

Table 11: Class Code register (address 09h) bit allocation

Bit 23 22 21 20 19 18 17 16 Symbol BCC[7:0] Reset 0Ch Access RRRRRRRR Bit 15 14 13 12 11 10 9 8 Symbol SCC[7:0] Reset 03h Access RRRRRRRR Bit 7 6 5 4 3 2 1 0 Symbol RLPI[7:0] Reset X0h Access RRRRRRRR

[1] X is 1h for OHCI1 and OHCI2; X is 2h for EHCI.

[1]

Table 12: Class Code register (address 09h) bit description

Bit Symbol Description

23 to 16 BCC[7:0] Base Class Code: 0Ch is the base class code assigned to this byte. It

15 to 8 SCC[7:0] Sub-Class Code: 03h is the sub-class code assigned to this byte. It

7 to 0 RLPI[7:0] Register-Level Programming Interface: 10h is the programming

8.2.1.7 CacheLine Size register

The CacheLine Size register is a read and write single-byte register that speciﬁes the system CacheLine size in units of DWords. This register must be implemented by master devices that can generate the Memory Write and Invalidate command. The value in this register is also used by master devices to determine whether to use Read, Read Line or Read Multiple command to access the memory.

Slave devices that want to allow memory bursting using a CacheLine-wrap addressing mode must implement this register to know when a burst sequence wraps to the beginning of the CacheLine.

This ﬁeld must be initialized to logic 0 on activation of RST#. Table 13 shows the bit description of the CacheLine Size register.

implies a serial bus controller.

implies the USB Host Controller.

interface code assigned to OHCI, which is USB 1.1 speciﬁcation compliant. 20h is the programming interface code assigned to EHCI, which is USB 2.0 speciﬁcation compliant.

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Table 13: CLS - CacheLine Size register (address 0Ch) bit description

Legend: * reset value

Bit Symbol Access Value Description 7 to 0 CLS[7:0] R/W 00h* CacheLine Size: This byte identiﬁes the system

8.2.1.8 Latency Timer register

This register speciﬁes—in units of PCI bus clocks—the value of the Latency Timer for the PCI bus master. Table 14 shows the bit description of the Latency Timer register.

Table 14: LT - Latency Timer register (address 0Dh) bit description

Legend: * reset value

Bit Symbol Access Value Description 7 to 0 LT[7:0] R/W 00h* Latency Timer: This byte identiﬁes the latency timer.

8.2.1.9 Header Type register

The Header Type register identiﬁes the layout of the second part of the predeﬁned header, beginning at byte 10h in conﬁguration space. It also identiﬁes whether the device contains multiple functions. For bit allocation, see Table 15.

ISP1562

USB PCI Host Controller

CacheLine size.

Table 15: Header Type register (address 0Eh) bit allocation

Bit 7 6 5 4 3 2 1 0 Symbol MFD HT[6:0] Reset 10000000 Access RRRRRRRR

Table 16: Header Type register (address 0Eh) bit description

Bit Symbol Description 7 MFD Multi-Function Device: This bit identiﬁes a multifunction device.

0 — The device has single function. 1 — The device has multiple functions.

6 to 0 HT[6:0] Header Type: These bits identify the layout of the part of the

predeﬁned header, beginning at byte 10h in conﬁguration space.

8.2.1.10 Base Address register 0

Power-up softwaremust build a consistent address map beforebooting the machine to an operating system. This means it must determine how much memory is in the system, and how much address space the I/O controllers in the system require. After determining this information, power-up software can map the I/O controllers into reasonable locations and proceed with system boot. To do this mapping in a device-independent manner, the base registers for this mapping are placed in the predeﬁned header portion of conﬁguration space.

Bit 0 in all Base Address registers is read-only and used to determine whether the register maps into memory or I/O space. Base Address registers that map to memory space must return logic 0 in bit 0. Base Address registers that map to I/O space must return logic 1 in bit 0.

The bit description of the BAR 0 register is given in Table 17.

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Table 17: BAR 0 - Base Address register 0 (address 10h) bit description

Legend: * reset value

Bit Symbol Access Value Description

31 to 0 BAR 0[31:0] R/W 0000

8.2.1.11 Subsystem Vendor ID register

The Subsystem Vendor ID register is used to uniquely identify the expansion board or subsystem where the PCI deviceresides. This register allows expansionboard vendorsto distinguish their boards, even though the boards may have the same Vendor ID and Device ID.

Subsystem Vendor IDs are assigned by PCI-SIG to maintain uniqueness. The bit description of the Subsystem Vendor ID register is given in Table 18.

Table 18: SVID - Subsystem Vendor ID register (address 2Ch) bit description

Legend: * reset value

Bit Symbol Access Value Description

15 to 0 SVID[15:0] R 1131h* Subsystem Vendor ID: 1131h is the subsystem

0000h*

ISP1562

USB PCI Host Controller

Base Address to Memory-Mapped Host Controller Register Space: The memory size required by OHCI

and EHCI are 4 kB and 256 B, respectively. Therefore, BAR 0[31:12] is assigned to the two OHCI ports, and BAR 0[31:8] is assigned to the EHCI port.

Vendor ID assigned to Philips Semiconductors.

8.2.1.12 Subsystem ID register

Subsystem ID values are vendorspeciﬁc. The bit description of the Subsystem ID register is given in Table 19.

Table 19: SID - Subsystem ID register (address 2Eh) bit description

Legend: * reset value

Bit Symbol Access Value Description

15 to 0 SID[15:0] R 156Xh*

[1] X is 1h for OHCI1 and OHCI2; X is 2h for EHCI.

8.2.1.13 Capabilities Pointer register

This register is used to point to a linked list of new capabilities implemented by the device. This register is only valid if CL (bit 4 in the Status register) is set. If implemented, bit 1 and bit 0 are reserved and should be set to 00b. Software should mask these bits off before using this register as a pointer in conﬁguration space to the ﬁrst entry of a linked list of new capabilities. The bit description of the register is given in Table 20.

Table 20: CP - Capabilities Pointer register (address 34h) bit description

Legend: * reset value

Bit Symbol Access Value Description

7 to 0 CP[7:0] R DCh* Capabilities Pointer: EHCI efﬁciently manages power

[1]

Subsystem ID: For the ISP1562, Philips Semiconductors has deﬁned OHCI functions as 1561h, and the EHCI function as 1562h.

using this register. This Power Management register is allocated at offset DCh. Only one Host Controller is needed to manage power in the ISP1562.

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8.2.1.14 Interrupt Line register

This is a 1 B register used to communicate interrupt line routing information. This register must be implemented by any device or device function that uses an interrupt pin. The interrupt allocation is done by the BIOS. The POST software needs to write the routing information to this register because it initializes and conﬁgures the system.

The value in this register speciﬁes which input of the system interrupt controller(s) the interrupt pin of the device is connected. This valueis used by device drivers and operating systems to determine priority and vector information. Values in this register are system architecture speciﬁc. The bit description of the register is given in Table 21.

Table 21: IL - Interrupt Line register (address 3Ch) bit description

Legend: * reset value

Bit Symbol Access Value Description 7 to 0 IL[7:0] R/W 00h* Interrupt Line: Indicates which IRQ is used to report

8.2.1.15 Interrupt Pin register

This 1 B register is use to specify which interrupt pin the device or device function uses.

ISP1562

USB PCI Host Controller

interrupt from the ISP1562.

A value of 1h corresponds to INTA#,2h corresponds to INTB#, 3h corresponds to INTC#, and 4h corresponds to INTD#. Devices or functions that do not use interrupt pin must set this register to logic 0. The bit description is given in Table 22.

Table 22: IP - Interrupt Pin register (address 3Dh) bit description

Legend: * reset value

Bit Symbol Access Value Description 7 to 0 IP[7:0] R 01h* Interrupt Pin: INTA# is the default interrupt pin used

8.2.1.16 Min_Gnt and Max_Lat registers

The Minimum Grant (Min_Gnt) and Maximum Latency (Max_Lat) registers are used to specify the desired settings of the device for latency timer values. For both registers, the value speciﬁes a period of time in units of 250 ns. Logic 0 indicates that the device has no major requirements for setting latency timers.

The Min_Gnt register bit description is given in Table 23.

Table 23: Min_Gnt - Minimum Grant register (address 3Eh) bit description

Legend: * reset value

Bit Symbol Access Value Description

7 to 0 MIN_GNT

[7:0]

[1] X is 1h for OHCI1 and OHCI2; X is 2h for EHCI.

R 0Xh*

by the ISP1562.

[1]

Min_Gnt: It is used to specify how long a burst period the device needs, assuming a clock rate of 33MHz.

The Max_Lat register bit description is given in Table 24.

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Table 24: Max_Lat - Maximum Latency register (address 3Fh) bit description

Legend: * reset value

Bit Symbol Access Value Description

7 to 0 MAX_LAT

[1] XX is 2Ah for OHCI1 and OHCI2; XX is 10h for EHCI.

8.2.1.17 TRDY Timeout register

This is a read and write register at address 40h. The default and recommended value is 00h—TRDY timeout disabled. This value can, however, be modiﬁed. It is an implementation-speciﬁc register, and not a standard PCI conﬁguration register.

The TRDY timer is 13 bits—the lower 5 bits are ﬁxed as logic 0, and the upper 8 bits are determined by the TRDY Timeout register value. The timeout is calculated by multiplying the 13-bit timer with the PCI CLK cycle time.

This register determines the maximum TRDY delay without asserting the UE (Unrecoverable Error) bit. If TRDY is longer than the delay determined by this register value, then the UE bit will be set.

[7:0]

R XXh*

ISP1562

USB PCI Host Controller

[1]

Max_Lat: It is used to specify how often the device needs to gain access to the PCI bus.

8.2.1.18 Retry Timeout register

The defaultvalue of this read and write register is 80h, and is located at address 41h. This value can, however, be modiﬁed. Programming this register as 00h means that retry timeout is disabled. This is an implementation-speciﬁc register, and not a standard PCI conﬁguration register.

The timeout is determined by multiplying the register value with the PCI CLK cycle time. This register determines the maximumnumber of PCI retires beforethe UEbit is set. If the number of retries is longer than the delay determined by this register value, then the UE bit will be set.

8.2.2 Enhanced Host Controller-speciﬁc PCI registers

In addition to the PCI conﬁguration header registers, EHCI needs some additional PCI conﬁguration space registers to indicate the serial bus release number, downstream port wake-up event capability, and adjust the USB bus frame length for Start-of-Frame (SOF). The EHCI-speciﬁc PCI registers are given in Table 25.

Table 25: EHCI-speciﬁc PCI registers

Offset Register

60h Serial Bus Release Number (SBRN) 61h Frame Length Adjustment (FLADJ) 62h to 63h Port Wake Capability (PORTWAKECAP)

8.2.2.1 SBRN register

The Serial Bus Release Number (SBRN) register is a 1 B register, and the bit description is given in Table 26. This register contains the release number of the USB speciﬁcation with which this USB Host Controller module is compliant.

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ISP1562

USB PCI Host Controller

Table 26: SBRN - Serial Bus Release Number register (address 60h) bit description

Legend: * reset value

Bit Symbol Access Value Description

7 to 0 SBRN[7:0] R 20h* Serial Bus Speciﬁcation Release Number: This

8.2.2.2 FLADJ register

This feature is used to adjust any offset from the clocksource that generates the clockthat drives the SOF counter. When a new value is written to these six bits, the length of the frame is adjusted. The bit allocation of the Frame Length Adjustment (FLADJ) register is given in Table 27.

Table 27: FLADJ - Frame Length Adjustment register (address 61h) bit allocation

Bit 7 6 5 4 3 2 1 0 Symbol reserved Reset 00100000 Access R/W R/W R/W R/W R/W R/W R/W R/W

[1]

FLADJ[5:0]

[1] The reserved bits should always be written with the reset value.

Table 28: FLADJ - Frame Length Adjustment register (address 61h) bit description

Bit Symbol Description

7 to 6 reserved 5 to 0 FLADJ[5:0] Frame Length Timing Value:Eachdecimal value change to this register

corresponds to 16 high-speed bit times. The SOF cycle time—number of SOF counter clock periods to generate a SOF micro frame length—is equal to 59488 + value in this ﬁeld. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000.

FLADJ value SOF cycle time

(480 MHz)

0 (00h) 59488 1 (01h) 59504 2 (02h) 59520

:: 31 (1Fh) 59984 32 (20h) 60000

62 (3Eh) 60480

63 (3Fh) 60496

8.2.2.3 PORTWAKECAP register

Port Wake Capability (PORTWAKECAP) is a 2 B register used to establish a policy about which ports are for wake events; see Table 29. Bit positions 15 to 1 in the mask correspond to a physical port implemented on the current EHCI controller. Logic 1 in a bit position indicates that a device connected below the port can be enabled as a wake-up device and the port may be enabled for disconnect or connect, or overcurrent events as wake-up events. This is an information only mask register. The bits in this register do not

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affect the actual operation of the EHCI Host Controller. The system-speciﬁc policy can be established by BIOS initializing this register to a system-speciﬁc value. The system software uses the information in this register when enabling devices and ports for remote wake-up.

Table 29: PORTWAKECAP - Port Wake Capability register (address 62h) bit description

Legend: * reset value

Bit Symbol Access Value Description

15 to 0 PORTWAKECAP

8.2.3 Power management registers

Table 30: Power Management registers

Offset Register

Value read from address 34h+ 0h Capability Identiﬁer (Cap_ID) Value read from address 34h+ 1h Next Item Pointer (Next_Item_Ptr) Value read from address 34h+ 2h Power Management Capabilities (PMC) Value read from address 34h+ 4h Power Management Control/Status (PMCSR) Value read from address 34h+ 6h Power Management Control/Status PCI-to-PCI Bridge

Value read from address 34h+ 7h Data

[15:0]

ISP1562

USB PCI Host Controller

R/W 0007h* Port Wake-Up Capability Mask: EHCI

does not implement this feature.

Support Extensions (PMCSR_BSE)

8.2.3.1 Cap_ID register

The Capability Identiﬁer (Cap_ID) register when read by the system software as 01h indicates that the data structure currently being pointed to is the PCI Power Management data structure. Each function of a PCI device may have only one item in its capability list with Cap_ID set to 01h. The bit description of the register is given in Table 31.

Table 31: Cap_ID - Capability Identiﬁer register bit description

Address: Value read from address 34h+ 0h Legend: * reset value

Bit Symbol Access Value Description 7 to 0 CAP_ID[7:0] R 01h* ID: This ﬁeld when 01h identiﬁes thelinked list item as

8.2.3.2 Next_Item_Ptr register

The Next Item Pointer (Next_Item_Ptr) register describes the location of the next item in the function’s capability list. The value given is an offset into the function’s PCI conﬁguration space. If the function does not implement any other capabilities deﬁned by the PCI-SIG for inclusion in the capabilities list, or if power management is the last item in the list, then this register must be set to 00h. See Table 32.

being PCI Power Management registers.

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USB PCI Host Controller

Table 32: Next_Item_Ptr - Next Item Pointer register bit description

Address: Value read from address 34h+ 1h Legend: * reset value

Bit Symbol Access Value Description

7 to 0 NEXT_ITEM_

PTR[7:0]

R 00h* Next Item Pointer: This ﬁeld provides an offset into

the function’s PCI conﬁguration space, pointing to the location of thenext item in the function’s capability list. If there are no additional items in the capabilities list, this register is set to 00h.

8.2.3.3 PMC register

The Power Management Capabilities (PMC) register is a 2 B register, and the bit allocation is given in Table 33. This register provides information on the capabilities of the function related to power management.

Table 33: PMC - Power Management Capabilities register bit allocation

Address: Value read from address 34h+ 2h

Bit 15 14 13 12 11 10 9 8 Symbol PME_S[4:0] D2_S D1_S AUX_C Reset 11X Access RRRRRRRR Bit 7 6 5 4 3 2 1 0 Symbol AUX_C[1:0] DSI reserved PMI VER[2:0] Reset 10000010 Access RRRRRRRR

[1]

[1] X is 0 for OHCI1 and OHCI2; X is 1 for EHCI.

Table 34: PMC - Power Management Capabilities register bit description

Address: Value read from address 34h+ 2h

Bit Symbol Description

15 to 11 PME_S

[4:0]

10 D2_S D2_Support: If this bit is logic 1, this function supports the D2 Power

9 D1_S D1_Support: If this bit is logic 1, this function supports the D1 Power

PME_Support: These bits indicate the power states in which the function may assert PME#. Logic 0 for any bit indicates that the function is not capable of asserting the PME# signal while in that power state.

PME_S[0] — PME# can be asserted from D0 PME_S[1] — PME# can be asserted from D1 PME_S[2] — PME# can be asserted from D2 PME_S[3] — PME# can be asserted from D3 PME_S[4] — PME# can be asserted from D3

Management State. Functions that do not support D2 must always return logic 0 for this bit.

Management State. Functions that do not support D1 must always return logic 0 for this bit.

hot cold

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USB PCI Host Controller

Table 34: PMC - Power Management Capabilities register bit description

…continued

Address: Value read from address 34h+ 2h

Bit Symbol Description

8 to 6 AUX_C

[2:0]

Aux_Current: This three-bit ﬁeld reports the V requirements for the PCI function.

If the Data register is implemented by this function:

aux(3V3)

auxiliary current

• A read from this ﬁeld needs to return a value of 000b.

• The Data register takes precedence over this ﬁeld for V

requirement reporting.

If the PME# generation from D3 (PMC[15] = 0), this ﬁeld must return a value of 000b when read.

For functions that support PME# from D3 register,the bit assignments corresponding to the maximum current required for V

111b — 375 mA 110b — 320 mA 101b — 270 mA 100b — 220 mA 011b — 160 mA 010b — 100 mA 001b — 55 mA 000b — 0 (self powered).

5 DSI Device Speciﬁc Initialization: This bit indicates whether special

initialization of this function is required, beyond the standard PCI conﬁguration header, before the generic class device driver is able to use it.

This bit is not used by some operating systems. For example, Microsoft Windows and Windows NT do not use this bit to determine whether to use D3. Instead, it is determined using the capabilities of the driver.

Logic 1 indicates that the function requires a device-speciﬁc initialization

sequence, following transition to D0 un-initialized state. 4 reserved 3 PMI PME Clock:

0 — Indicates that no PCI clock is required for the function to generate

PME#.

1 — Indicates that the function relies on the presence of the PCI clock for the

PME# operation.

Functions that do not support the PME# generation in any state must return

logic 0 for this ﬁeld. 2 to 0 VER[2:0] Version: A value of 010b indicates that this function complies with

aux(3V3)

are:

Power Management Interface Speciﬁcation Rev. 1.1

is not supported by the function

cold

and do not implement the Data

cold

aux(3V3)

current

PCI Bus

8.2.3.4 PMCSR register

The Power Management Control/Status (PMCSR) register is a 2 B register used to manage the power management state of the PCI function, as well as to allow and monitor Power Management Events (PMEs). The bit allocation of the register is given in Table 35.

Product data sheet Rev. 01 — 14 July 2005 27 of 98

Philips Semiconductors

ISP1562

USB PCI Host Controller

Table 35: PMCSR - Power Management Control/Status register bit allocation

Address: Value read from address 34h+ 4h

Bit 15 14 13 12 11 10 9 8 Symbol PMES DS[1:0] D_S[3:0] PMEE Reset X

[1]

000000X

Access R/W R R R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol reserved

[2]

PS[1:0]

Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

[1]

[1] Sticky bit, if the function supports PME# from D3

function does not support PME# from D3

[2] The reserved bits should always be written with the reset value.

cold

, then X is indeterminate at the time of initial operating system boot; X is 0 if the

cold

Table 36: PMCSR - Power Management Control/Status register bit description

Address: Value read from address 34h+ 4h

Bit Symbol Description

15 PMES PME Status: This bit is set when the function normally asserts the PME#

signal independent of the state of the PMEE bit. Writing logic 1 to this bit

clears it and causes the function to stop asserting PME#, if enabled. Writing

logic 0 has no effect. This bit defaults to logic 0, if the function does not

support the PME# generation from D3

generation from D3

the operating system each time the operating system is initially loaded. 14 to 13 DS[1:0] Data Scale: This two-bit read-only ﬁeld indicates the scaling factor when

interpreting the valueof the Data register.The value and meaning of this ﬁeld

vary, depending on which data value is selected by the D_S ﬁeld. This ﬁeld is

a required component of the Data register (offset 7) and must be

implemented, if the Data register is implemented. If the Data register is not

implemented, this ﬁeld must return 00b when PMCSR is read. 12 to 9 D_S

[3:0]

Data_Select: This four-bit ﬁeld selects the data that is reported through the

Data register and the D_S ﬁeld. This ﬁeld is a required component of the

Data register (offset 7) and must be implemented, if the Data register is

implemented. If the Data register is not implemented, this ﬁeld must return

00b when PMCSR is read.

. If the function supports the PME#

, then this bit is sticky and mustbe explicitly cleared by

cold

Product data sheet Rev. 01 — 14 July 2005 28 of 98

Philips Semiconductors

ISP1562

USB PCI Host Controller

Table 36: PMCSR - Power Management Control/Status register bit description

Address: Value read from address 34h+ 4h

Bit Symbol Description

8 PMEE PME Enabled: Logic 1 allows the function to assert PME#. When it is

logic 0, PME# assertion is disabled. This bit defaultsto logic 0, if the function

does not support the PME# generation from D3

PME# from D3

operating system each time the operating system is initially loaded. 7 to 2 reserved 1 to 0 PS[1:0] Power State: This two-bit ﬁeld is used to determine the current power state

of the EHCI function and to set the function into a new power state. The

deﬁnition of the ﬁeld values is given as:

00b — D0

01b — D1

10b — D2

11b — D3

If the software attempts to write an unsupported, optional state to this ﬁeld,

the write operation must complete normally on the bus; however, the data is

discarded and no status change occurs.

8.2.3.5 PMCSR_BSE register

The PMCSR PCI-to-PCI Bridge Support Extensions(PMCSR_BSE) register supports PCI bridge-speciﬁc functionality and is required for all PCI-to-PCI bridges. The bit allocation of this register is given in Table 37.

hot

…continued

. If the function supports

, then this bit is sticky and must be explicitly cleared by the

cold

Table 37: PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit allocation

Address: Value read from address 34h+ 6h

Bit 7 6 5 4 3 2 1 0 Symbol BPCC_EN B2_B3# reserved Reset 00000000 Access RRRRRRRR

Product data sheet Rev. 01 — 14 July 2005 29 of 98

Philips Semiconductors

Table 38: PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit

Address: Value read from address 34h+ 6h

Bit Symbol Description

7 BPCC_EN Bus Power/Clock Control Enable:

6 B2_B3#

5 to 0 reserved -

description

ISP1562

USB PCI Host Controller

1 — Indicates that the bus power or clock control mechanism as deﬁned in

Table 39 is enabled

0 — Indicates that the bus or power control policies as deﬁned in are disabled.

When the Bus Power or Clock Control mechanism is disabled, the bridge’s PMCSR Power State (PS) ﬁeld cannot be used by the system software to control the power or clock of the bridge’s secondary bus.

B2/B3 support for D3

to occur as a direct result of programming the function to D3 1 — Indicates that when the bridge function is programmed to D3

secondary bus’s PCI clock will be stopped (B2). 0 — Indicates that when the bridge function is programmed to D3

secondary bus will have its power removed (B3). This bit is only meaningful if bit 7 (BPCC_EN) is logic 1.

: The state of this bit determines the action that is

hot

Table 39

hot

, its

Table 39: PCI bus power and clock control

Originatingdevice’s bridge PM state

D0 B0 none D1 B1 none D2 B2 clock stopped on secondary bus D3

hot

cold

8.2.3.6 Data register

The Data register is an optional, 1 B register that provides a mechanism for the function to report state dependent operating data, such as power consumed or heat dissipated.

Table 40 shows the bit description of the register.

Table 40: Data register bit description

Address: Value read from address 34h+ 7h Legend: * reset value

Bit Symbol Access Value Description 7 to 0 DATA[7:0] R 00h* DA TA: This register is used to report the state dependent

Secondary bus PM state

B2, B3 clock stopped and PCI VCC removed from secondary

B3 none

Resultant actions by bridge (either direct or indirect)

bus (B3 only); for deﬁnition of B2_B3#, see

data requested by the D_S ﬁeld of the PMCSR register. The value of this register is scaled by the value reported by the DS ﬁeld of the PMCSR register.

Table 38.

Product data sheet Rev. 01 — 14 July 2005 30 of 98

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