Philips ISP1501 User Guide

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ISP1501

Hi-Speed Universal Serial Bus peripheral transceiver

Rev. 02 — 21 November 2002 Product data

1. General description

The ISP1501 is a full-function transceiver designed to provide a Hi-Speed Universal
Serial Bus (USB) analog front-end toApplication-Specific Integrated Circuits (ASICs)
and Field Programmable Gate Arrays (FPGAs) with a built-in USB Serial Interface
Engine (SIE). A Hi-Speed USB transceiver is integrated to implement USB
connectivity for high-speed peripherals. In addition, an Original USB transceiver
provides backward compatibility with full-speed USB systems. A minimum number of
external components is needed.

2. Features

■ Complies with

■ Legacy compliant Original USB full-speed transceiver interface

■ Bus-powered capability with suspend mode

■ Integrated parallel-to-serial converter (transmit) and serial-to-parallel converter

(receive) for Hi-Speed USB data

■ Hi-Speed USB data recovery upon receiving

■ Hi-Speed USB data synchronization upon transmitting

■ Integrated bit stuffing and de-stuffing for Hi-Speed USB data

■ Non-Return-to-Zero Inverted (NRZI) encoding and decoding for Hi-Speed

USB data

■ Integrated Phase Locked Loop (PLL) oscillator using 12 MHz crystal

■ Internal power-on reset

■ Separate 3.3 V supplies for analog transceiver and digital I/Os minimizes

crosstalk

■ 3.3 V or 5 V tolerant digital input interface

■ 16-bit bi-directional data bus allows FPGA verification, greatly reducing ASIC

implementation risk

■ Full industrial operating temperature range from −40 to +85 °C

■ 6 kV in-circuit ESD protection; compliant with

■ Available in LQFP48 package.

Universal Serial Bus Specification Rev. 2.0

IEC 61000-4-2

(level 3)

Philips Semiconductors

Hi-Speed USB peripheral transceiver

ISP1501

3. Applications

■ Scanner

■ Digital still camera

■ Printer, e.g.

◆ Color printer

◆ Multi-functional printer

■ External storage device, e.g.

◆ Portable hard disk

◆ Zip® drive

◆ Jaz® drive

◆ Magneto-optical (MO) drive

◆ Optical drive (CD-ROM, CD-RW, DVD).

4. Ordering information

Table 1: Ordering information

Type number Package

Name Description Version

ISP1501BE LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

9397 750 10025

Product data Rev. 02 — 21 November 2002 2 of 40

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5. Block diagram

ISP1501

Hi-Speed USB peripheral transceiver

CLKOUT48
CLKOUT30

MODE0, MODE1

RESET

SUSPEND

TX_VALID/OE

TX_READY

TX_BS_EN/FSE0

TX_LAST_BYTE

DDIR

DATA15 to DATA0

RX_VALID/VP

RX_INACTIVE/VM

RX_BS_ERROR/RCV

RX_LAST_BYTE

TEST_J_K/VO

V

to V

CCA1
V

DGND1, DGND2

AGND1 to AGND3

CCD1

, V

CCA3
CCD2

2

16

3
2
2
3

13
15
11, 12
3
1
2

43
44
42
20

38 to 31,
28 to 21

48
47
46
39

45

5, 8, 16
29, 40
30, 41
4, 10, 19

SYSTEM LOGIC

NZRI + BS

ENCODER

NZRI + BS

DECODER

POWER

SUPPLY

ISP1501

HIGH-SPEED

TRANSCEIVER

FULL-SPEED

TRANSCEIVER

PLL

OSCILLATOR

9

RPU

7

DP

6

DM

18

XTAL1

17

XTAL2

MGT059

Fig 1. Block diagram.

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Product data Rev. 02 — 21 November 2002 3 of 40

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6. Pinning information

6.1 Pinning

dth

ISP1501

Hi-Speed USB peripheral transceiver

RX_VALID/VP

RX_INACTIVE/VM

48

47

RESET

V

CCA1

DM

DP

V

CCA2

RPU

1
2
3
4
5
6
7
8

9
10
11
12

13

14

RREF

CLKOUT48

SUSPEND

TX_VALID/OE

AGND1

AGND2
MODE0
MODE1

Fig 2. Pin configuration LQFP48.

RX_BS_ERROR/RCV

TEST_J_K/VO

46

45

ISP1501BE

15

16

CCA3

V

CLKOUT30

TX_BS_EN/FSE0
44

17

XTAL2

TX_READY
43

18

XTAL1

CCD2

DGND2

V

41

20

DDIR

40

21

DATA0

RX_LAST_BYTE
39

22

DATA1

TX_LAST_BYTE
42

19

AGND3

DATA15

DATA14

38

24 37

23

DATA2

DATA3

36
35
34
33
32
31
30
29
28
27
26
25

MGT060

DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
DGND1
V

CCD1

DATA7
DATA6
DATA5
DATA4

6.2 Pin description

Table 2: Pin description

CCA1

[1]

Pin Type Description

2 I pin function depends on operating mode (see Table 3):

State = 0, 1 — output enable for FS transceiver
State = 2, 3 — transmission valid flag for HS transceiver

[2]

[2]

5 - analog supply voltage 1 (3.3 V)

resistor

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

Symbol

SUSPEND 1 I enables power saving mode for USB suspend state
TX_VALID/

OE

RESET 3 I reset input
AGND1 4 - analog ground 1 supply
V
DM 6 AI/O USB D− connection (analog) with integrated 45 Ω series

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ISP1501

Hi-Speed USB peripheral transceiver

Table 2: Pin description

Symbol

[1]

Pin Type Description

…continued

DP 7 AI/O USB D+ connection (analog) with integrated 45 Ω series

resistor

V

CCA2

8 - analog supply voltage 2 (3.3 V)

RPU 9 AI connection for external pull-up resistor (1.5 kΩ±5%) on

USB D+; switched on via internal switch during the FS and

HS chirp states
AGND2 10 - analog ground2 supply
MODE0 11 I operating state and interface selection input 0; see Table 3
MODE1 12 I operating state and interface selection input 1; see Table 3
CLKOUT48 13 O 48 MHz clock output; clock is always running when input

SUSPEND is logic 0; see Section 17 on application of this

clock
RREF 14 AI connection for external reference resistor (12kΩ±1%) to

analog ground supply
CLKOUT30 15 O clock output for Hi-Speed USB digital interface (30 MHz);

clock is always running when input SUSPEND is logic 0
V

CCA3

16 - analog supply voltage 3 (3.3 V)
XTAL2 17 AO crystal oscillator output (12 MHz)
XTAL1 18 AI crystal oscillator input (12 MHz)
AGND3 19 - analog ground3 supply
DDIR 20 I selects direction of 16-bit data bus DATA[15:0]
DATA0 21 I/O data bit 0; bi-directional, slew rate controlled output (5 ns)
DATA1 22 I/O data bit 1; bi-directional, slew rate controlled output (5 ns)
DATA2 23 I/O data bit 2; bi-directional, slew rate controlled output (5 ns)
DATA3 24 I/O data bit 3; bi-directional, slew rate controlled output (5 ns)
DATA4 25 I/O data bit 4; bi-directional, slew rate controlled output (5 ns)
DATA5 26 I/O data bit 5; bi-directional, slew rate controlled output (5 ns)
DATA6 27 I/O data bit 6; bi-directional, slew rate controlled output (5 ns)
DATA7 28 I/O data bit 7; bi-directional, slew rate controlled output (5 ns)
V

CCD1

29 - digital supply voltage 1 (3.3 V)
DGND1 30 - digital ground 1 supply
DATA8 31 I/O data bit 8; bi-directional, slew rate controlled output (5 ns)
DATA9 32 I/O data bit 9; bi-directional, slew rate controlled output (5 ns)
DATA10 33 I/O data bit 10; bi-directional, slew rate controlled output (5 ns)
DATA11 34 I/O data bit 11; bi-directional, slew rate controlled output (5 ns)
DATA12 35 I/O data bit 12; bi-directional, slew rate controlled output (5 ns)
DATA13 36 I/O data bit 13; bi-directional, slew rate controlled output (5 ns)
DATA14 37 I/O data bit 14; bi-directional, slew rate controlled output (5 ns)
DATA15 38 I/O data bit 15; bi-directional, slew rate controlled output (5 ns)
RX_LAST_BYTE 39 O logic 0 — DATA[7:0] = valid data, DATA[15:8] = valid data

logic 1 — DATA[7:0] = valid data, DATA[15:8] = bit stuff
error byte

V

CCD2

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Product data Rev. 02 — 21 November 2002 5 of 40

40 - digital supply voltage 2 (3.3 V)

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Philips Semiconductors

ISP1501

Hi-Speed USB peripheral transceiver

Table 2: Pin description

Symbol

DGND2 41 - digital ground 2 supply
TX_LAST_BYTE 42 I transmit last byte input; used in conjunction with

TX_READY 43 O transmit ready output; a logic 1 means ISP1501 is ready to

TX_BS_EN/FSE0 44 I pin function depends on operating state (see Table 3):

TEST_J_K/
VO

RX_BS_ERROR/
RCV

RX_INACTIVE/VM47 O pin function depends on operating state (see Table 3):

[1]

Pin Type Description

45 I pin function depends on operating state (see Table 3):

46 O pin function depends on operating state (see Table 3):

…continued

TX_BS_EN to indicate different handling of the upper and
lower data byte (see Table 7)

accept data on the next rising clock edge of CLKOUT30

State = 0, 1 — a logic 1 forces single-ended zero (SE0) for
FS transmitter

State = 2, 3 — a logic 1 enables bit stuffing for the HS
transmitter

State = 0, 1 — differential data for the FS transceiver input
State = 2, 3 — a logic 1 enables Hi-Speed USB test

modes TEST_J and TEST_K; it also disables bit stuffing
and NRZI for the HS receiver and transmitter

State = 0, 1 — differential data at D+/D− receiver output
State = 2, 3 — a logic 1 signals a bit stuff error on receive

data; the position of the erroneous byte is indicated by
RX_LAST_BYTE

State = 0, 1 — single-ended D− receiver output
State = 2, 3 — a logic 1 indicates HS line inactivity

RX_VALID/
VP

[1] Symbol names with an overscore (e.g. NAME) indicate active LOW signals.
[2] FS: full-speed (Original USB); HS: high-speed (Hi-Speed USB).

48 O pin function depends on operating state (see Table 3):

State = 0, 1 — single-ended D+ receiver output
State = 2, 3 — valid data on falling clock edge at

pin CLKOUT30

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7. Functional description

The ISP1501 supports both full-speed (FS) and high-speed (HS) USB physical layer
for a Hi-Speed USB peripheral.

An adaptive termination circuit ensures a correct 45 Ω termination for DP and DM.
Calibration is done at power-on and after any operating state change.

An internal bandgap reference circuit is used for generating the driver current and the
biasing of the analog circuits. This circuit requires an external precision resistor
(12 kΩ±1%) to analog ground.

A PLL oscillator using a 12 MHz crystal generates the internal clock of 480 MHz.
Fromthis signal, 30 MHz and 48 MHz clocks are derived for external use (availableat
pins CLKOUT30 and CLKOUT48, respectively).

An internal power-on-reset (POR) circuit monitors the digital supply and is used to
start all circuits in the correct mode. An external reset can be applied via pin RESET.

7.1 Full-speed (FS) transceiver

ISP1501

Hi-Speed USB peripheral transceiver

The full-speed (FS) transceiver interface is a serial interface. Access to this interface
requires pins MODE1 and MODE0 to be set to either the disconnect state or the
full-speed (FS) state. Bit stuffing/de-stuffing and NRZI encoding/decoding must be
implemented on the external ASIC.

When pins MODE1 and MODE0 are in the disconnect or FS states, the FS
transceiver is active and follows the protocol as specified in Table 5. The only
difference between the disconnect and FS states is that the RPU resistor is
disconnected when MODE[1:0] is in the disconnect state whereas the RPU resistor is
connected to the DP line when MODE[1:0] is in the FS state.

To transmit FS USB traffic, pin OE is asserted by holding it at logic 0 (LOW) to enable
the transmit driver.The USB bus will be driven to the USB bus state that corresponds
to the logic conditions of FSE0 and VO. A logic 1 (HIGH) on pin FSE0 forces a USB
SE0 bus state in which both the DP and DM lines are held to a voltage less than
V

OL(max)

(see Table 13), regardless of VO.To force a USB J-state on the bus, FSE0 is
de-asserted (set to logic 0) and VO is asserted (set to logic 1). The DP line will be
held to a voltage greater than V
a voltage less than V

OL(max)

.

OH(min)

(see Table 13), and the DM line will be held to

To receive the FS USB traffic, the transmit driver needs to be disabled by the
de-asserted pin OE by holding it at logic 1. VP and VM always reflect the state of
DP and DM, respectively. An FS J-state (DP > V
bus will assert VP, de-assert VM and assert RCV. An FS K-state (DM > V
DP<V
SE0 on the USB bus (DP and DM < V

) on the USB bus will de-assert VP, assert VM and de-assert RCV. An

IL(max)

) will set VP and VM to LOW.RCV will be

IL(max)

IH(min)

and DM < V

IL(max)

) on the USB

and

IH(min)

held in the same state as it was just before the SE0 condition occurred. In the
suspend mode (SUSPND = HIGH), the differential receiver is inactive and output
RCV is always LOW. Out-of-suspend (‘K’) signalling is detected via the single-ended
receivers VP and VM. During suspend, the (D+, D-) lines are still driven to their

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intended states without slew-rate control. This is permitted because driving during
suspend is used to signal remote wake-up by driving a ‘K’ signal (one transition from
idle to the ‘K’ state) for a period of 1 to 15 ms.

7.2 High-speed (HS) transceiver—transmit logic

The high-speed (HS) transceiver interface uses a 16-bit parallel bi-directional data
interface. This HS module incorporates bit stuffing/de-stuffing and
Non-Return-to-Zero-Inverted (NRZI) encoding/decoding logic. Access to the HS
interface requires MODE[1:0] to be set to either the high-speed (HS) state or the
high-speed (HS) chirp state.

When MODE[1:0] pins are in the HS or HS chirp states, the HS transceiver is active
and follows the protocol as specified in Section 10.1, Section 10.2 and Section 10.3.
One difference between the HS and HS chirp states is that the RPU resistor is
disconnected when MODE[1:0] is in the HS state whereas the RPU resistor is
connected to the DP line when MODE[1:0] is in the HS chirp state. Another difference
between the HS and HS chirp state is that the 45 Ω terminations are disabled from
the DP and DM lines in the HS chirp state.

ISP1501

Hi-Speed USB peripheral transceiver

The 16-bit data bus is a bi-directional bus. Pin DDIR must be set to logic 1 for
clocking data into the 16-bit DATA[15:0] bus so that the payload is transmitted from
the device to the host. If pin DDIR is set to logic 0, the 16-bit data bus is an output to
the external ASIC. Any payload transferred from the host/hub to the transceiver is
clocked out into the 16-bit data bus.

The transmit data is clocked on the rising edge of the 30 MHz clock output
(CLKOUT30). All the handshake signals (TX_LAST_BYTE, TX_BS_EN and
TX_VALID) are latched at the same time. These signals conform to the same set-up
and hold times as specified in Section 17.1. Each set of latched data, including the
16-bit data bus and handshake signals, are qualified if TX_VALID and TX_READY
are asserted during latching. TX_READY transitions take place on the falling edge of
the 30 MHz clock output.

For normal HS transmit, TEST_J_K is set to logic 0. The HS logic will process the
16-bit data with the latched TX_LAST_BYTE and TX_BS_EN signals according to

Table 7, and the processed data is serially driven on the USB bus in HS signaling.

When TEST_J_K is set to logic 1, the TX_BS_EN signal is ignored. The 16-bit input
data will be serially driven on the bus in HS signaling with the NRZI and bit-stuffing
disabled.

7.3 High-speed (HS) transceiver—receive logic

For receiving high-speed (HS) USB signals, the incoming differential signal from the
USB cable is amplified before it is fed into a sampler circuit. In the normal receive
mode, TEST_J_K is set to logic 0 and the over-sampled serial data is NRZI decoded
and bit de-stuffed before being converted to 16-bit parallel words. The 16-bit data and
other handshake signals (RX_BS_ERROR, RX_LAST_BYTE and RX_VALID) are
latched on the falling edge of CLKOUT30 in accordance with the timings as specified
in Table 18.

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When TEST_J_K is set to logic 1, the sampled data from the differential amplifier will
not be NRZI decoded and bit de-stuffed. All serial HS USB signals are
passed-through and converted to 16-bit data on the parallel data bus. The handshake
signals (RX_BS_ERROR, RX_LAST_BYTE and RX_VALID) are invalid.

7.4 High-speed (HS) transceiver—periphery circuit

To maintain a constant current driver for high-speed (HS) transmit and biasing of
other analog circuits, an internal bandgap reference circuit and RREF resistor are
used to form the reference current. This circuit requires an external precision resistor
(12 kΩ±1%) from pin RF to the analog ground. A pull-up resistor of 1.5 kΩ±5%
must be connected between pin RPU and V
of less than ±500 ppm must be used between pins XTAL1 and XTAL2. Alternatively,
an input clock (3.3 V, 12 MHz clock ±500 ppm, duty cycle between 40 and 60%) can
also be used to drive pin XTAL1 (pin XTAL2 is left open).

8. Operating states

ISP1501

Hi-Speed USB peripheral transceiver

. A 12 MHz crystal with an accuracy

CCA3

8.1 Interface and state selection

The MODE1 and MODE0 pins control the operating states of the ISP1501 and select
the appropriate function of multiplexed pins (see Table 3).

Table 3: Interface selection

MODE[1:0] State State name Pin Function

00 0 Disconnect 2

44 FSE0
45 VO
46 RCV
47 VM
48 VP

01 1 Full-speed (FS) 2

44 FSE0
45 VO
46 RCV
47 VM
48 VP

10 2 High-speed (HS) 2

44 TX_BS_EN
45 TEST_J_K
46 RX_BS_ERROR
47 RX_INACTIVE
48 RX_VALID

OE

OE

TX_VALID

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Product data Rev. 02 — 21 November 2002 9 of 40

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ISP1501

Hi-Speed USB peripheral transceiver

Table 3: Interface selection

…continued

MODE[1:0] State State name Pin Function

11 3 High-speed (HS)

chirp

2 TX_VALID
44 TX_BS_EN
45 TEST_J_K
46 RX_BS_ERROR
47 RX_INACTIVE
48 RX_VALID

8.2 State transitions

A Hi-Speed USB peripheral handles more than one electrical state under the USB
specification. The ISP1501 accommodates the various states through the MODE[1:0]
input pins. Table 4 summarizes the operating states.

Table 4: Operating states

State State name Description

0 Disconnect Legacy (full-speed) SIE interface; FS transceiver

enabled; pull-up resistor on pin RPU disconnected

1 Full-speed (FS) Legacy (full-speed) SIE interface; FS transceiver

enabled; full-speed slew rate selected; pull-up resistor
on pin RPU connected to pin DP

2 High-speed (HS) High-speed SIE interface; HS transceiver enabled;

FS transceiver on permanent SE0 to provide 45 Ω
termination; pull-up resistor on pin RPU disconnected

3 High-speed (HS) chirp High-speed SIE interface; HS transceiver enabled;

FS transceiver disabled; pull-up resistor on pin RPU
connected to pin DP

8.2.1 Disconnect state

In the disconnect state (MODE[1:0] = 00), an external pull-up resistor on pin RPU is
not connected to the DP line. The FS transceiver is enabled, and the legacy (Original
USB) SIE interface is active (see Figure 3).

3.3 V

1.5 kΩ
± 5%

RPU

9

ISP1501

45 Ω

45 Ω

FS driver

Fig 3. Disconnect state.

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Product data Rev. 02 — 21 November 2002 10 of 40

004aaa039

7

DP

DM

6

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8.2.2 Full-speed (FS) state

In the full-speed (FS) state (MODE[1:0] = 01), an external pull-up resistor of

1.5 kΩ±5% is required on the DP line. This is implemented via the RPU resistor.The
RPU resistor is internally connected to the DP line. The FS transceiver is enabled,
and the legacy (Original USB) SIE interface is active (see Figure 4).

ISP1501

ISP1501

Hi-Speed USB peripheral transceiver

3.3 V

1.5 kΩ
± 5%

RPU

9

Fig 4. Full-speed state.

8.2.3 High-speed (HS) state

In the high-speed (HS) state, internal 45 Ω resistors on the DP and DM lines are
connected to the ground. The pull-up resistor is disconnected. The HS transceiver is
enabled, and the parallel interface and the HS-handshake signals are used (see

Figure 5).

FS driver

ISP1501

HS current
driver

45 Ω

45 Ω

004aaa052

7

DP

DM

6

3.3 V

1.5 kΩ
± 5%

RPU

9

7

DP

DM

6

45 Ω45 Ω

004aaa041

Fig 5. High-speed state.

8.2.4 High-speed (HS) chirp state

In the high-speed (HS) chirp state, 45 Ω terminations are disabled from the
DP and DM lines. The pull-up resistor is connected on the DP line. The
HS transceiveris enabled, and the parallel interface and HS handshake signals are in
use (see Figure 6).

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Product data Rev. 02 — 21 November 2002 11 of 40

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Fig 6. High-speed chirp state.

ISP1501

HS current
driver

ISP1501

Hi-Speed USB peripheral transceiver

3.3 V

1.5 kΩ
± 5%

RPU

9

7

DP

DM

6

45 Ω45 Ω

004aaa040

8.3 Reset

The output clocks are affected by pin RESET and may show a momentary change at
RESET. The ASIC may not transmit or receive data while the ISP1510 RESET is
driven LOW.

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Product data Rev. 02 — 21 November 2002 12 of 40

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