Philips ISP1301 User Guide

ISP1301

Universal Serial Bus On-The-Go transceiver

Rev. 01 — 14 April 2004 Product data

1. General description

The ISP1301 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver device that isfully compliant with

Supplement to the USB Speciﬁcation Rev. 1.0a

receive serial data at both full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) data rates.

It is ideal for use in portable electronics devices, such as mobile phones, digital still cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio players. It allows USB Application Speciﬁc Integrated Circuits (ASICs), Programmable Logic Devices (PLDs) and any system chip set (with the USB host or device function built-in but without the USB physical layer)to interface to the physical layer of the USB.

The ISP1301 can interface to devices with digital I/O voltages in the range of

1.65 V to 3.6 V.

UniversalSerial Bus Speciﬁcation Rev. 2.0

. The ISP1301 can transmit and

and

On-The-Go

2. Features

The ISP1301 is available in HVQFN24 package.

■ Fully complies with:

◆

Universal Serial Bus Speciﬁcation Rev. 2.0

◆

On-The-Go Supplement to the USB 2.0 Speciﬁcation Rev. 1.0a

◆

On-The-Go Transceiver Speciﬁcation (CEA–2011) Rev. 1.0

■ Can transmit and receive serial data at both full-speed (12 Mbit/s) and low-speed

(1.5 Mbit/s) data rates

■ Ideal for system ASICs or chip sets with built-in USB OTG dual-role core

■ Supports mini USB analog car kit interface

■ Supports various serial data interface protocols; transparent general-purpose

buffer mode allows you to control the direction of data transfer

■ Supports data line and V

■ Contains Host Negotiation Protocol (HNP) command and status registers

■ Supports serial I2C-bus™ interface for OTG status and command controls

■ 2.7 V to 4.5 V power supply input range for the ISP1301

■ Built-in charge pump regulator outputs 5 V at current greater than 8 mA

■ Supports external charge pump

■ Supports wide range interfacing I/O voltage (V

control logics

pulsing session request

BUS

DD_LGC

= 1.65 V to 3.6 V) for digital

Philips Semiconductors

ISP1301

USB OTG transceiver

3. Applications

4. Abbreviations

■ 8 kV built-in electrostatic discharge (ESD) protection on the DP, DM, V

lines

■ Full industrial grade operation from −40 °Cto+85°C

■ Available in a small HVQFN24 (4 × 4mm2) halogen-free and lead-free package.

■ Mobile phone

■ Digital camera

■ Personal digital assistant

■ Digital video recorder.

ASIC — Application-Speciﬁc Integrated Circuit ATX — Analog USB transceiver HNP — Host Negotiation Protocol ESD — ElectroStatic Discharge I2C-bus — Inter IC-bus IC — Integrated Circuit OTG — On-The-Go PDA — Personal Digital Assistant SE0 — Single-Ended zero SOF — Start-of-Frame SRP — Session Request Protocol USB — Universal Serial Bus USB-IF — USB Implementers Forum.

BUS

and ID

5. Ordering information

Table 1: Ordering information

Type number

ISP1301BS HVQFN24 plastic thermal enhanced very thin quad ﬂat package;

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Package Name Description Version

SOT616-1

no leads; 24 terminals; body 4 × 4 × 0.85 mm

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6. Block diagram

ISP1301

USB OTG transceiver

SCL

SDA

ADR/PSW

INT_N

OE_N/INT_N

DAT/VP SE0/VM

RCV

SPEED

SUSPEND

DD_LGC

REG(3V3)

720

3.3 V DC-DC

REGULATOR

BAT

C2 C1

22 21

BUS

CHARGE PUMP

CGND

BUS

ISP1301

3 2 1 5

SERIAL

CONTROLLER

14 13

12 11 10

6 8

LEVEL

SHIFTER

CARKIT

INTERRUPT

DETECTOR

BUS

COMPARATORS

ID DETECTOR

PULL-UP AND

PULL-DOWN

RESISTORS

RESET_N

Fig 1. Block diagram.

exposed die pad

DGND AGND

TRANSCEIVER

USB

004aaa195

DM DP

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7. Pinning information

7.1 Pinning

ISP1301

USB OTG transceiver

DD_LGC

ADR/PSW

SDA

SCL

RESET_N

INT_N

SPEED

REG(3V3)

CGND

ISP1301BS

SUSPEND

22 21 20

9 10 11

OE_N/INT_N

Fig 2. Pin conﬁguration HVQFN24 (top view).

REG(3V3)

SUSPEND

SPEED

OE_N/INT_N

91011

BAT

BUS

AGND

DAT/VP

SE0/VM

004aaa542

RCV

SE0/VM

INT_N

RESET_N

SCL

SDA

ADR/PSW

Bottom view

DD_LGC

DGND

(exposed die pad)

ISP1301BS

terminal 1

22 21 20

CGND

BAT

DAT/VP

AGND

004aaa196

BUS

Fig 3. Pin conﬁguration HVQFN24 (bottom view).

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7.2 Pin description

ISP1301

USB OTG transceiver

Table 2: Pin description

Symbol

ADR/PSW 1 I/O high-Z ADR input — sets the least-signiﬁcant I

SDA 2 I/OD high-Z serial I

SCL 3 I/OD high-Z serial I

RESET_N 4 I - asynchronous reset; active LOW

INT_N 5 OD high-Z interrupt output; active LOW

SPEED 6 I - speed selection input for the ATX;effectivewhen

[2]

Pin Type

[1]

[3]

Reset value

Description

C-bus address bit of the ISP1301; latched-on reset (including power-on reset)

PSW output — enables or disables the external charge pump after reset

bidirectional; push-pull input; three-state output

C-bus data input and output

bidirectional; push-pull input; open-drain output

C-bus clock input and output

bidirectional; push-pull input; open-drain output

push-pull input

open-drain output

bit SPD_SUSP_CTRL = 0:

• LOW: low-speed

• HIGH: full-speed.

push-pull input

REG(3V3)

SUSPEND 8 I - suspend selection input for ATX; effective when

7 P - output of the internal voltage regulator; an

external decoupling capacitor of 0.1 µF is required

bit SPD_SUSP_CTRL = 0:

• LOW: normal operating

• HIGH: suspend.

push-pull input

OE_N/ INT_N

VM 10 O - single-ended DM receiver output

VP 11 O - single-ended DP receiver output

RCV 12 O 0 differential receiver output; reﬂects the

9 I/O high-Z OE_N input — enable driving DP and DM when

in the USB mode INT_N output — interrupt (push pull) when

suspended and bit OE_INT_EN = 1 bidirectional; push-pull input; three-state output

push-pull output

differential value of DP and DM push-pull output

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Table 2: Pin description

Symbol

SE0/VM 13 I/O -

DAT/VP 14 I/O -

DM 15 AI/O - USB data minus pin (D−) DP 16 AI/O - USB data plus pin (D+) AGND 17 P - analog ground ID 18 AI/O - identiﬁcation detector input and output;

BUS

BAT

C1 21 AI/O - charge pump capacitor pin 1; typically use a

C2 22 AI/O - charge pump capacitor pin 2; typically use a

CGND 23 P - ground for the charge pump V

DD_LGC

DGND exposed

ISP1301

USB OTG transceiver

[1]

…continued

[2]

Pin Type

19 AI/O - V

20 P - supply voltage (2.7 V to 4.5 V)

24 P - supply voltage for the interface logic signals

die pad

[3]

Reset

Description

value

[4]

SE0 (input and output) — SE0 function in DAT_SE0 USB mode

VM (input and output) — VM function in VP_VM USB mode

bidirectional; push-pull input; three-state output

[4]

DAT (input and output) — DAT function in DAT_SE0 USB mode

VP (input and output) — VP function in VP_VM USB mode

bidirectional; push-pull input; three-state output

connected to the ID pin of the USB mini receptacle

line input and output of the USB interface;

BUS

place an external decoupling capacitor of 0.1 µF close to this pin

100 nF capacitor between pins C1 and C2

(1.65 V to 3.6 V)

P - digital ground

[1] A detailed description of these pins can be found in Section 8.9. [2] Symbol names ending with underscore N (for example, NAME_N) indicate active LOW signals. [3] I = input; O = output; I/O = digital input/output; OD = open-drain output; AI/O = analog input/output;

P = power or ground pin.

[4] High-Z when pin OE_N/INT_N is LOW. Driven LOW when pin OE_N/INT_N is HIGH.

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8. Functional description

8.1 Serial controller

The serial controller includes the following functions:

• I

C-bus slave interface

• Interrupt generator

• Mode Control registers

• OTG registers

• Interrupt related registers

• Device identiﬁcation registers.

The serial controller acts as an I2C-bus slave, and uses the SCL and SDA pins to communicate with the OTG controller.

For more details on serial controller, see Section 11.

ISP1301

USB OTG transceiver

8.2 V

charge pump

BUS

The charge pump supplies current to the V following modes:

• Output 5 V at current greater than 8 mA

• Pull-up V

• Pull-down V

before initiating SRP.

8.3 V

8.3.1 V

8.3.2 Session valid comparator

comparators

BUS

comparators provide indications regarding the voltage level on V

BUS

valid comparator

BUS

This comparator is used by an A-device to determine whether or not the voltage on V

is at a valid level for operation. The minimum threshold for the V

BUS

comparator is 4.4 V. Any voltage on V fault. During power up, it is expected that the comparator output will be ignored.

The session valid comparator is a TTL-level input that determines when V enough for a session to start. Both the A-device and the B-device use this comparator to detect when a session is being started. The A-device also uses this comparator to indicate when a session is completed. The session valid threshold of the ISP1301 is between 0.8 Vand 2.0 V.

to 3.3 V through a resistor (R

BUS

to ground through a resistor (R

BUS

line. It can operate in any of the

BUS

VBUS(PU)

below this threshold is considered to be a

BUS

) for initiating V

VBUS(PD)

) for discharging V

pulsing SRP

BUS

valid

BUS

is high

8.3.3 Session end comparator

The session end comparator determines when V

is below the B-device session

BUS

end threshold of 0.2 V to 0.8 V.

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8.4 ID detector

In either the active or suspended power mode, the ID detector senses the condition of the ID line and differentiates between the following three conditions:

• Pin ID is ﬂoating; bit ID_FLOAT = 1

• Pin ID is shorted to ground; bit ID_GND = 1

• Pin ID is connected to ground through resistor R

The ID detector also has a switch that can be used to ground pin ID. This switch is controlled by bit ID_PULLDOWN in the serial controller.

8.5 Pull-up and pull-down resistors

The pull-up and pull-down resistors include the following switchable resistors:

• Pin DP pull-up

• Pin DP pull-down

• Pin DM pull-up

• Pin DM pull-down.

ID_GND = 0.

ISP1301

USB OTG transceiver

; bit ID_FLOAT = 0 and bit

ACC_ID

The pull-up resistor is a context variable as described in the document. The variable pull-up resistor hardware is implemented to meet the USB ECN_27% speciﬁcation.

ECN_27%_Resistor

8.6 USB transceiver (ATX)

The behavior of the USB transceiver depends on the operation mode of the ISP1301:

• In the USB mode, the USB transceiver block performs USB full-speed or

low-speed transceiver functions. This includes differential driver, differential receiver and single-ended receivers.

• In the transparent general purpose buffer mode or the UART mode, the USB

transceiverblockfunctions as a level shifter between the pins DAT/VP and SE0/VM and the pins DP and DM.

8.7 3.3 V DC-DC regulator

The built-in 3.3 V DC-DC regulator conditions the supply voltage (V ISP1301:

• V

The output of the regulator can be monitored on the V

= 3.6 V to 4.5 V: the regulator will output 3.3 V ± 10 %

BAT

< 3.6 V: the regulator will be bypassed.

BAT

REG(3V3)

pin.

) for use in the

BAT

8.8 Car kit interrupt detector

The car kit interrupt detector is a comparator that detects when the DP line is below the car kit interrupt threshold V detector is enabled in the audio mode only (bit AUDIO_EN = 1).

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PH_CR_INT

(0.4 V to 0.6 V). The car kit interrupt

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8.9 Detailed description of pins

8.9.1 ADR/PSW

The ADR/PSW pin has two functions. On reset (including power-on reset), the level on this pin is latched as ADR_REG, which represents the least signiﬁcant bit (LSB) of the I2C address of the ISP1301. If bit ADR_REG = 0, the I2C-bus address for the ISP1301 is 0101100 (0x2C); if bit ADR_REG = 1, the I2C-bus address for the ISP1301 is 0101101 (0x2D).

After reset, the ADR/PSW pin can be programmed as an output. If in the Mode Control 2 register bit PSW_OE = 1, then the ADR/PSW output will be enabled. The logic level will be determined by bit ADR_REG. If bit ADR_REG = 0, then the ADR/PSW pin will drive HIGH. If bit ADR_REG = 1, then the ADR/PSW pin will drive LOW.

The ADR/PSW pin can be used to turn on or off the external charge pump. The ISP1301 built-in charge pump supports V more current support (for example, 50 mA), an external charge pump may be needed. In this case, the ADR/PSW pin can act as a power switch for the external charge pump. Figure 4 shows an example of using external charge pump.

ISP1301

USB OTG transceiver

current at 8 mA. If the application needs

BUS

ISP1301

Fig 4. Using external charge pump.

8.9.2 SCL and SDA

The SCL (serial clock) and SDA (serial data) signals implement a two-wire serial I2C-bus.

8.9.3 RESET_N

Active LOW asynchronous reset for all digital logic. Either connect this pin to V for power-on reset or apply a minimum of 10 µs LOW pulse for hardware reset.

ADR/PSW

BUS

+3.3 V

100 kΩ

BAT

CHARGE PUMP

ON/OFF

OUT

4.7 µF

BUS

DM DP

GND

004aaa437

DD_LGC

8.9.4 INT_N

The INT_N (interrupt) pin is asserted while an interrupt condition exists. It is deasserted when the Interrupt Latch register is cleared. The INT_N pin is open-drain, and, therefore, can be connected using a wired-AND with other interrupt signals.

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8.9.5 OE_N/INT_N

Pin OE_N/INT_N is normally an input to the ISP1301. When bit TRANSP_EN = 0 and bit UART_EN = 0, the OE_N/INT_N pin controls the

direction of DAT/VP, SE0/VM, DP and DM as indicated in Table 4. When suspended (either pin SUSPEND = HIGH or bit SUSPEND_REG = 1) and bit

OE_INT_EN = 1, pin OE_N/INT_N becomes a push-pull output (active LOW) to indicate the interrupt condition.

8.9.6 SE0/VM, DAT/VP, RCV, VM and VP

The ISP1301 transmits USB data on the USB line under the following conditions:

• Bit TRANSP_EN = 0

• Bit UART_EN = 0

• Pin OE_N/INT_N = LOW.

Table 10 shows the operation of the SE0/VM and DAT/VP pins during the transmit

operation. The RCV pin is not used during transmit.

ISP1301

USB OTG transceiver

The ISP1301 receives USB data from the USB line under the following conditions:

• Bit TRANSP_EN = 0

• Bit UART_EN = 0

• Pin OE_N/INT_N = HIGH.

Table 12 shows the operation of the SE0/VM, DAT/VP and RCV pins during the

receive operation. The VP and VM pins are single-ended receiver outputs of the DP and DM pins,

respectively.

8.9.7 DP and DM

The DP (data plus) and DM (data minus) pins implement the USB data signals. When in the transparent general-purpose buffer mode, the ISP1301 operates as a level shifter between the (DAT/VP, SE0/VM) and (DP, DM) pins.

8.9.8 ID

The ID (identiﬁcation) pin is connected to the ID pin on the USB mini receptacle. An internal pull-up resistor (to V ID_PULLDOWN is set, the ID pin will be shorted to ground.

8.9.9 V

BUS

This pin acts as an input to the V

REG(3V3)

BUS

) is connected to this pin. When bit

comparator or an output from the charge pump.

When the VBUS_DRV bit of the OTG Control register is asserted, the ISP1301 tries to drive V least 8 mA.

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to a voltage of 4.4 V to 5.25 V with an output current capability of at

BUS

Philips Semiconductors

ISP1301

USB OTG transceiver

8.9.10 V

BAT

This pin is an input and supplies power to the ISP1301. The ISP1301 operates when V

is between 2.7 V and 4.5 V.

BAT

8.9.11 C1 and C2

The C1 and C2 pins are for connecting the ﬂying capacitor of the charge pump. The output current capacity of the charge pump depends on the value of the capacitor. For maximum efﬁciency, place capacitors as close as possible to the pins.

Fig 5. Charge pump capacitor.

Table 3: Recommended charge pump capacitor value

ext

47 nF 8 mA 100 nF 18 mA

ISP1301

004aaa278

BUS

IL (max)

ext

[1]

[2]

8.9.12 V

[1] For output voltage V [2] For V

DD_LGC

= 3.0 V to 4.5 V.

BAT

> 4.7 V (bit VBUS_VLD = 1).

BUS

This pin is an input and sets logic thresholds. It also powers the pads of the following logic pins:

• ADR/PSW

• DAT/VP, SE0/VM and RCV

• VM and VP

• INT_N

• OE_N/INT_N

• RESET_N

• SPEED

• SUSPEND

• SCL and SDA.

8.9.13 AGND, CGND and DGND

AGND, CGND and DGND are ground pins for analog, charge pump and digital circuits, respectively. These pins can be connected separately or together depending on the system performance requirements.

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9. Modes of operation

There are four types of modes in the ISP1301:

• Power modes

• Direct I

• USB modes

• Transparent modes.

9.1 Power modes

The power modes of the ISP1301 are as follows:

• Active power mode: power is on.

• USB suspend mode: to reduce power consumption, the USB differential receiver is

powered down.

• Global power-down mode: set bit GLOBAL_PWR_DN = 1 of the Mode Control 2

register; the differential transmitter and receiver, clock generator, charge pump, and all biasing circuits are turned off to reduce power consumption to the minimum possible; for details on waking up the clock, see Section 12.

C-bus mode

ISP1301

USB OTG transceiver

9.2 Direct I2C-bus mode

In the direct I2C-bus mode, an external I2C-bus master (OTG controller) directly communicates with the serial controller through the SCL and SDA lines. The serial controller has a built-in I2C-bus slave function.

In this mode, an external I2C-bus master can access the internal registers of the device (Status, Control, Interrupt, and so on) through the I2C-bus interface.

The supported I2C-bus bit rate is 100 kbit/s (maximum). The ISP1301 is in the direct I2C-bus mode when either bit TRANSP_EN bit = 0 or pin

OE_N/INT_N is deasserted.

9.3 USB modes

The four USB modes of the ISP1301 are:

• VP_VM unidirectional mode

• VP_VM bidirectional mode

• DAT_SE0 unidirectional mode

• DAT_SE0 bidirectional mode.

In the VP_VM USB mode, the DAT/VP pin is used for the VP function, the SE0/VM pin is used for the VM function, and the RCV pin is used for the RCV function.

In the DAT_SE0 USB mode, the DAT/VP pin is used forthe DAT function, the SE0/VM pin is used for the SE0 function, and the RCV pin is not used.

In the unidirectional mode, the DAT/VP and SE0/VM pins are always inputs. In the bidirectional mode, the direction of these signals depends on the OE_N/INT_N input.

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Table 6 speciﬁes the functionality of the device during the four USB modes.

The ISP1301 is in the USB mode when both the TRANSP_EN and UART_EN bits are cleared.

9.4 Transparent modes

9.4.1 Transparent general-purpose buffer mode

In the transparent general-purpose buffer mode, the DAT/VP and SE0/VM pins are connected to the DP and DM pins, respectively. Using bits TRANSP_BDIR1 and TRANSP_BDIR0 of the Mode Control 2 register as speciﬁed in Table 8, you can control the direction of data transfer. The ISP1301 is in the transparent general-purpose buffer mode if bit TRANSP_EN = 1 and bit DAT_SE0 = 1.

9.4.2 Transparent UART mode

When in the transparent UART mode, the ATX behaves as two logic level translator between the following pins:

ISP1301

USB OTG transceiver

• For TxD signal: from SE0/VM (V

• For RxD signal: from DP (+3.3 V level) to DAT/VP (V

level) to DM (+3.3 V level)

DD_LGC

level).

In the UART mode, the OTG controller is allowed to connect a UART to the DAT/VP and SE0/VM pins of the ISP1301.

The UART mode is entered by setting the UART_EN bit in the Mode Control 1 register. The UART mode is equivalent to one of the transparent general purpose buffer mode (bit TRANSP_BDIR1 = 1, bit TRANSP_BDIR0 = 0).

9.4.3 Summary tables

Table 4: Device operating modes

Mode USB

suspend condition

Direct I

USB modes

USB suspend mode 1 X X 0 0 see Table 5 and Table 7 USB functional mode 0 X X 0 0 ATX is fully functional; seeTable 6

Transparent modes

Transparent general-purpose buffer mode

Transparent UART mode X X X X 1 DAT/VP <= DP (RxD signal of UART)

C-bus mode

C-bus mode X X X 0 X

X X HIGH 1 X X1X1X

X 1 X 1 0 ATX is not functional; see Table 8

Bit DAT

[1]

_SE0

Pin OE_N/ INT_N

Bit TRANSP _EN

Bit UART _ EN

Description

SE0/VM => DM (TxD signal of UART); ATX is not functional

[1] Conditions:

a) bit SPD_SUSP_CTRL = 0 and pin SUSPEND = HIGH, or b) bit SPD_SUSP_CTRL = 1 and bit SUSPEND_REG = 0.

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Table 5: USB suspend mode: I/O

Pin Function

DP as output can be driven if pin OE_N/INT_N is active LOW, otherwise high-Z DM as output can be driven if pin OE_N/INT_N is active LOW, otherwise high-Z V

BUS

SCL connected to SCL I/O of the I SDA connected to SDA I/O of the I

[1] In the USB suspend mode, the ISP1301 can drive the DP and DM lines, if the OE_N/INT_N input

ISP1301

USB OTG transceiver

[1] [1]

can be driven depending on bit VBUS_DRV

C-bus slave

(when the OE_INT_EN bit is not set) is LOW. In such a case, these outputs are driven as in the USB functional modes, but with the full-speed characteristics, irrespective of the value of the SPEED input pin or the SPEED_REG bit.

Table 6: USB functional modes: I/O values

[1]

USB mode Bit Pin

DAT_SE0 BI_DI OE_N/

DAT/VP SE0/VM VP VM RCV

INT_N

VP_VM unidirectional 0 0 X TxD+

bidirectional 0 1 LOW TxD+

0 1 HIGH RxD+

DAT_SE0 unidirectional 1 0 X TxD

bidirectional 1 1 LOW TxD

1 1 HIGH RxD

[1] Some of the modes and signals are provided to achieve backward compatibility with IP cores. [2] TxD+ and TxD− are single-ended inputs for driving the DP and DM outputs, respectively, in the single-ended mode. [3] RxD+ and RxD− are the outputs of the single-ended receivers connected to DP and DM, respectively. [4] TxD is the input for driving DP and DM in the DAT_SE0 mode. [5] FSE0 is for forcing an SE0 on the DP and DM lines in the DAT_SE0 mode. [6] RxD is the output of the differential receiver. [7] RSE0 is an output indicating that an SE0 has been received on the DP and DM lines.

[2] [2]

[3] [4] [4]

[6]

TxD− TxD− RxD− FSE0 FSE0 RSE0

[2] [2]

[3] [5] [5]

[7]

RxD+

[3]

RxD−

Table 7: USB suspend mode: I/O values

USB suspend mode Input pin Output pin

DP DM DAT/VP SE0/VM VP VM RCV

DAT_SE0 (bit DAT_SE0 = 1)

LOW LOW LOW HIGH LOW LOW LOW HIGH LOW HIGH LOW HIGH LOW LOW LOW HIGH LOW LOW LOW HIGH LOW HIGH HIGH HIGH LOW HIGH HIGH LOW

VP_VM (bit DAT_SE0 = 0)

LOW LOW LOW LOW LOW LOW LOW HIGH LOW HIGH LOW HIGH LOW LOW LOW HIGH LOW HIGH LOW HIGH LOW HIGH HIGH HIGH HIGH HIGH HIGH LOW

[3]

RxD

[3]

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