Philips ISP1183 User Manual

ISP1183

Low-power Universal Serial Bus interface device with DMA

Rev. 01 — 24 February 2004 Product data

1. General description

The ISP1183 is a Universal Serial Bus (USB) interface device that complies with

Universal Serial Bus Speciﬁcation Rev. 2.0

(12 Mbit/s). It provides full-speed USB communication capacity to microcontroller or microprocessor-based systems. The ISP1183 communicates with the system’s microcontroller or microprocessor through a fast general-purpose parallel interface.

The ISP1183 supports fully autonomous, multiconﬁgurable Direct Memory Access (DMA) operation.

The modular approach to implementing a USB interface device allows designer to select the optimum system microcontroller from the wide variety available. The ability to reuse existing architecture and ﬁrmware investments shortens development time, eliminates risks and reduces costs. The result is fast and efﬁcient development of the most cost-effective USB peripheral solution.

, supporting data transfer at full-speed

2. Features

The ISP1183 supports I/O voltage range of 1.65 V to 3.6 V enabling it to be directly interfaced to battery-operated devices, such as mobile phones. The ISP1183 is ideally suited for battery-operated (low power) application in many portable peripherals such as mobile phones, Personal Digital Assistants (PDAs) and MP3 players. This device can be used in bus-powered or hybrid-powered applications. Also, more number of endpoints in the ISP1183 enable the device to be used in applications such as multifunctional printers, other than standard applications such as printers, communication devices, scanners, external mass storage devices and digital still cameras.

■ Complies with

speciﬁcations

■ Complies with ACPI™, OnNow™ and USB power management requirements

■ Supports data transfer at full-speed (12 Mbit/s)

■ High performance USB interface device with integrated Serial Interface Engine

(SIE), FIFO memory, transceiver, and 3.3 V voltage regulator

■ High speed (11.1 Mbyte/s or 90 ns read/write cycle) parallel interface

■ Fully autonomous and multiconﬁguration DMA operation

■ Up to 14 programmable USB endpoints with 2 ﬁxed control IN/OUT endpoints

■ Integrated physical 2462 bytes of multiconﬁguration FIFO memory

■ Endpoints with double buffering to increase throughput and ease real-time data

transfer

■ Seamless interface with most microcontrollers and microprocessors

Universal Serial Bus Speciﬁcation Rev. 2.0

and most Device Class

Philips Semiconductors

■ Bus-powered capability with low power consumption and low suspend current

■ Software controlled connection to the USB bus (SoftConnect™)

■ Supports internal power-on and low-voltage reset circuit

■ Supports software reset

■ Hybrid-powered capability with low-power consumption required from the system

■ V

■ 6 MHz crystal oscillator input with integrated PLL for low EMI

■ Good USB connection indicator that blinks with trafﬁc (GoodLink™)

■ Supports I/O voltage range of 1.65 V to 3.6 V

■ Operation over the extended USB bus voltage range (4.0 V to 5.5 V) with 3.3 V

■ Operating temperature range −40 °Cto+85°C

■ Full-scan design with high fault coverage

■ Available in HVQFN32 lead-free and halogen-free package.

3. Applications

indication

BUS

tolerant I/O pads

ISP1183

Low-power USB interface device with DMA

4. Abbreviations

■ Battery-operated device, for example:

◆ Mobile phone

◆ MP3 player

◆ Personal Digital Assistant (PDA)

■ Communication device, for example:

◆ Router

◆ Modem

■ Digital camera

■ Mass storage device, for example:

◆ Zip® drive

■ Printer

■ Scanner.

CRC — Cyclic Redundancy Check DMA — Direct Memory Access EMI — ElectroMagnetic Interference FIFO — First In, First Out MMU — Memory Management Unit PID — Packet IDentiﬁer PIO — Parallel I/O PLL — Phase-Locked Loop SIE — Serial Interface Engine USB — Universal Serial Bus.

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5. Ordering information

Table 1: Ordering information

Type number

ISP1183BS HVQFN32 plastic thermal enhanced very thin quad ﬂat package;

ISP1183

Low-power USB interface device with DMA

Package Name Description Version

SOT617-1

no leads; 32 terminals; body 5 × 5 × 0.85 mm

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6. Block diagram

Philips Semiconductors

to and from USB

3.3 V

1.5 kΩ

ANALOG

POWER-ON

VOLTAGE

REGULATOR

Tx/Rx

RESET

BUS

SoftConnect

internal reset

3.3 V

6 MHz

XTAL2XTAL1

PLL

OSCILLATOR

BIT CLOCK

RECOVERY

PHILIPS

SIE

48 MHz

12 MHz

MEMORY

MANAGEMENT

UNIT

INTEGRATED

RAM

ISP1183

CONTROLLER

HANDLER

ENDPOINT

HANDLER

MICRO

DMA

HANDLER

BUS

INTERFACE

DGND

5, 22, 25

1.65 V to

3.6 V

LEVEL

SHIFTER

PADS

19, 20, 23, 24, 26 to 29

1 2

4 17

13 15

to and from

microcontroller

DATA[7:0]

INT_N CS_N WR_N

RD_N

VBUSDET_N

DACK

DREQ

WAKEUP

SUSPEND

RESET_N

Low-power USB interface device with DMA

11 12

AGND

Fig 1. Block diagram.

REG(3V3)

DD(I/O)

18, 30

004aaa288

ISP1183

Philips Semiconductors

7. Pinning information

7.1 Pinning

ISP1183

Low-power USB interface device with DMA

REG(3V3)

AGND

VBUSDET_N

DREQ

DACK 15

RESET_N

XTAL2 XTAL1

DGND

RD_N

WR_N

CS_N

INT_N

Bottom view

BUS

8 7

6 5 4 3 2

GND (exposed die pad)

ISP1183BS

terminal 1

DD(I/O)

WAKEUP

DATA7

SUSPEND

DATA6

DATA5

DATA4

DGND

17 18

19 20 21 22

23 24

004aaa433

Fig 2. Pin conﬁguration HVQFN32.

7.2 Pin description

Table 2: Pin description

Symbol

INT_N 1 O interrupt output; active LOW

CS_N 2 I chip select input

WR_N 3 I write strobe input

RD_N 4 I read strobe input

DGND 5 - digital ground supply XTAL1 6 I crystal oscillator input (6 MHz); connect a fundamental

XTAL2 7 O crystal oscillator output (6 MHz); connect a fundamental

[1]

Pin Type Description

3.3 V tolerant I/O pad

parallel-resonant crystal or an external clock source (leave pin XTAL2 unconnected)

parallel-resonant crystal; leave this pin open when using an external clock source on pin XTAL1

DD(I/O) DATA0 DATA1

DGND

DATA2

DATA3

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ISP1183

Low-power USB interface device with DMA

Table 2: Pin description

BUS

[1]

Pin Type Description

8IV

Symbol

…continued

BUS

sensing input and power supply input; see

Section 8.11

DM 9 AI/O USB D− line connection (analog) DP 10 AI/O USB D+ line connection (analog) AGND 11 - analog ground supply V

REG(3V3)

12 - regulated supply voltage (3.3 V ± 10 %) from internal

regulator; used to connect a 0.1 µF decoupling capacitor

and pull-up resistor on pin DP

Remark: Cannot be used to supply external devices. VBUSDET_N 13 O V

indicator output (active LOW); see Table 3

BUS

DREQ 14 O DMA request output (4 mA; programmable polarity, see

Table 21); signals to the DMA controller that the ISP1183

wants to start a DMA transfer

3.3 V tolerant I/O pad

DACK 15 I DMA acknowledge input (programmable polarity, see

Table 21); used by the DMA controller to signal the start of a

DMA transfer requested by the ISP1183; when not in use,

connect this pin to ground through a 10 kΩ resistor

3.3 V tolerant I/O pad

RESET_N 16 I reset input (Schmitt trigger); a LOW level produces an

asynchronous reset

3.3 V tolerant I/O pad

A0 17 I address input; selects command (A0 = HIGH) or data

(A0 = LOW)

3.3 V tolerant I/O pad

DD(I/O)

18 - I/O power supply; add a decoupling capacitor of 0.1 µF

(1.65 V to 3.6 V); see Section 8.11 DATA0 19 I/O data bit 0 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad DATA1 20 I/O data bit 1 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad V

21 - 3.3 V output voltage; internally connected to the regulator

output; connect to a decoupling capacitor of 0.1 µF DGND 22 digital ground supply DATA2 23 I/O data bit 2 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad DATA3 24 I/O data bit 3 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad DGND 25 - digital ground supply DATA4 26 I/O data bit 4 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad DATA5 27 I/O data bit 5 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad

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ISP1183

Low-power USB interface device with DMA

Table 2: Pin description

Symbol

[1]

Pin Type Description

…continued

DATA6 28 I/O data bit 6 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad DATA7 29 I/O data bit 7 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad V

DD(I/O)

30 - I/O power supply; add a decoupling capacitor of 0.1 µF

WAKEUP 31 I wake-up input (edge triggered, LOWto HIGH); generates a

remote wake-up from the suspend state; when not in use,

connect this pin to ground through a 10 kΩ resistor

3.3 V tolerant I/O pad

SUSPEND 32 O suspend state indicator output (4 mA)

3.3 V tolerant I/O pad

GND exposed

die pad

[1] Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals.

- ground supply; down bonded to the exposed die pad (heatsink); to be connected to the DGND during PCB layout

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8. Functional description

The ISP1183 is a full-speed USB interface device with up to 14 conﬁgurable endpoints. It has a fast general-purpose parallel interface for communication with many types of microcontrollers and microprocessors. It supports an 8-bit data bus with separate address and data. The block diagram is given in Figure 1.

The ISP1183 has 2462 bytes of internal FIFO memory that is shared among the enabled USB endpoints. The type and FIFO size of each endpoint can be individually conﬁgured, depending on the required packet size. Isochronous and bulk endpoints are double-buffered for increased data throughput.

ISP1183

Low-power USB interface device with DMA

The ISP1183 requires two supply voltages. The core voltage is supplied from V through an internal regulator, which transforms +5.0 V to +3.3 V when V powered. The I/O interface voltage is supplied from V

1.65 V to 3.6 V. The ISP1183 operates on a 6 MHz oscillator frequency.

, which can be

DD(I/O)

8.1 Analog transceiver

The transceiver is compliant with the directly interfaces with the USB cable through external termination resistors.

Universal Serial Bus Speciﬁcation Rev. 2.0

8.2 Philips SIE

The Philips Serial Interface Engine (SIE) implements the full USB protocol layer. It is completely hardwired for speed and needs no ﬁrmware intervention. The functions of this block include: synchronization pattern recognition, parallel-to-serial conversion, bit (de)stufﬁng, CRC checkingand generation, PacketIDentiﬁer (PID) veriﬁcation and generation, address recognition, and handshake evaluation and generation.

8.3 MMU and integrated RAM

The Memory Management Unit (MMU) and the integrated RAM provide the conversion between the USB speed (full-speed: 12 Mbit/s bursts) and the parallel interface to the microcontroller (maximum 11.1 Mbyte/s). This allows the microcontroller to read and write USB packets at its own speed.

BUS

. It

8.4 SoftConnect

The connection to USB is accomplished by pulling pin DP (for full-speed USB devices) HIGH through a 1.5 kΩ pull-up resistor. In the ISP1183, by default, the

1.5 kΩ pull-up resistor is integrated on-chip. The connection is established by a command sent from the external or system microcontroller. This allows the system microcontroller to complete its initialization sequence before deciding to establish connection with the USB. Reinitialization of the USB connection can also be performed without disconnecting the cable.

Remark: The tolerance of the internal resistors is 25 %. This is higher than the 5 % tolerance speciﬁed by the USB speciﬁcation. The overall voltage speciﬁcation for the connection, however, can still be met with a good margin. The decision to make use of this feature lies with the USB equipment designer.

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8.5 Bit clock recovery

The bit clock recovery circuit recovers the clock from the incoming USB data stream using a 4 x oversampling principle. It can track jitter and frequency drift as speciﬁed by the

8.6 Voltage regulator

A 5 V-to-3.3 V voltage regulator is integrated on-chip to supply the analog transceiver and internal logic. This voltage is available at pin V

1.5 kΩ pull-up resistor on pin DP. Alternatively, the ISP1183 provides SoftConnect technology through an integrated 1.5 kΩ pull-up resistor (see Section 8.4).

8.7 PLL clock multiplier

A 6 MHz-to-48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external components are required for the operation of the PLL.

8.8 PIO and DMA interfaces

USB Speciﬁcation Rev. 2.0

ISP1183

Low-power USB interface device with DMA

REG(3V3)

to supply an external

A generic Parallel I/O (PIO) interface is deﬁned for speed and ease-of-use. It also allows direct interfacing to most microcontrollers. To a microcontroller, the ISP1183 appears as a memory device with an 8-bit data bus and a 1-bit address bus. The ISP1183 supports nonmultiplexed address and data buses.

The ISP1183 can also be conﬁgured as a Direct Memory Access (DMA) slave device to allow more efﬁcient data transfer. One of the 14 endpoint FIFOs may directly transfer data to or from the local shared memory. The DMA interface can be independently conﬁgured from the PIO interface.

It can be directly interfaced to microprocessors or microcontrollers with I/O voltage range as low as 1.65 V.

8.9 V

indicator

BUS

The ISP1183 indicates the availability of V available(at pin V (at pin V

BUS

), pin VBUSDET_N will output HIGH. Pin VBUSDET_N will change from

HIGH-to-LOW level in approximately 2.5 ms to 3.5 ms. See Section 19.

8.10 Operation modes

The ISP1183 can be operated in several operation modes as given in Table 3.

Table 3: ISP1183 operation modes

Pin name Plug-out

state

BUS

DD(I/O)

WAKEUP X X L L L RESET_N X X L H H INT_N H L

0VX 5V5V5V

1.8 V 0 V 1.8 V 1.8 V 1.8 V

using the V

BUS

pin. When V

BUS

), pin VBUSDET_N will output LOW. When V

Dead state Reset state Plug-in state Normal state

[1]

HH-

BUS

is not available

BUS

[2]

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ISP1183

Low-power USB interface device with DMA

Table 3: ISP1183 operation modes

Pin name Plug-out

state

SUSPEND H L VBUSDET_N H L DATA Hi-Z L

[1] Not driven LOW.There is, however,no current ﬂow through the pads because no I/O supply voltage is

available. Therefore, no potential will develop at the output.

[2] During the normal operation, when V

the USB bus for 3 ms or more, a suspend interrupt is generated on pin INT_N. On receiving the suspend interrupt, the external processor issues a GOSUSP command to the device. Once the GOSUSP command is issued by the processor, the device starts to prepare itself togo to the suspend mode. During suspend, to reduce power consumption, the internal clocks can be shut down. Once the deviceis completely ready to go into the suspend mode, it will assert pin SUSPEND HIGH and go into the suspend mode. The typical time between the issuing of the GOSUSP command to the device and

the device asserting pin SUSPEND HIGH is approximately 2 ms. [3] Independent of the external reset. Depends only on the power-on reset. [4] On connecting the USB cable (V

approximately 2.5 ms to 3.5 ms.

8.11 Power supply

The ISP1183 is poweredfrom a single supply voltage, rangingfrom 4.0 V to 5.5 V. An integrated voltage regulator provides a 3.3 V supply voltage for the internal logic and the USB transceiver. This voltage is available at pin V external pull-up resistor on USB connection pin DP. See Figure 3.

…continued

Dead state Reset state Plug-in state Normal state

[1] [1] [1]

BUS

), pin VBUSDET_N will change from HIGH level to LOW level in

BUS

LLL

[3]

H -> L

[4]

Hi-Z Hi-Z -

is available, pin SUSPEND is LOW. If there is no activity on

REG(3V3)

for connecting an

The ISP1183 can also be operated from a 3.0 V to 3.6 V supply, as shown in

Figure 4. In this case, the internal voltage regulator is disabled and pin V

must be connected to V

BUS

REG(3V3)

DD(I/O)

ISP1183

004aaa295

DD(I/O)

1.65 V to 3.6 V

Fig 3. ISP1183 with a 4.0 V to 5.5 V supply. Fig 4. ISP1183 with a 3.0 V to 3.6 V supply.

4.0 V to 5.5 V

. For details, see Section 19.

BUS

ISP1183

004aaa296

18 30

BUS

REG(3V3)

DD(I/O)

3.0 V to 3.6 V

8.12 Crystal oscillator

The ISP1183 has a crystal oscillator designed for a 6 MHz parallel-resonant crystal (fundamental). A typical circuit is shown in Figure 5. Alternatively, an external clock signal of 6 MHz can be applied to input XTAL1, while leaving output XTAL2 open.

REG(3V3)

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ISP1183

Low-power USB interface device with DMA

Fig 5. Typical oscillator circuit.

The 6 MHz oscillator frequency is multiplied to 48 MHz by an internal PLL. In the suspend state, the crystal oscillator and the PLL are switched off to save

power. The oscillator operation is controlled by using bit CLKRUN in the Hardware Conﬁguration register. CLKRUN switches the oscillator on and off.

8.13 Power-on reset

The ISP1183 has an internal power-on reset (POR) circuit. The clock signal normally requires 3 ms to 4 ms to stabilize.

The triggering voltage of the POR circuit is 0.5 V nominal. A POR is automatically generated when V 50 µs.

DD(I/O)

0.5 V

XTAL2

ISP1183

004aaa294

goes below the trigger voltage for a duration longer than

DD(I/O)

POR

≤ 350 µs

XTAL1

18 pF

6 MHz

18 pF

2 ms

0 V

t1: clock is running t2: registers are accessible

004aaa390

Fig 6. POR timing.

POR

EXTERNAL CLOCK

004aaa365

Stable external clock available at A.

Fig 7. Clock with respect to the external POR.

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A hardware reset disables all USB endpoints and clears all Endpoint Conﬁguration registers (ECRs), except for the control endpoint that is ﬁxed and always enabled.

Section 10.3 explains how to (re)initialize endpoints.

9. Interrupts

Figure 8 shows the interrupt logic of the ISP1183. Each of the indicated USB events

is logged in a status bit of the Interrupt register. Corresponding bits in the Interrupt Enable register determine whether an event will generate an interrupt.

Interrupts can be masked globally using bit INTENA of the Mode register (see

Table 18).

The signaling mode of output INT is controlled by bit INTLVL of the Hardware Conﬁguration register (see Table 20). Default settings after reset is level mode. When pulse mode is selected, a pulse of 166 ns is generated when the OR-ed combination of all interrupt bits changes from logic 0 to logic 1.

(clear EPn interrupt; reading EPn status register will set this signal)

ISP1183

Low-power USB interface device with DMA

reset interrupt source

IERST

IESUSP

IERESM

IESOF

interrupt enable register

IEP0IN

IEP0OUT

suspend interrupt source

IEP14

...

EPn interrupt source

Fig 8. Interrupt logic.

(clear SUSPEND interrupt; reading interrupt register will set this signal)

(clear RESET interrupt; reading interrupt register will set this signal)

RESET

SUSPND

. . .

RESET

. . .

RESUME

SOF

EP14

...

EP0IN

EP0OUT

interrupt register

INTENA

device mode

INTLVL

hardware configuration

PULSE

GENERATOR

004aaa255

INT

Bits SUSPND, RESET, RESUME, SP_EOT, EOT and SOF are cleared when the Interrupt register is read. The endpoint bits (EP0OUT to EP14) are cleared when the associated Endpoint Status register is read.

Bit BUSTATUS follows the USB bus status exactly, allowing the ﬁrmware to get the current bus status when reading the Interrupt register.

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SETUP and OUT token interrupts are generated after the ISP1183 has acknowledgedthe associated data packet. In the bulk transfer mode, the ISP1183 will issue interrupts for every ACK received for an OUT token or transmitted for an IN token.

In the isochronous mode, an interrupt is issued on each packet transaction. The ﬁrmware is responsible for timing synchronization with the host. This can be done using the Pseudo Start-Of-Frame (PSOF) interrupt, enabled using bit IEPSOF in the Interrupt Enable register. If a Start-Of-Frame is lost, PSOF interrupts are generated every1 ms. This allowsthe ﬁrmware to keep data transfersynchronized with thehost. After three missed SOF events, the ISP1183 will enter the suspend state.

An alternative way of handling the isochronous data transfer is to enable both the SOF and PSOF interrupts and disable the interrupt for each isochronous endpoint.

ISP1183

Low-power USB interface device with DMA

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10. Endpoint description

Each USB device is logically composed of several independent endpoints. An endpoint acts as a terminus of a communication ﬂow between the host and the device. At design time, each endpoint is assigned a unique number (endpoint identiﬁer, see Table 4). The combination of the device address (given by the host during enumeration), the endpoint number, and the transfer direction allows each endpoint to be uniquely referenced.

The ISP1183 has 16 endpoints: endpoint 0 (control IN and OUT) plus 14 conﬁgurable endpoints, which can be individually deﬁned as interrupt, bulk or isochronous—IN or OUT. Each enabled endpoint has an associated FIFO, which can be accessed either using the parallel I/O interface or DMA.

10.1 Endpoint access

Table 4 lists the endpoint access modes and programmability. All endpoints support

I/O mode access. Endpoints 1 to 14 also support DMA access. FIFO DMA access is selected and enabled through bits EPDIX[3:0] and DMAEN of the DMA Conﬁguration register. A detailed description of the DMA operation is given in Section 11.

ISP1183

Low-power USB interface device with DMA

Table 4: Endpoint access and programmability

Endpoint identiﬁer

0 64 (ﬁxed) no yes no control OUT 0 64 (ﬁxed) no yes no control IN 1 to 14 programmable supported supported supported programmable

[1] The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes. [2] IN: input for the USB host (ISP1183 transmits); OUT: output from the USB host (ISP1183 receives). The data ﬂow direction is

determined by bit EPDIR in the Endpoint Conﬁguration register.

FIFO size (bytes)

[1]

Double buffering I/O mode

access

DMA mode access

Endpoint type

[2]

10.2 Endpoint FIFO size

The FIFO size determines the maximum packet size that the hardware can support for a given endpoint. Only enabled endpoints are allocated space in the shared FIFO storage, disabled endpoints have zero bytes. Table 5 lists programmable FIFO sizes.

The following bits in the Endpoint Conﬁguration register (ECR) affect FIFO allocation:

• Endpoint enable bit (FIFOEN)

• Size bits of an enabled endpoint (FFOSZ[3:0])

• Isochronous bit of an enabled endpoint (FFOISO).

Remark: Register changes that affect the allocation of the shared FIFO storage

among endpoints must not be made while valid data is present in any FIFO of the enabled endpoints. Such changes will render all FIFO contents undeﬁned.

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Table 5: Programmable FIFO size

FFOSZ[3:0] Nonisochronous Isochronous

0000 8 bytes 16 bytes 0001 16 bytes 32 bytes 0010 32 bytes 48 bytes 0011 64 bytes 64 bytes 0100 reserved 96 bytes 0101 reserved 128 bytes 0110 reserved 160 bytes 0111 reserved 192 bytes 1000 reserved 256 bytes 1001 reserved 320 bytes 1010 reserved 384 bytes 1011 reserved 512 bytes 1100 reserved 640 bytes 1101 reserved 768 bytes 1110 reserved 896 bytes 1111 reserved 1023 bytes

ISP1183

Low-power USB interface device with DMA

Each programmable FIFO can be independently conﬁgured through its ECR. The total physical size of all enabled endpoints (IN plus OUT), however, must not exceed 2462 bytes.

Table 6 shows anexample of a conﬁgurationﬁtting in the maximum available space of

2462 bytes. The total number of logical bytes in the example is 1311. The physical storage capacity used for double buffering is managed by the device hardware and is transparent to the user.

Table 6: Memory conﬁguration example

Physical size (bytes)

64 64 control IN (64-byte ﬁxed) 64 64 control OUT (64-byte ﬁxed) 2046 1023 double-buffered 1023-byte isochronous endpoint 16 16 16-byte interrupt OUT 16 16 16-byte interrupt IN 128 64 double-buffered 64-byte bulk OUT 128 64 double-buffered 64-byte bulk IN

Logical size (bytes)

Endpoint description

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10.3 Endpoint initialization

In response to the standard USB request Set Interface, the ﬁrmware mustprogram all 16 ECRs of the ISP1183 in sequence (see Table 4), whether the endpoints are enabled or not. The hardware will then automatically allocate FIFO storage space.

If all endpoints have been successfully conﬁgured, theﬁrmware mustreturn an empty packet to the control IN endpoint to acknowledge success to the host. If there are errors in the endpoint conﬁguration, the ﬁrmware must stall the control IN endpoint.

When reset by hardware or through the USB bus, the ISP1183 disables all endpoints and clears all ECRs, except for the control endpoint, which is ﬁxed and always enabled.

Endpoint initialization can be done at any time. It is, however, valid only after enumeration.

10.4 Endpoint I/O mode access

When an endpoint event occurs (a packet is transmitted or received), the associated endpoint interrupt bits (EPn) of the Interrupt register (IR) are set by the SIE. The ﬁrmware then responds to the interrupt and selects the endpoint for processing.

ISP1183

Low-power USB interface device with DMA

The endpoint interrupt bit is cleared when the Endpoint Status register (ESR) is read. The ESR also contains information on the status of the endpoint buffer.

For an OUT (= receive) endpoint, the packet length and the packet data can be read from the ISP1183 by using the Read Buffer command. When the whole packet is read, the ﬁrmware sends a Clear Buffer command to enable the reception of new packets.

For an IN (= transmit) endpoint, the packet length and data to be sent can be written to the ISP1183 by using the Write Buffer command. When the whole packet is written to the buffer, the ﬁrmware sends a Validate Buffer command to enable data transmission to the host.

10.5 Special actions on control endpoints

Control endpoints require special ﬁrmware actions. The arrival of a SETUP packet ﬂushes the IN buffer and disables the Validate Buffer and Clear Buffer commands for the control IN and OUT endpoints. The microcontroller needs to re-enable these commands by sending an Acknowledge Setup command to both control endpoints.

This ensures that the last SETUP packet stays in the buffer and that no packets can be sent back to the host until the microcontroller has explicitly acknowledged that it has seen the SETUP packet.

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11. DMA transfer

Direct Memory Access (DMA) is a method to transfer data from one location to another in a computer system, without intervention of the central processor unit (CPU). Many implementations of DMA exist. The ISP1183 supports two methods:

ISP1183

Low-power USB interface device with DMA

• 8237 compatible mode: based on the DMA subsystem of the IBM

computers (PC, AT and all its successors and clones); this architecture uses the Intel® 8237 DMA controller and has separate address spaces for memory and I/O

• DACK-only mode: based on the DMA implementation in some embedded RISC

processors, which has a single address space for both memory and I/O.

The ISP1183 supports DMA transfer for all 14 conﬁgurable endpoints (see Table 4). Only one endpoint can be selected at a time for DMA transfer. The DMA operation of the ISP1183 can be interleaved with normal I/O mode access to other endpoints.

The following features are supported:

• Single-cycle or burst transfers (up to 16 bytes per cycle)

• Programmable transfer direction (read or write)

• Programmable signal levels on pins DREQ and DACK.

11.1 Selecting an endpoint for DMA transfer

The target endpoint for DMA access is selected through bits EPDIX[3:0] in the DMA Conﬁguration register, see Table 7. The transfer direction (read or write) is automatically set bybit EPDIR in the associated ECR, to match the selected endpoint type (OUT endpoint: read; IN endpoint: write).

Asserting input DACK automatically selects the endpoint speciﬁed in the DMA Conﬁguration register, regardless of the current endpoint used for I/O mode access.

personal

Table 7: Endpoint selection for DMA transfer

Endpoint identiﬁer

1 0010 OUT: read IN: write 2 0011 OUT: read IN: write 3 0100 OUT: read IN: write 4 0101 OUT: read IN: write 5 0110 OUT: read IN: write 6 0111 OUT: read IN: write 7 1000 OUT: read IN: write 8 1001 OUT: read IN: write 9 1010 OUT: read IN: write 10 1011 OUT: read IN: write 11 1100 OUT: read IN: write 12 1101 OUT: read IN: write 13 1110 OUT: read IN: write 14 1111 OUT: read IN: write

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EPDIX[3:0] Transfer direction

EPDIR = 0 EPDIR = 1

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11.2 8237 compatible mode

The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the Hardware Conﬁguration register (see Table 20). The pin functions for this mode are shown in

Table 8.

Table 8: 8237 compatible mode: pin functions

Symbol Description I/O Function

DREQ DMA request O ISP1183 requests a DMA transfer DACK DMA acknowledge I DMA controller conﬁrms the transfer RD_N read strobe I instructs the ISP1183 to put data on the bus WR_N write strobe I instructs the ISP1183 to get data from the bus

The DMA subsystem of an IBM-compatible PC is based on the Intel 8237 DMA controller. It operates as a ‘ﬂy-by’ DMA controller: the data is not stored in the DMA controller, but it is transferred between an I/O port and a memory address. A typical example of the ISP1183 in the 8237-compatible DMA mode is given in Figure 9.

The 8237 has two control signals for each DMA channel: DREQ (DMA request) and DACK_N (DMA acknowledge). General control signals are HRQ (hold request) and HLDA (hold acknowledge). The bus operation is controlled using MEMR_N (memory read), MEMW_N (memory write), IOR_N (I/O read) and IOW_N (I/O write).

ISP1183

Low-power USB interface device with DMA

DATA[7:0]

ISP1183

RAM

DREQ

DACK

RD_N

WR_N

MEMR_N MEMW_N

DMA

CONTROLLER

8237

DREQ HRQ DACK_N

IOR_N IOW_N

Fig 9. ISP1183 in the 8237-compatible DMA mode.

HLDA

CPU

HRQ HLDA

004aaa291

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Philips Semiconductors

The following example shows the steps that occur in a typical DMA transfer:

1. The ISP1183 receives a data packet in one of its endpoint FIFOs; the packet

2. The ISP1183 asserts the DREQ signal requesting the 8237 for a DMA transfer.

3. The 8237 asks the CPU to release the bus by asserting the HRQ signal.

4. After completing the current instruction cycle, the CPU places the bus control

5. The8237 sets its address linesto 1234H and activates the MEMW_N and IOR_N

6. The8237 asserts DACK_Nto inform the ISP1183 that it will start a DMA transfer.

7. The ISP1183 places the byte or word to be transferred on the data bus lines

8. The 8237 waits one DMA clock period and then deasserts MEMW_N and

9. The ISP1183 deasserts the DREQ signal to indicate to the 8237 that DMA is no

10. The 8237 deasserts the DACK_N output indicating that the ISP1183 must stop

11. The 8237 places the bus control signals (MEMR_N, MEMW_N, IOR_N and

12. The CPU acknowledges control of the bus by deasserting HLDA. After activating

ISP1183

Low-power USB interface device with DMA

must be transferred to memory address 1234H.

signals (MEMR_N, MEMW_N, IOR_N and IOW_N) and the address lines in

three-state and asserts HLDA to inform the 8237 that it has control of the bus.

control signals.

because its RD_N signal was asserted by the 8237.

IOR_N. This latches and stores the byte or word at the desired memory location.

It also informs the ISP1183 that the data on the bus lines has been transferred.

longer needed. In the single cycle mode this is done after each byte or word, in

the burst mode following the last transferred byte or word of the DMA cycle.

placing data on the bus.

IOW_N) and the address lines in three-state and deasserts the HRQ signal,

informing the CPU that it has released the bus.

the bus control lines (MEMR_N, MEMW_N, IOR_N and IOW_N)and the address

lines, the CPU resumes the execution of instructions. For a typical bulk transfer, the above process is repeated 64 times, once for each

byte. After each byte, the address register in the DMA controller is incremented and the byte counter is decremented.

11.3 DACK-only mode

The DACK-only DMA mode is selected by setting bit DAKOLY in the Hardware Conﬁguration register (see Table 20). The pin functions for this mode are shown in

Table 9. A typical example of the ISP1183 in the DACK-only DMA mode is given in Figure 10.

Table 9: DACK-only mode: pin functions

Symbol Description I/O Function

DREQ DMA request O ISP1183 requests a DMA transfer DACK DMA acknowledge I DMA controller conﬁrms the transfer;

also functions as data strobe RD_N read strobe I not used WR_N write strobe I not used

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